CN100561906C - Realize the method and the device of clock active/standby changeover error-free - Google Patents
Realize the method and the device of clock active/standby changeover error-free Download PDFInfo
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- CN100561906C CN100561906C CNB2005100564838A CN200510056483A CN100561906C CN 100561906 C CN100561906 C CN 100561906C CN B2005100564838 A CNB2005100564838 A CN B2005100564838A CN 200510056483 A CN200510056483 A CN 200510056483A CN 100561906 C CN100561906 C CN 100561906C
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Abstract
The invention discloses a kind of method that realizes clock active/standby changeover error-free, each network element node all disposes two active and standby each other clock units in the communication system, this method comprises the steps: hardware line between two clock units is made that clock signal is sent mutually between the clock unit; Clock signal is controlled according to phase locked algorithm in the active clock unit, and the external reference clock signal of clock signal and input is consistent, and the clock signal of standby clock unit real-time tracking and locking active clock unit; Switch moment when clock active/standby takes place, clock signal is controlled with the controlling value of the active clock unit of tracking lock in the standby clock unit, the clock signal after making clock active/standby switch with switch before clock signal keep with homophase frequently.The invention also discloses a kind of device of realizing clock active/standby changeover error-free.Seamlessly transit when adopting this method and device that the communication equipment clock active/standby is switched, avoid service board to produce error code.
Description
Technical field
The present invention relates to a kind of Clock Synchronization Technology of the communications field, when especially relating to a kind of clock active/standby and switching, avoid service board to produce the method and the device of error code.
Background technology
In synchronous digital communications network, realizing by clock unit synchronously between each network element node in the net.The clock synchronization mode of extensive use at present is principal and subordinate's method of synchronization, and principal and subordinate's method of synchronization adopts the clock of a series of classifications, and each grade clock is all followed the tracks of the upper level clock, and maintenance and upper level clock synchronization.In network, generally all be provided with the net head that inserts reference clock, reference clock is a clock that ratio of precision is higher, remaining network element all is synchronized with reference clock.Principal and subordinate's method of synchronization is used very extensive in the public network system, and the advantage of this mode is a network stabilization, networking flexibility, and lower to the clock frequency requirement from node, control is simple; The shortcoming of this mode is very sensitive to the fault of reference clock and synchronous distribute links, and certain node breaks down on reference clock or link, can have influence on following node, and hand on, and causes the clock instability of whole network., do the multiple duplication except reference clock and link, slave unit developer's angle also needs the clock unit of node network element is done multiple duplication for this reason.
In the common communication equipment, clock unit is generally dual backup, promptly in a network element node, exists two clock units, and these two clock units are active and standby each other.Under the normal condition, active clock unit output clock, clock is not exported in the standby clock unit.In case the active clock unit breaks down, perhaps artificial Forced Switch, the standby clock unit changes the master into uses operating state, takes over the work of original active clock unit, the output clock.So just finished a process that clock active/standby is switched.
In the prior art, two clock units work alone, and do not have direct contact between the two.Two independently tracked separately identical external reference clock sources of clock unit, then through separately phase locked algorithm calculation process, calculate controlling value,, export the clock of and external reference clock source same frequency in order to control the VCXO (VCXO) in the clock unit separately.Though two clock units are followed the tracks of same clock source, because the otherness of hardware device, and the otherness handled of software algorithm operation, the clock frequency of two clock unit outputs is identical, and phase place but there are differences, and this phenomenon is called with homophase not frequently.
Therefore, when two clock unit generation masterslave switchovers, can cause damage to business.Because the output clock of two clock units is with homophase not frequently, during masterslave switchover, clock is transition smoothly, causes service board to produce error code, to such an extent as to the professional situation that hit or interruption occur.
Summary of the invention
The technical issues that need to address of the present invention provide a kind of method and device of realizing clock active/standby changeover error-free, seamlessly transit when adopting this method and device that the communication equipment clock active/standby is switched, avoid service board to produce error code, thereby improve the stability and the reliability of communication system.
In order to solve the problems of the technologies described above, the invention provides a kind of method that realizes clock active/standby changeover error-free, each network element node all disposes two active and standby each other clock units in the communication system, two clock units of each network element node all are connected with same external reference clock source, and this method comprises the steps:
(a), make each clock unit all can receive the clock signal of another clock unit with hardware line between two clock units;
(b) be in main when using state when a clock unit, this clock unit is controlled its clock signal according to phase locked algorithm, make the external reference clock signal that clock signal is followed the tracks of and locking is imported, another clock unit then is in stand-by state, the main clock signal of using the clock unit of state of real-time tracking and locking;
(c) when taking place, clock active/standby switches moment, the standby clock unit is controlled its clock signal with the controlling value of the active clock unit of tracking lock as current controlling value, the clock signal after making clock active/standby switch with switch before clock signal keep with homophase frequently.
Further, this method also has following characteristics: described step (b) is further divided into following steps:
(b1) be in main when using state when a clock unit, the main phase-locked loop closed loop work that is connected with the external reference clock source in this active clock unit, according to phase locked algorithm control clock signal, make the external reference clock signal that clock signal is followed the tracks of and locking is imported, the DPLL digital phase-locked loop that is connected with another clock unit in this active clock unit is in open loop situations simultaneously, does not work;
(b2) another clock unit is in stand-by state, DPLL digital phase-locked loop closed loop work in this standby clock unit, clock signal to the active clock unit carries out real-time tracking and locking, the central processing unit of standby clock unit reads and preserves the controlling value that interface register is followed the tracks of the active clock unit clock signal that obtains in the DPLL digital phase-locked loop according to certain time interval, main phase-locked loop is in open loop situations in this standby clock unit simultaneously, does not work.
Further, this method also has following characteristics: described step (c) is further divided into following steps:
(c1) when taking place, clock active/standby switches moment, the central processing unit of standby clock unit adopts the voltage-controlled magnitude of voltage of the controlling value of current preservation as its main phase-locked loop immediately, trigger the masterslave switchover of clock unit then, its main phase-locked loop closed loop work control clock signal, clock signal after making clock active/standby switch with switch before clock signal keep with homophase frequently, its DPLL digital phase-locked loop is in open loop situations simultaneously, does not work;
(c2) when taking place, clock active/standby switches moment, the central processing unit of active clock unit triggers the masterslave switchover of clock unit, its main phase-locked loop quits work, and its DPLL digital phase-locked loop closed loop is started working, and the clock signal of another clock unit is carried out real-time tracking and locking.
Further, this method also has following characteristics: the described time interval be 100 milliseconds～2 seconds in addition, the described time interval can be adjusted according to system features.
In order to solve the problems of the technologies described above, the invention provides a kind of device of realizing the clock active/standby changeover error-free method, this device comprises two identical clock units of the active and standby each other structure of each network element node configuration in the communication system, and two clock units of each network element node include the main phase-locked loop that is connected with same external reference clock source, the DPLL digital phase-locked loop that links to each other with the clock signal end of another clock unit; When the clock unit was in stand-by state, this DPLL digital phase-locked loop can be used for real-time tracking and the main clock signal of using the clock unit of state of locking.
Further, this device also has following characteristics: described DPLL digital phase-locked loop comprises phase discriminator, low pass filter, analog to digital converter, digital filter, digital to analog converter and VCXO, DPLL digital phase-locked loop is obtained the clock signal of another clock unit, through phase discriminator compare with the clock signal of another clock unit output digital phase demodulation value, change analog quantity into through low pass filter again, with analog quantity after analog-to-digital conversion, enter digital-to-analogue conversion and then control VCXO by digital filter output, and then the output signal of VCXO is transferred to phase discriminator compare with the clock signal of another clock unit, until finishing digital phase-locked process.
Further, this device also has following characteristics: described DPLL digital phase-locked loop also includes the interface register of the clock signal that is used to follow the tracks of another clock unit.
Further, this device also has following characteristics: described phase discriminator, interface register and digital filter are realized that by field programmable gate array this field programmable gate array adopts the XC2S600E chip in the Spartan2 of U.S. Sai Lingsi company (Xilinx.Inc.) series; Perhaps, described phase discriminator, interface register and digital filter also can be realized by digital signal processor.
Compared with prior art, the present invention has the following advantages:
(1) because the standby clock unit can real-time tracking and the clock signal of locking active clock unit among the present invention, and switch moment at clock active/standby, can control its clock signal with the controlling value of current tracking lock, the clock signal that makes clock active/standby switch front and back keeps with the frequency homophase, avoid service board to produce error code, thereby improve the stability and the reliability of whole communication system;
(2) since among the present invention the logical construction of implement device adopt field programmable gate array or digital signal processor to realize, therefore design convenient, flexiblely, upgrading need not additionally to increase cost.
Description of drawings
Fig. 1 is the functional unit theory diagram of implement device among the present invention;
Fig. 2 is the timing loop state transition diagram of implementation method among the present invention.
Embodiment
Realize the method and the device of clock active/standby changeover error-free for understanding the present invention in depth. the present invention is described in detail below in conjunction with drawings and the specific embodiments.
In communication system, each network element node configuration has two identical clock units of active and standby each other structure, realize clock active/standby changeover error-free, must guarantee moment of switching at clock active/standby, provide the clock of a continous-stable to export to service board, service board could can not take place to produce error code than great fluctuation process because of clock.In order to achieve the above object, should consider that at first two clock units keep synchronously, when necessarily requiring clock unit to be operated in stand-by state, the clock of real-time tracking active clock unit is accomplished with the frequency homophase.
Implement device of the present invention is made up of two identical clock units of active and standby each other structure, the structure of each clock unit as shown in Figure 1, include the main phase-locked loop that is connected with same external reference clock source, the DPLL digital phase-locked loop that links to each other with the clock signal end of another clock unit, main phase-locked loop is by phase discriminator, dispose central processing unit (the abbreviating CPU as) control unit of phase locked algorithm, digital to analog converter (abbreviating D/A converter as), VCXO (abbreviating VCXO as) is formed, DPLL digital phase-locked loop is then by phase discriminator, low pass filter, analog to digital converter (abbreviating A/D converter as), digital filter, D/A converter and VCXO form, wherein, because main phase-locked loop and DPLL digital phase-locked loop are through being set to interlocking, promptly can not work simultaneously, therefore to can be two loops shared for the D/A converter of two loops and VCXO, promptly at D/A converter and CPU control unit, a selector switch is set between the digital filter, is used for switching moment and switches main phase-locked loop and DPLL digital phase-locked loop at clock active/standby.DPLL digital phase-locked loop also is provided with an interface register that is used to follow the tracks of the clock signal of another clock unit.In DPLL digital phase-locked loop, phase discriminator, interface register and digital filter are by field programmable gate array (Field Programmable Gate Array, abbreviate FPGA as) realize that this example adopts the XC2S600E chip in the Spartan2 of U.S. Sai Lingsi company (Xilinx.Inc.) series; Or described phase discriminator, interface register and digital filter are realized by digital signal processor, also can realize by software mode.
In conjunction with illustrated in figures 1 and 2, when clock cell operation during at standby mode, main phase-locked loop open loop quits work, and is inoperative to actual phase; DPLL digital phase-locked loop is in closed-loop working state, be used for following the tracks of the clock signal of another clock unit (being the active clock unit), DPLL digital phase-locked loop is with the clock signal of the active clock unit that obtained, after passing through phase discriminator and the clock signal of another clock unit being compared, export digital phase demodulation value to low pass filter and change analog quantity into, this analog quantity is through behind the A/D converter, obtain the voltage-controlled value of D/A by digital filter, directly export the voltage-controlled value of D/A to D/A converter, and then control VCXO, and then the output signal of VCXO is transferred to phase discriminator compare with the clock signal of active clock unit, until finishing the digital phase-locked loop process; In the process of digital phase-locked loop, the CPU control unit of main phase-locked loop is followed the tracks of the controlling value of the active clock unit clock signal that obtains according to certain time interval fetch interface register, and preserved reference control value when being used as that clock active/standby takes place and switching, this time interval is 100 milliseconds～2 seconds, should the time interval tentatively be set to 1 second in the present embodiment, can do suitably to adjust according to system features, this is in order to obtain DPLL digital phase-locked loop controlling value stably (after DPLL digital phase-locked loop is finished tracking lock to the clock signal of active clock unit, the DPLL digital phase-locked loop controlling value of this standby clock unit is identical with the main phase-locked loop controlling value of active clock unit), because when normal operation, the DPLL digital phase-locked loop controlling value is a value more stably, changes very little relatively; And if read this value in the moment of switching, then this value may depart from stationary value, can not reflect the working condition of active clock unit exactly.
When clock cell operation during at master mode, main phase-locked loop is closed loop work, the external reference clock signal at first is converted to the digital signal amount by phase discriminator, send to the CPU control unit, the CPU control unit calculates the voltage-controlled value of D/A by phase locked algorithm, the voltage-controlled value of D/A directly exports D/A converter to digital quantity is converted to analog quantity, regulate and control VCXO by the magnitude of voltage of analog quantity then, again the output signal of VCXO is transferred to phase discriminator and compare, until Frequency Phase Lock with the external reference clock signal; And the DPLL digital phase-locked loop open loop quits work.
When clock masterslave switchover moment, the CPU control unit that is in the clock unit of stand-by state before this adopts the voltage-controlled magnitude of voltage of the reference control value of current preservation as its main phase-locked loop immediately, trigger clock unit masterslave switchover in logic then, selector switch switches main phase-locked loop and DPLL digital phase-locked loop, this clock unit enters the main state of using, its main phase-locked loop becomes closed loop from open loop, by the normal phase-locked operation of phase locked algorithm control beginning, and beginning clock signal, because the initial value of its voltage-controlled magnitude of voltage is the reference control value that the CPU control unit is preserved before switching, therefore the clock signal that makes clock active/standby switch front and back keeps avoiding service board to produce error code with the frequency homophase; And its DPLL digital phase-locked loop becomes open loop from closed loop, quits work.
Meanwhile, be in main clock unit before this and stop clock signal, trigger clock unit masterslave switchover in logic with state, selector switch switches main phase-locked loop and DPLL digital phase-locked loop, this clock unit enters stand-by state, and its main phase-locked loop becomes open loop from closed loop, quits work; And its DPLL digital phase-locked loop becomes closed loop from open loop, real-time tracking and lock the clock signal of another clock unit (after being masterslave switchover, being in main clock unit with state).
The present invention causes service board to produce error code easily in the time of solving in the communication system rearranging main/slave clock effectively, and causes the difficult problem of switching services or interruption, is specially adapted to the clock system of principal and subordinate's method of synchronization work of present extensive use.
Claims (11)
1, a kind of method that realizes clock active/standby changeover error-free, each network element node all disposes two active and standby each other clock units in the communication system, two clock units of each network element node all are connected with same external reference clock source, it is characterized in that this method comprises the steps:
(a), make each clock unit all can receive the clock signal of another clock unit with hardware line between two clock units;
(b) be in main when using state when a clock unit, this clock unit is controlled its clock signal according to phase locked algorithm, make the external reference clock signal that clock signal is followed the tracks of and locking is imported, another clock unit then is in stand-by state, the main clock signal of using the clock unit of state of real-time tracking and locking;
(c) when taking place, clock active/standby switches moment, the standby clock unit is controlled its clock signal with the controlling value of the active clock unit of tracking lock as current controlling value, the clock signal after making clock active/standby switch with switch before clock signal keep with homophase frequently.
2, the method for realization clock active/standby changeover error-free according to claim 1 is characterized in that, described step (b) is further divided into following steps:
(b1) be in main when using state when a clock unit, the main phase-locked loop closed loop work that is connected with the external reference clock source in this active clock unit, according to phase locked algorithm control clock signal, make the external reference clock signal that clock signal is followed the tracks of and locking is imported, the DPLL digital phase-locked loop that is connected with another clock unit in this active clock unit is in open loop situations simultaneously, does not work;
(b2) another clock unit is in stand-by state, DPLL digital phase-locked loop closed loop work in this standby clock unit, clock signal to the active clock unit carries out real-time tracking and locking, the central processing unit of standby clock unit reads and preserves the controlling value that interface register is followed the tracks of the active clock unit clock signal that obtains in the DPLL digital phase-locked loop according to certain time interval, main phase-locked loop is in open loop situations in this standby clock unit simultaneously, does not work.
3, the method for realization clock active/standby changeover error-free according to claim 2 is characterized in that, described step (c) is further divided into following steps:
(c1) when taking place, clock active/standby switches moment, the central processing unit of standby clock unit adopts the voltage-controlled magnitude of voltage of the controlling value of current preservation as its main phase-locked loop immediately, trigger the masterslave switchover of clock unit then, its main phase-locked loop closed loop work control clock signal, clock signal after making clock active/standby switch with switch before clock signal keep with homophase frequently, its DPLL digital phase-locked loop is in open loop situations simultaneously, does not work;
(c2) when taking place, clock active/standby switches moment, the central processing unit of active clock unit triggers the masterslave switchover of clock unit, its main phase-locked loop quits work, and its DPLL digital phase-locked loop closed loop is started working, and the clock signal of another clock unit is carried out real-time tracking and locking.
4, the method for realization clock active/standby changeover error-free according to claim 3 is characterized in that: the described time interval is 100 milliseconds～2 seconds.
5, according to the method for claim 3 or 4 described realization clock active/standby changeover error-frees, it is characterized in that: the described time interval can be adjusted according to system features.
6, a kind of device of method according to claim 1 of realizing, this device comprises two identical clock units of the active and standby each other structure of each network element node configuration in the communication system, two clock units of each network element node include the main phase-locked loop that is connected with same external reference clock source, it is characterized in that: each clock unit also includes DPLL digital phase-locked loop, and the clock signal end of each clock unit all is connected with the DPLL digital phase-locked loop of another clock unit; When the clock unit was in stand-by state, this DPLL digital phase-locked loop can be used for real-time tracking and the main clock signal of using the clock unit of state of locking.
7, according to the device shown in the claim 6, it is characterized in that: described DPLL digital phase-locked loop comprises phase discriminator, low pass filter, analog to digital converter, digital filter, digital to analog converter and VCXO, DPLL digital phase-locked loop is obtained the clock signal of another clock unit, through phase discriminator compare with the clock signal of another clock unit output digital phase demodulation value, change analog quantity into through low pass filter again, with analog quantity after analog-to-digital conversion, enter digital-to-analogue conversion and then control VCXO by digital filter output, and then the output signal of VCXO is transferred to phase discriminator compare with the clock signal of another clock unit, until finishing digital phase-locked process.
8, device according to claim 7 is characterized in that: described DPLL digital phase-locked loop also includes the interface register of the clock signal that is used to follow the tracks of another clock unit.
9, device according to claim 8 is characterized in that: described phase discriminator, interface register and digital filter are realized by field programmable gate array.
10, device according to claim 9 is characterized in that: described field programmable gate array adopts the XC2S600E chip in the U.S. Spartan2 of the Sai Lingsi company series.
11, device according to claim 8 is characterized in that: described phase discriminator, interface register and digital filter are realized by digital signal processor.
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| CNB2005100564838A CN100561906C (en) | 2005-03-24 | 2005-03-24 | Realize the method and the device of clock active/standby changeover error-free |
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| CN101132247B (en) * | 2007-09-28 | 2011-04-06 | 中兴通讯股份有限公司 | Method for implementing main clock phase alignment and device thereof |
| CN104717090B (en) * | 2013-12-17 | 2019-07-02 | 中兴通讯股份有限公司 | Interface signal is active and standby mutually to send processing method and system |
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