CN1299464C - Method and device for realizing main backup of clock in synchronizing system - Google Patents
Method and device for realizing main backup of clock in synchronizing system Download PDFInfo
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- CN1299464C CN1299464C CNB031318053A CN03131805A CN1299464C CN 1299464 C CN1299464 C CN 1299464C CN B031318053 A CNB031318053 A CN B031318053A CN 03131805 A CN03131805 A CN 03131805A CN 1299464 C CN1299464 C CN 1299464C
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Abstract
The present invention relates to a device for realizing main and backup clocks in a synchronization system, which comprises a switching circuit for mains and backups. The present invention is characterized in that The switching circuit for mains and backups comprises a main locking circuit, a main removing circuit, a switching signal generation circuit and a treatment circuit of switching and outputting signals. The present invention provides a simple and reliable method and a device for switching the mains and the backups, which compensates the defects of other switching methods for switching the mains and the backups. The present invention not only can avoid the condition that two panels are simultaneously used as the mains, but also can eliminate the phase oscillation of main and backup states, and at the same time, time delay for switching the mains and the backups is reduced as far as possible.
Description
Technical field
The present invention relates to a kind of main and standby rearranging method and device, relate in particular to the method and apparatus of realizing active and standby usefulness of synchronised clock (Hot Spare) and hot-swap in the synchro system of communication field.
Background technology
The master-slave redundancy design has been widely used in the communication system devices, and especially the warm standby function of its realization has improved the reliability and stability of equipment to a large extent.In the synchro system of communication field, all veneers or subsystem all are operated under its synchronised clock, so clock board is as the core in the synchro system, and its reliability is even more important, and therefore must take masterslave switchover to handle to clock board.
At present, in synchro system, realize that the apparatus and method that clock active/standby is switched roughly have following several situation:
1, clock board adopts the phase-lock mode of loose coupling,
Owing to reasons such as phase resolution and phase place randomnesss, the phase difference of master/backup clock plate may be the arbitrary value in voltage controlled oscillator (hereinafter to be referred as VCO) the output frequency half period, so, can't accomplish during masterslave switchover that real phase place is continuous, and master/backup clock plate output clock phase is inconsistent, as adopting the VCO of 16.384MHZ in the program controlled switching system, the output clock phase difference of its master/backup clock plate is roughly just between 0～30ns, if carry out masterslave switchover, the variation of the clock duty cycle of a clock cycle will take place, just taken place so phase place is discontinuous, promptly enable to accomplish active and standby seamless switching, promptly mainly close and standby output does not have the time interval between opening, also can't stop the generation of the discontinuous situation of above-mentioned phase place, caused the masterslave switchover implementation procedure to delay time with output.
2, adopt the mode of long and short hands to realize masterslave switchover, the shortcoming of the method is to need connector to cooperate;
3, adopt simple JK flip-flop or the interlocking of rest-set flip-flop state, the method is easy to generate the vibration of activestandby state;
4, a kind of active/standby changeover apparatus of in the patent No. is 98118143 patent, putting down in writing, this device is the output signal of differential level with the masterslave switchover command conversion, output to the differential formation unit on the bus mother board then, being used for that the masterslave switchover control signal is carried out jitter elimination handles, and form and to enable control signal, the switching device between active and standby part is carried out switch control.Because it is switched and can only pass through a certain veneer, active and standby selection also can only if this plate breaks down, then can't be finished masterslave switchover, so this device is not accomplished real hot-swap by to this plate operation.
Summary of the invention
To the objective of the invention is the shortcoming that exists in the prior art in order overcoming, propose a kind of method and apparatus that clock active/standby is used of realizing in synchro system, the state that utilize master/slave switch circuit to finish in the system two main and standby boards dead-beats, not to have a time-delay is switched.
In order to achieve the above object, the invention provides a kind of method that clock active/standby is used that realizes in synchro system, this method may further comprise the steps:
Primary, spare clock board provides frequency identical clock signal mutually;
Adopt the active and standby vibration in the anti-locking system of lock main circuit;
Adopt with the main circuit of eliminating and realize that two boards is active and standby and use the function interlocking;
Adopt changeover signal to produce circuit and produce changeover signal;
And carry out delay process to switching output signal.
The present invention also provides a kind of device that clock active/standby is used of realizing in synchro system, comprise master/slave switch circuit, it is characterized in that: this master/slave switch circuit comprises the lock main circuit, produces circuit, switches output signal processing circuit, wherein with main elimination circuit, changeover signal
One lock main circuit is used for synchro system as main state locking with veneer;
The together main circuit of eliminating, being used to avoid two veneers is main generation with state condition simultaneously
One changeover signal produces circuit, is used to produce the control signal of switching of veneer;
One switches output signal processing circuit, is used for realizing handling switching output signal.
Plate is switched output signal deliver to described lock main circuit and described respectively with the main circuit of eliminating, after treatment, produce circuit with switching enable signal and plate signal on the throne being delivered to described changeover signal, produce this plate and switch output signal, described plate switched output signal and delivered to the described output signal processing circuit of switching, and finishes switching the processing of output signal.
The present invention proposes the method and apparatus that a kind of simple and reliable active and standby usefulness is switched, this method and apparatus has remedied the deficiency of other main and standby rearranging method, both can avoid two plates is the situation generation of main usefulness simultaneously, can eliminate the phase oscillation of activestandby state again, reduce the time-delay of masterslave switchover simultaneously as far as possible.
Below in conjunction with embodiment, and be elaborated, so that purpose of the present invention, feature and advantage are had more deep understanding with reference to accompanying drawing.
Description of drawings
Fig. 1 is the master/slave switch circuit theory diagram.
Fig. 2 is lock main circuit schematic diagram.
Fig. 3 is with the main circuit theory diagrams of eliminating.
Fig. 4 produces circuit theory diagrams for changeover signal.
Fig. 5 is for switching the output signal processing circuit schematic diagram.
Embodiment
As shown in Figure 1, be master/slave switch circuit theory diagram provided by the present invention, active/standby changeover apparatus involved in the present invention, the master/slave switch circuit that it adopted comprise lock main circuit 101, with main eliminate circuit 102, switch window control circuit 103, changeover signal produces circuit 104 and switches output signal processing circuit 105.
Lock main circuit 101 is used for synchro system as main state locking with veneer.In case after certain board status is main using in the system, cause taking place masterslave switchover unless have artificial control or system to break down, otherwise this plate is main usefulness, can prevents that like this locking system produces active and standby vibration because of disturbing always;
With the main circuit 102 of eliminating, being used to avoid two veneers is main generation with state condition simultaneously.All be operated in main when using state when two veneers appear in the system in (as competition and factor such as interference) for a certain reason, this circuit drives immediately and switches, making wherein, a plate becomes main using, another piece plate becomes standby, from two plates is main use a certain block of plate and become the standby time interval and can adjust simultaneously, can finish in several nanoseconds the soonest;
Switch window control circuit 103, be used to realize to switching the control of window, i.e. the time period of generation is switched in control, only just can switch in this time period.That says here has switched several situations, and a kind of is that button is switched in operation, and another kind is to send out on the backstage to switch order, also has a kind ofly to be the main board fault and to reset.This circuit can guarantee that two veneers switch when phase place is identical;
Changeover signal produces circuit 104, is used to produce the control signal of switching of veneer external interface device.Two interlocking signals are arranged between the active and standby plate, and it is continuous to cross one another, and a signal is high, and another signal must be for low, and the sign that single board main/standby is used is determined by the state of these two signals.The output signal of switching of this plate is adopted in the control of veneer external interface device, for main board, make interface device open-minded; For standby plate, interface device is disconnected.Masterslave switchover at first changes the output signal level of switching of main board, makes it become stand-by state from main with state; After standby plate receives the change of this level, drive negater circuit immediately, the output signal of switching of this plate is changed, thereby make this plate become the main state of using by stand-by state.From the variation of activestandby state as can be seen, exist and switch the gap, be to have time-delay between the masterslave switchover output signal, this implementation with circuit is relevant, circuit all among the design are finished with programming device, adopt different programming devices, the time-delay between the masterslave switchover output signal also can be different, can select the programming device of low time delay as far as possible.
Switch output signal processing circuit 105, be used for realizing handling switching output signal.Because the output signal of switching of this plate is adopted in the control of veneer external interface device, by carrying out suitable processing to switching output signal, can be 0 nanosecond with the actual clearance control of switching, and does not promptly have time-delay; That is to say that although there is the time-delay of switching output signal between the main standby plate, the time-delay on the main standby plate between the signal of control interface device has not almost had.The output signal of switching after treatment just is used for the control interface device, and the interlocking signal that directly is used for switching is not have treated signal.
Wherein, plate another veneer of (in the system with respect to this plate) is switched output signal deliver to described lock main circuit 101 and described respectively with the main circuit 102 of eliminating, carry out this plate master by described lock main circuit and lock, and two plates in the system are all mainly get rid of processing with the main circuit of eliminating with the situation of state by described with state; Order is switched control signal and is delivered to the described window control circuit 103 of switching, after switching time section control and treatment, with plate is switched enable signal and to plate signal on the throne and foregoing main through locking, with main eliminate after handling to the plate changeover signal, deliver to described changeover signal and produce circuit 104; After described changeover signal generation circuit 104 is received above-mentioned five signals, produce this plate and switch output signal, and deliver to the described output signal processing circuit 105 of switching, and remedy the time-delay that the masterslave switchover signal produces, making between the signal of two plate control interface devices does not have time-delay.
Below by a specific embodiment, describe technical scheme of the present invention in detail.
In the present embodiment, carry out main and may further comprise the steps:
1. primary, spare clock board provides frequency identical clock signal mutually, is synchronized with the main veneer of using to guarantee standby board;
2. adopt the lock main circuit, the active and standby vibration in the anti-locking system;
3. adopt with the main circuit of eliminating, guarantee that two boards is active and standby to use the function interlocking;
4. produce active and standby plate changeover signal;
5. the changeover signal to above-mentioned output carries out delay process.
Wherein, can switch in that phase place is identical, also need before the 4th step, add that is switched a window controlled step, the time period of switching with control in order to guarantee two veneers.
The specific implementation circuit of the master/slave switch circuit in the present embodiment is described in detail as follows:
As shown in Figure 2, be the lock main circuit schematic diagram in the master/slave switch circuit of the present invention, lock main circuit 101 is made up of a not gate 201 and one or 202, its course of work is: will switch output signal 10 to plate and deliver to this plate, switch output signal 20 after not gate 201 negates with this plate, deliver to together or door 202 mutually or, by or door 202 outputs deliver to changeover signal and produce circuit.
As shown in Figure 3, be the same main circuit theory diagrams of eliminating in the master/slave switch circuit of the present invention, its course of work is: plate is switched output signal 10 delivers to this plate, with this plate switch output signal 20 through or 301 mutually or after deliver to the input of d type flip flop 302; Deliver to the clock control end of d type flip flop 302 mutually behind the XOR through XOR gate 303 with the main plate position signal 30 of eliminating clock 40 and this plate; Wherein, be that control two plates are that the master uses the clock in the time interval of switching simultaneously with the main clock of eliminating, this clock frequency can suitably be adjusted.The plate position signal of two plates is inconsistent, but it is identical with main elimination clock frequency, eliminate in the circuit with main described, opposite fully by the signal that produces behind the XOR, this trigger is spaced apart half of same main elimination clock cycle in the triggered time of two boards like this, the output of d type flip flop is delivered to changeover signal and is produced circuit, if two plates take place is the phenomenon of main usefulness simultaneously, promptly plate being switched output signal and this plate, to switch output signal level identical, all be 0, when the clock control of d type flip flop brought out existing rising edge, d type flip flop was output as 0 and delivers to changeover signal and produce circuit, it is standby that this plate is become, thereby avoided two plates to be all main phenomenon with state.
Switch window control circuit 103 in the master/slave switch circuit, to occur in definite time period in order making to switch, especially when two plate phase places are identical, to switch, the minimum that influences of system, therefore, set and to switch window to control the switching time section be particularly necessary.Switching window can be produced by following dual mode like this:
1, all export the 8K frame head at two veneers and give, and standby plate is during with the 8K frame head phase alignment of main board input, switch window and just open position at the 8K frame head to plate;
2, suppose that the main clock phase difference is θ to the maximum, always from slowly changing between 0～θ, so when phase difference was 0, system produced a negative pulse, this negative pulse can keep microsecond level or Millisecond to phase difference, and the width of this negative pulse promptly is to switch window.Utilization switch window switch control only need to switch order and switch window by or door mutually or after, deliver to changeover signal generation circuit.
As shown in Figure 4, be that the changeover signal in the master/slave switch circuit of the present invention produces circuit theory diagrams, this circuit is used for producing this plate and switches output signal, comprises a NAND gate 401 and one or 402.Its course of work is: the input of NAND gate 401 has output signal 70, this plate of switching window control circuit output signal 50, lock main circuit output signal 60, same main elimination circuit to pull out partitioned signal 80 and fault-signal 90, the output signal of NAND gate 401 with to plate signal 100 on the throne, switch that enable signal 110 is delivered to or door 402, should or the output of door be the changeover signal that this circuit produces.
For example, when any one input of NAND gate is 0, be output as 1, this plate becomes standby.
The above-mentioned partitioned signal that pulls out can adopt the hour hand that contacts with backboard to realize, also can be when pulling out plate spanner by veneer move and realize.Must add other constraints in addition, as switch enable signal, can pass through the software masking masterslave switchover; To plate signal on the throne,, switch just meaningless if not on the throne to plate.
As shown in Figure 5, for switching the output signal processing circuit schematic diagram in the master/slave switch circuit of the present invention, this circuit designs for the time-delay of controlling veneer external interface device break-make, usually when switching, when main board begins to become standby plate, standby plate can be after time-delay, just can become main board, can can cause equally that so also two plates are the generation of spare condition simultaneously, and all disconnections this moment of the interface device of veneer, outwards do not export clock, though the time is very short, but, caused the interrupted of clock signal because interface device disconnects.The course of work of this circuit is: this plate is switched output signal 20 after the delay process of time delay module 501, again with this signal itself through with door 502 with, output interface device drive signal 120, remedy the time-delay that the masterslave switchover signal produces, because the time that the clock signal of active and standby plate output is interrupted is relevant with the time-delay of interface device, so by selecting suitable interface device, can guarantee to export the continuity of clock, wherein the time-delay deadline of time delay module can suitably be provided with.
Embodiment described above is illustrative and not restrictive; the content that protection scope of the present invention is put down in writing with claim is as the criterion; any variation of having done under the situation that does not break away from the spirit and scope of the present invention and modification are all within protection scope of the present invention.
Claims (13)
1. realize the method that clock active/standby is used for one kind in synchro system, this method may further comprise the steps:
Primary, spare clock board provides frequency identical clock signal mutually;
The active and standby vibration in the anti-locking system of circuit is locked in employing;
Adopt with the main circuit of eliminating and realize that two boards is active and standby and use the function interlocking;
Foundation is switched window control and is switched the time of origin section;
Adopt changeover signal to produce circuit and produce changeover signal; And
Handle switching output signal.
2. the method that the realization clock active/standby is used in synchro system as claimed in claim 1, it is characterized in that described foundation switches the step that the time of origin section is switched in window control, comprise when all export the 8K frame head at two veneers of system and giving plate, and under the situation of standby plate with the 8K frame head phase alignment of main board input, switch window and open position at the 8K frame head.
3. the method that the realization clock active/standby is used in synchro system as claimed in claim 1, it is characterized in that described foundation switches the step that the time of origin section is switched in window control, to switch order with switch window by or door mutually or after, deliver to described changeover signal generation circuit.
4. in synchro system, realize the device that clock active/standby is used for one kind, comprise master/slave switch circuit, it is characterized in that: this master/slave switch circuit comprise the lock main circuit, with main eliminate circuit, switch the window control circuit, changeover signal produces circuit, switches output signal processing circuit, wherein a lock main circuit is used for synchro system as main state locking with veneer;
The together main circuit of eliminating, being used to avoid two veneers is main generation with state condition simultaneously
One changeover signal produces circuit, is used to produce the control signal of switching of veneer external interface device;
One switches the window control circuit, is used to control the time period of switching, and can switch at same phase to guarantee two veneers;
One switches output signal processing circuit, is used for realizing handling switching output signal;
Plate is switched output signal deliver to described lock main circuit and described respectively with the main circuit of eliminating, after treatment, produce circuit with switching enable signal and plate signal on the throne being delivered to described changeover signal, produce this plate and switch output signal, described plate switched output signal and delivered to the described output signal processing circuit of switching, and finishes switching the processing of output signal.
5. the device that the realization clock active/standby is used in synchro system as claimed in claim 4, it is characterized in that described lock main circuit comprise one or and a not gate, plate is switched after output signal delivers to this plate lock main circuit, with switch through this plate of not gate negate output signal mutually or, by or door output deliver to described changeover signal and produce circuit.
6. the device that the realization clock active/standby is used in synchro system as claimed in claim 4, it is characterized in that described with main eliminate circuit comprise one or, an XOR gate and a d type flip flop, to plate switch output signal deliver to this plate with main eliminate circuit after, with this plate switch output signal mutually or after deliver to the d type flip flop input: deliver to d type flip flop clock control end behind the XOR with main elimination clock mutually with the plate position signal of this plate.
7. the device that the realization clock active/standby is used in synchro system as claimed in claim 4, it is characterized in that described changeover signal produce circuit comprise a NAND gate and one or, wherein the input of NAND gate comprises and switches window control circuit output signal, lock main circuit output signal, pulls out partitioned signal and fault-signal with main output signal, this plate of eliminating circuit, the output signal of NAND gate with to plate signal on the throne, switch enable signal mutually or after export and switch control signal.
8. the device that the realization clock active/standby is used in synchro system as claimed in claim 7 is characterized in that any one input of described NAND gate is at 0 o'clock, is output as 1, and this moment, this plate became stand-by state.
9. the device of realizing that in synchro system clock active/standby is used as claimed in claim 7 is characterized in that the described hour hand acquisition of partitioned signal from contact with backboard of pulling out.
10. the device that the realization clock active/standby is used in synchro system as claimed in claim 7 is characterized in that described spanner action acquisition of pulling out partitioned signal by veneer.
11. the device that the realization clock active/standby is used in synchro system as claimed in claim 4, it is characterized in that the described output signal processing circuit of switching, comprise a time delay module and one and door, wherein this plate is switched output signal after the delay process of time delay module, again with this signal itself and, output interface device drive signal.
12. the device of realizing that in synchro system clock active/standby is used as claimed in claim 11 is characterized in that the delay time of the described time delay module of delay adjustments of time of interrupting according to the clock signal of active and standby plate output and interface device.
13. the device of realizing that in synchro system clock active/standby is used as claimed in claim 4 is characterized in that described master/slave switch circuit also comprises to switch the window control circuit, is used to realize to switching the control of time of origin section.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB031318053A CN1299464C (en) | 2003-06-04 | 2003-06-04 | Method and device for realizing main backup of clock in synchronizing system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB031318053A CN1299464C (en) | 2003-06-04 | 2003-06-04 | Method and device for realizing main backup of clock in synchronizing system |
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| CN1553622A CN1553622A (en) | 2004-12-08 |
| CN1299464C true CN1299464C (en) | 2007-02-07 |
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| CNB031318053A Expired - Fee Related CN1299464C (en) | 2003-06-04 | 2003-06-04 | Method and device for realizing main backup of clock in synchronizing system |
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Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100338967C (en) * | 2005-05-19 | 2007-09-19 | 北京北方烽火科技有限公司 | Method and apparatus for realizing clock redundancy back-up in WCDMA system base station |
| CN100428647C (en) * | 2005-05-27 | 2008-10-22 | 华为技术有限公司 | Method for keeping uniform of main/stand-by clock of communication system |
| CN103051404B (en) * | 2011-10-12 | 2017-02-01 | 中兴通讯股份有限公司 | Method of preventing synchronizing network topology from generating shaking, and clock synchronizer |
| CN102361456B (en) * | 2011-10-26 | 2013-07-03 | 华亚微电子（上海）有限公司 | Clock phase alignment and adjustment circuit |
| CN107948106A (en) * | 2017-11-23 | 2018-04-20 | 盛科网络（苏州）有限公司 | A kind of method and apparatus of the main power board of selection for interchanger |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4821227A (en) * | 1984-08-18 | 1989-04-11 | Mitsubishi Denki Kabushiki Kaisha | Plesiochronous matching apparatus |
| JPH0897750A (en) * | 1994-09-22 | 1996-04-12 | Nec Commun Syst Ltd | Clock reception distribution system |
| CN2383274Y (en) * | 1999-08-24 | 2000-06-14 | 深圳市中兴通讯股份有限公司 | Main spare plate switching device for electronic communication system |
| CN1092864C (en) * | 1998-08-25 | 2002-10-16 | 华为技术有限公司 | Master backup reverse device |
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2003
- 2003-06-04 CN CNB031318053A patent/CN1299464C/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4821227A (en) * | 1984-08-18 | 1989-04-11 | Mitsubishi Denki Kabushiki Kaisha | Plesiochronous matching apparatus |
| JPH0897750A (en) * | 1994-09-22 | 1996-04-12 | Nec Commun Syst Ltd | Clock reception distribution system |
| CN1092864C (en) * | 1998-08-25 | 2002-10-16 | 华为技术有限公司 | Master backup reverse device |
| CN2383274Y (en) * | 1999-08-24 | 2000-06-14 | 深圳市中兴通讯股份有限公司 | Main spare plate switching device for electronic communication system |
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