CN113886300B - Clock data self-adaptive recovery system and chip of bus interface - Google Patents

Abstract

The invention discloses a clock self-adaptive recovery system and a chip based on a bus interface, wherein the clock self-adaptive recovery system comprises a bus interface receiver, a data state machine and a phase-locked loop; the bus interface receiver is used for receiving external data sent by the host computer by adopting a pre-generated standard sampling clock; a data state machine for starting a cyclic transition of the working state to start executing a round of data processing operation when the bus interface receiver starts receiving a specific data bit of external data; the data state machine is used for controlling a cyclic transfer mode of the working state, and controlling the phase-locked loop to adjust and generate a target sampling clock on the basis, so that an actual sampling period generated by the target sampling clock correspondingly adapts to the change of the real-time rate of the external data sent by the host, and one jump edge of the target sampling clock is maintained to be locked in a central sampling interval of a corresponding ideal sampling period.

Description

Clock data self-adaptive recovery system and chip of bus interface

Technical Field

The invention relates to the technical field of clock data recovery, in particular to a technology for recovering data through a local clock signal at a receiving end, and specifically relates to a clock data self-adaptive recovery system and a chip of a bus interface.

Background

A universal serial bus is a high-speed serial bus, in order to save overhead in serial data communication, generally only data signals are transmitted without transmitting clock signals synchronized with the data signals, in particular NRZI (Non Return to Zero Invert, non-return-to-zero inversion coding) differential signals present in data packets of a USB transmission, for data transmission, and synchronous data access can be generated without synchronizing clock signals. Therefore, a clock data recovery circuit CDR (Clock Data Recovery, abbreviated CDR) is typically employed to correctly sample the differential signal and generate non-return-to-zero inversion encoded data that is synchronized to the local clock.

The current way to implement a clock data recovery circuit using the phase-locked loop method is to align the clock edge of the receiving end inside the serial interface with the edge detected from the input data bit stream through a feedback loop, complete the frequency and phase locking, extract the clock again and sample the data bit stream with the extracted clock to recover the data, thereby sampling the data at an optimized point within the data bit time interval, but the loop locking time of the phase-locked loop circuit is long.

In the actual data transmission of the serial bus interface, the phase offset exists between the data of the input receiving end (RXD) and the local clock, and more importantly, the frequency offset exists, so that the local clock cannot accurately sample the input data, and an excessive error rate can be generated.

Disclosure of Invention

In order to solve the frequency offset problem of clock signals in the process of transmitting data by a bus interface, the invention discloses a clock data self-adaptive recovery system and a chip of the bus interface, which are based on an automatic compensation mechanism of a state machine, compare the external data received in real time with sampling results in an ideal state in terms of logic level and time sequence characteristics thereof, and then carry out self-adaptive compensation of clocks according to the comparison results, thereby adjusting the synchronization of the clock signals and digital signals and completing correct clock data recovery. The specific technical scheme is as follows:

The clock self-adaptive recovery system based on the bus interface is connected with a host through the bus interface; the clock self-adaptive recovery system comprises a bus interface receiver, a data state machine and a phase-locked loop; the bus interface receiver is connected with the bus interface; the bus interface receiver is used for receiving external data sent by the host computer by adopting a pre-generated standard sampling clock; the standard sampling clock of the ideal frequency sets the sampling frequency of one bit of external data of the ideal rate as the preset sampling frequency in each ideal sampling period; the bus interface receiver is connected with the data state machine, and the data state machine is used for starting the cyclic transition of the working state when the bus interface receiver starts to receive specific data bits of external data so as to start to execute a round of data processing operation; the phase-locked loop is connected with the data state machine, and the data state machine is used for controlling a cyclic transfer mode of the working state, controlling the phase-locked loop to regulate and generate a target sampling clock on the basis, enabling an actual sampling period generated by the target sampling clock to adapt to the change of the real-time rate of external data sent by the host, and maintaining one jump edge of the target sampling clock to be locked in a central sampling interval of a corresponding ideal sampling period; wherein the actual sampling period indicates that the logic level of the currently sampled bit remains the same for the same time.

Compared with the prior art, in the clock self-adaptive recovery system, the data state machine controls the bus interface receiver to receive external data transmitted by the bus interface by adopting the stable standard sampling clock generated by the gating clock module, and sends the external data to the data state machine to trigger the data state machine to carry out working state transfer, so that the phase-locked loop automatically adjusts the width of a sampling period to be suitable for the duration (actual sampling period) of sampling one bit of the external data in the working state transfer process, and locks a jump edge for sampling of a target sampling clock at a fixed sampling position of a corresponding ideal sampling period by exerting the phase locking function of the phase-locked loop.

The method further monitors the relation between the real-time rate of the external data sent by the host and the ideal rate to feed back the phase offset and the frequency offset of the external data relative to the standard sampling clock, and dynamically adjusts the working state of state machine transfer according to the corresponding offset, so that the level width of the target sampling clock is adapted to the change of the real-time rate of the external data, further the synchronization of clock signals and digital signals is realized, the correct clock data recovery function is completed, and the data is not easy to lose.

Further, the data state machine is configured to control a working state to automatically track a change of a data bit of external data received by the bus interface receiver in real time, and control a phase-locked loop to generate a target sampling clock according to a cyclic working state actually polled by the data state machine in the data processing operation, so that a level width of the target sampling clock and a level width of the data bit of the external data are synchronously changed; the sampling time maintained by the data state machine in each cycle working state is one unit clock period of the standard sampling clock, and the phase-locked loop samples one data bit of external data in each cycle working state and one data bit is one bit; the operating state includes a cyclical operating state. The target sampling clock generated by the technical scheme not only adapts to the level width change of the data bit of the external data which is currently sampled (the data bit of the external data is received by the bus interface receiver in real time and polled by the state machine), but also supports the phase-locked loop to accurately sample the external data at the jump edge of the locking.

Further, the data state machine is configured to advance an adaptive compensation time to complete a round of data processing operation when the real-time rate of the external data sent by the host is less than the ideal rate, so that the actual sampling period is adjusted to be less than the ideal sampling period; the data state machine is used for delaying one self-adaptive compensation time to finish one round of data processing operation when the real-time rate of external data sent by the host is greater than the ideal rate, so that the actual sampling period is regulated to be greater than the ideal sampling period; the ratio of the product of the preset sampling times and the unit clock period to the preset sampling error offset is the self-adaptive compensation time; the preset sampling error offset is of a pre-configured count and is determined by the frequency offset of the external data relative to the standard sampling clock. Thus, the data state machine triggers the phase-locked loop to output the adaptive compensation time to change the sampling period length, and the sampling period length is used for adjusting the number of the cyclic working states which can be transferred in the process of one round of data processing operation.

Further, the cyclic working states configured by the data state machine are divided into a first cyclic working state and a second cyclic working state, wherein the sum of the number of the first cyclic working states and the number of the second cyclic working states is equal to twice the preset sampling times, and the first cyclic working state and the second cyclic working state belong to different types of cyclic working states; when the duty cycle of a round of data processing operations is equal to an ideal sampling period, a round of data processing operations is set by the data state machine to be performed by a polling operation; the polling operation is divided into a first polling operation and a second polling operation according to the type of the transferred cyclic working state; the data state machine is used for starting the cycle transfer of the first cycle working state when the data bit received by the bus interface receiver is logic 1 after entering the cycle working state so as to start to execute a first polling operation and determine to start to execute a round of data processing operation; and the data state machine is further used for starting the cycle transfer of the second cycle working state to start to execute a second polling operation and determining to start to execute a round of data processing operation if the data bit received by the bus interface receiver is logic 0 after entering the cycle working state.

According to the technical scheme, two different types of cyclic working states and two different types of polling operations are set according to the cyclic transition situations of a state machine with a logic 1 data bit and a state machine with a logic 0 data bit respectively, and the cyclic transition of the working states is started more completely according to the received data bit, so that the data processing operation can monitor the phase offset and the frequency offset.

Further, the data state machine is configured to advance the adaptive compensation time by one round of data processing operation with respect to one round of polling operation, so as to reduce polling of all the cyclic working states corresponding to one round of adaptive compensation time in the corresponding round of polling operation, and set a sampling period formed by the currently completed round of data processing operation as an actual sampling period; the data state machine controls the phase-locked loop to set the logic level from the central position of the ideal sampling period matched with the current polling operation to the logic level of the cyclic working state which is transferred to by the last in the actual sampling period to be different from the logic level of the cyclic working state which corresponds to the rest sampling periods in the same actual sampling period, and controls the phase-locked loop to output the logic level which is set in the actual sampling period under the corresponding cyclic working state which is transferred to the phase-locked loop, and a target sampling clock is generated, so that the jump edge of the target sampling clock is locked in the central sampling period of the corresponding ideal sampling period. According to the technical scheme, the continuous sampling time of the circulating working state of the same type is shortened by reducing the transfer number of the circulating working state of the same type so as to adapt to the transmission characteristic that the real-time rate of external data sent by a host is larger than the ideal rate, the problem that the frequency of the data transmitted in real time is advanced relative to the standard sampling clock is solved, the jump edge of the target sampling clock for sampling is aligned to the central position of the ideal sampling period before self-adaptive adjustment, and the error rate is extremely low.

Further, the cyclic working states configured by the data state machine comprise N first cyclic working states and M second cyclic working states; wherein N is an integer greater than or equal to four, N is the preset sampling times, and the nth first cycle working state is used for indicating the sequence of the working state transition sequence; m is an integer greater than or equal to four, M is equal to N, and the Mth second cycle working state is used for indicating the sequence of the working state transition sequence; when detecting that the real-time rate of the external data sent by the host is greater than the ideal rate, the cyclic transfer process of the cyclic working state of the same type controlled by the data state machine comprises the following steps: when N is even, from the first same type of circulation working state to the N/2-1 th same type of circulation working state and from the N/2+1 th same type of circulation working state to the N-1 th same type of circulation working state, in each same type of circulation working state, if the bus interface receiver currently detects that a jump edge occurs on a data bit, the data state machine is transferred from the current same type of circulation working state to the first different type of circulation working state, so that the data state machine does not transfer from the next same type of circulation working state to the N same type of circulation working state, a round of data processing operation is determined to be completed, and the control working state is realized to automatically track the change of the data bit of external data received by the bus interface receiver in real time; or when N is odd number, from the first same type of circulation working state to the N/2-3/2 th same type of circulation working state, from the N/2+1/2 th same type of circulation working state to the N-1 th same type of circulation working state, in each same type of circulation working state, if the bus interface receiver currently detects that a jump edge occurs on a data bit, the data state machine is transferred from the current same type of circulation working state to the first different type of circulation working state, so that the data state machine does not transfer from the next same type of circulation working state to the N same type of circulation working state, a round of data processing operation is determined to be completed, and the control working state is realized to automatically track the change of the data bit of external data received by the bus interface receiver in real time.

Compared with the prior art, the technical scheme distinguishes the cyclic working state sampled to the first logic level from the cyclic working state sampled to the second logic level, forms two types of cyclic working states each representing one logic level, and ensures that the two types of cyclic working states are equal in number and are transferred in sequence; based on the above, the technical scheme controls the types of the corresponding circulation working states to change (the switching between the first circulation working state and the second circulation working state) in the corresponding sampling time based on the logic level of the actually sampled data bit in the process of one polling operation, shortens the sampling time or the actual sampling period of the circulation working state of the same type of the transition to be smaller than an ideal sampling period, finishes the transition of the circulation working state of the same type in one polling operation, adapts to the shortening of the level width of the sampled data bit of the same logic level, and further ensures that the edge of the target sampling clock and the edge of the received external data are mutually locked.

Further, the data state machine is further configured to delay one of the adaptive compensation times to complete one round of data processing operation with respect to one round of polling operation, so as to increase and poll all the cyclic operating states corresponding to one of the adaptive compensation times in a new round of polling operation, and then set a sampling period formed by the currently completed round of data processing operation as an actual sampling period; the data state machine controls the phase-locked loop to set the logic level from the central position of the ideal sampling period matched with the current polling operation to the logic level of the cyclic working state which is transferred to by the last in the actual sampling period to be different from the logic level of the cyclic working state which corresponds to the rest sampling periods in the same actual sampling period, and controls the phase-locked loop to output the logic level which is set in the actual sampling period under the corresponding transferred cyclic working state, and generates a target sampling clock, so that the jump edge of the target sampling clock is locked in the central sampling period of the corresponding ideal sampling period; the last cycle working state transferred to in the actual sampling period is the central position of an ideal sampling period matched in advance of the next polling operation. According to the technical scheme, the continuous sampling time of the circulating working state of the same type is prolonged by increasing the transfer number of the circulating working state of the same type so as to adapt to the transmission characteristic that the real-time rate of external data sent by a host is smaller than the ideal rate, the problem of frequency delay of the data transmitted in real time relative to a standard sampling clock is solved, the jump edge of the target sampling clock for sampling is aligned to the central position of the ideal sampling period before self-adaptive adjustment, and the error rate is extremely low.

Further, the working states of the data state machine configuration comprise N first cycle working states and M second cycle working states; wherein N is an integer greater than or equal to four, N is equal to the preset sampling times, and the Nth first cycle working state is used for indicating the sequence of the working state transition sequence; m is an integer greater than or equal to four, M is equal to N, and the Mth second cycle working state is used for indicating the sequence of the working state transition sequence; when the real-time rate of the external data sent by the host is smaller than the ideal rate, the cyclic transfer process of the cyclic working state of the same type controlled by the data state machine comprises the following steps: when N is even, in the nth cycle operation state, if no jump edge occurs in the data bit currently sampled by the bus interface receiver, the data state machine transfers from the nth cycle operation state to the first cycle operation state according to the unit clock period, so as to determine that the polling operation is finished at the present time, and starts to execute the next polling operation until all the cycle operation states of the same type corresponding to the adaptive compensation time are transferred in the next polling operation, wherein in the next polling operation, before transferring to the nth/2+1th cycle operation state, the data state machine transfers to the last cycle operation state of the same type corresponding to the adaptive compensation time, and determines to complete a round of data processing operation, so as to automatically track the change of the data bit of the external data received by the bus interface receiver in real time in the data processing operation; or when N is an odd number, in the nth cycle operation state, if no jump edge occurs on the data bit currently sampled by the bus interface receiver, the data state machine transfers from the nth cycle operation state to the first cycle operation state according to the unit clock period, so as to determine that the polling operation is finished at the present time, and starts to execute the next polling operation until all cycle operation states of the same type corresponding to the adaptive compensation time are transferred in the next polling operation, wherein in the next polling operation, before transferring to the last cycle operation state of the same type corresponding to the adaptive compensation time, and determining to finish a round of data processing operation, so as to automatically track the change of the data bit of the external data received by the bus interface receiver in real time in the data processing operation.

Compared with the prior art, the technical scheme distinguishes the cyclic working state sampled to the first logic level from the cyclic working state sampled to the second logic level, forms two types of cyclic working states each representing one logic level, and ensures that the two types of cyclic working states are equal in number and are transferred in sequence; on the basis, the technical scheme expands the sampling time or the actual sampling period of the same type of cyclic working state to be transferred to be larger than an ideal sampling period, transfers the same type of cyclic working state in two polling operations, and is suitable for the lengthening of the level width of the sampled data bit with the same logic level, so that the mutual locking of the edge of a target sampling clock and the edge of received external data is ensured.

Further, for each of the first cyclic operation state and the second cyclic operation state, when N is an even number, the specific steps of the polling operation include: in each cycle working state, if one data bit of external data sampled by the bus interface receiver currently is a first logic level, the data state machine is transferred from the current cycle working state to the next cycle working state until the data state machine is transferred to the N/2 th cycle working state; in the N/2 th cycle working state, if one data bit of the external data currently sampled by the bus interface receiver is at a first logic level or a second logic level, the data state machine is transferred from the N/2 th cycle working state to the N/2+1 th cycle working state according to the unit clock period; in each cycle working state, if the bus interface receiver currently samples one data bit of external data to be a first logic level, the data state machine is transferred from the current cycle working state to the next cycle working state until the data state machine is transferred to the Nth cycle working state, so as to complete one polling operation; in the nth cycle working state, if one data bit of the external data currently sampled by the bus interface receiver is at a second logic level, the data state machine is transferred from the nth cycle working state to the first other cycle working state according to the unit clock period; in the nth cycle working state, if one data bit of the external data sampled by the bus interface receiver currently is a first logic level, the data state machine is transferred from the nth cycle working state to a first same cycle working state according to the unit clock period so as to enter the next polling operation; wherein, when the first logic level represents logic 1, the second logic level represents logic 0; or the first logic level represents a logic 0 and the second logic level represents a logic 1.

By combining the technical scheme of delaying one self-adaptive compensation time and the technical scheme of advancing one self-adaptive compensation time, the technical scheme designs a circulation working state correspondingly aiming at each sampling of the same data bit on the premise that the number of each circulation working state is even, and determines the transfer of the next circulation working state according to the logic level state of actual sampling in each unit clock period, the normal operation of the current polling operation can be advanced by adopting a state machine to define an ideal sampling period, the first circulation working state with the number of the preset sampling times or the second circulation working state with the number of the preset sampling times is polled in the ideal sampling period, and the type of the circulation working state at the central position of the ideal sampling period can be controlled not to change so as to realize the mutual locking function between the clock and the data.

Further, for each of the first cyclic operation state and the second cyclic operation state, when N is an odd number, the specific steps of the polling operation include: in each cycle working state, if the bus interface receiver currently samples one data bit of external data to be a first logic level, the data state machine is transferred from the current cycle working state to the next cycle working state until the data state machine is transferred to the N/2-1/2 th cycle working state; in the N/2-1/2 th cycle working state, if the bus interface receiver currently samples one data bit of external data to be a first logic level or a second logic level, the data state machine is transferred from the N/2-1/2 th cycle working state to the N/2+1/2 th cycle working state according to the unit clock period; in each cycle working state, if the bus interface receiver currently samples one data bit of external data to be a first logic level, the data state machine is transferred from the current cycle working state to the next cycle working state until the data state machine is transferred to the Nth cycle working state, so as to complete one polling operation; in the nth cycle working state, if one data bit of the external data sampled by the bus interface receiver currently is a first logic level, the data state machine is transferred from the nth cycle working state to a first same cycle working state according to the unit clock period so as to enter the next polling operation; in the nth cycle working state, if one data bit of the external data currently sampled by the bus interface receiver is at a second logic level, the data state machine is transferred from the nth cycle working state to the first other cycle working state according to the unit clock period; wherein, when the first logic level represents logic 1, the second logic level represents logic 0; or the first logic level represents a logic 0 and the second logic level represents a logic 1.

By combining the technical scheme of delaying one self-adaptive compensation time and the technical scheme of advancing one self-adaptive compensation time, the technical scheme designs a circulation working state correspondingly aiming at each sampling of the same data bit on the premise that the number of each circulation working state is odd, and determines the transition of the next circulation working state according to the logic level state of actual sampling in each unit clock period, the normal operation of the current polling operation can be advanced in a state machine mode to define an ideal sampling period, the first circulation working state with the number of the preset sampling times or the second circulation working state with the number of the preset sampling times is polled in the ideal sampling period, and the type of the circulation working state at the central position of the ideal sampling period can be controlled to be unchanged, so that the mutual locking function between the clock and the data is realized.

Further, for each of the first and second cyclic operating states, the target sampling clock is specifically: on the premise that N is an even number, when the data state machine is in any one of a first cycle working state to an N/2 th cycle working state, the phase-locked loop outputs a second logic level in the sampling time of the current cycle working state; when the data state machine is in any one of the (N/2+1) th to (N) th cyclic working states, the phase-locked loop outputs a first logic level in the sampling time of the current cyclic working state; on the premise that N is an odd number, when the data state machine is in any one of the first cycle working state to the N/2-1/2 th cycle working state, the phase-locked loop outputs a second logic level in the sampling time of the current cycle working state; when the data state machine is in any one of the N/2+1/2 cycle working state to the N cycle working state, the phase-locked loop outputs a first logic level in the sampling time of the current cycle working state; wherein, when the first logic level represents logic 1, the second logic level represents logic 0; or the first logic level represents a logic 0 and the second logic level represents a logic 1; and the sum of sampling time of the cyclic working state which is actually transferred by the data state machine is equal to the actual sampling period.

In the technical scheme, whether the current polling operation or the next polling operation is performed, the logic level from the central position of an ideal sampling period of current sampling matching to the last transferred circulation working state in the actual sampling period is set to be different from the logic level of the circulation working state corresponding to the rest sampling intervals in the same actual sampling period, so that the phase-locked loop configures the output logic level in the sampling time of the circulation working state of the data state machine, and the target sampling clock is formed according to the sequence of the unit clock period.

Further, the data state machine is further configured with at least one first initial working state and at least one second initial working state; the ratio of the number of pulses of the synchronous domain of the external data to the preset sampling times is equal to the number of first initial working states, and the number of the first initial working states is equal to the number of second initial working states; the bus interface receiver receives data bits in a first initial working state and a second initial working state, wherein the data bits received by the bus interface receiver in the first initial working state and the second initial working state are synchronous fields belonging to the external data; the data state machine is used for entering a first initial working state before starting the cycle transfer of the first cycle working state or before starting the cycle transfer of the second cycle working state, and after the clock self-adaptive recovery system is reset, if the data bit received by the bus interface receiver is at a first logic level; in the first initial working state, if the data bit received by the bus interface receiver is at a first logic level, maintaining the first initial working state; in the first initial working state, if the data bit received by the bus interface receiver is at the second logic level, transferring from the first initial working state to the second initial working state; in the second initial working state, if the data bit received by the bus interface receiver is at the second logic level, maintaining the second initial working state; in the second initial working state, if the data bit received by the bus interface receiver is at the first logic level, transferring from the second initial working state to the first initial working state, and circularly transferring until the ratio of the number of pulses of the synchronous domain of the external data to the preset sampling times is equal to the number of traversed second initial working states, and transferring from the second initial working state to the first circular working state so as to adapt to the jump edge of the synchronous domain of the external data transmitted by the bus interface; the phase-locked loop is at a second logic level in a sampling time stage of a first initial working state, and the phase-locked loop is at the second logic level in a sampling time stage of a second initial working state; wherein, when the first logic level represents logic 1, the second logic level represents logic 0; or the first logic level represents a logic 0 and the second logic level represents a logic 1.

According to the technical scheme, the data bits are synchronously processed in a mode of continuously detecting the jump edges, so that the sampling clock is synchronous with the sampling clock after continuously sampling the jump edges of two identical change trends of the synchronous packet headers of external data transmitted by the host. And the stability and the anti-interference performance of sampling are improved. Avoiding abrupt change in the gap of the synchronous domain from influencing the normal sampling of the data bit.

Further, when the real-time rate of the external data is smaller than the ideal rate, the time length occupied by the level of one bit of the external data under the sampling action of a standard sampling clock is longer than the length of the ideal sampling period; when the real-time rate of the external data is greater than the ideal rate, the time length occupied by the logic level of one bit of the external data under the sampling action of a standard sampling clock is smaller than the length of the ideal sampling period. According to the technical scheme, based on the scenes of clock jitter and frequency offset and phase offset of data bits of external data relative to a sampling clock, the real-time rate of the external data is represented by using the time length occupied by the logic level of the bits (the level width of the data bits of the same logic level), so that the comparison with the ideal rate (corresponding ideal sampling period) is facilitated.

Further, if the currently sampled data bit is logic 0 during the transition between the first cyclic operating states on the premise that the second logic level is denoted as logic 0 and the first logic level is denoted as logic 1, the data state machine is configured to transition from the first cyclic operating state to the second cyclic operating state; if the currently sampled data bit is logic 0 in the process of transferring between the second cycle working states on the premise that the second logic level is expressed as logic 0 and the first logic level is expressed as logic 1, the data state machine is not configured to transfer from the second cycle working state to the first cycle working state; if the currently sampled data bit is logic 1 in the process of transferring between the second cyclic working states on the premise that the second logic level is expressed as logic 1 and the first logic level is expressed as logic 0, the data state machine is configured to transfer from the second cyclic working state to the first cyclic working state; in the process of transferring between the first cycle working states, if the currently sampled data bit is logic 1, the data state machine is not configured to transfer from the first cycle working state to the second cycle working state on the premise that the second logic level is expressed as logic 1 and the first logic level is expressed as logic 0.

Based on the technical scheme, in the operation process of the data state machine, the triggering function of the second logic level detected in the transition process between the first circulation working states is different from that of the same second logic level detected in the transition process between the second circulation working states, wherein the transition from the current circulation working state to the other circulation working state can be realized when the same second logic level is detected in the transition process of one type of circulation working state, and the transition between the circulation working states of the same type can only be realized when the same second logic level is detected in the transition process of the other type of circulation working state, so that the occurrence of the phenomenon is avoided: after switching from polling the data bits of a current logic level to polling the data bits of another logic level, the data state machine cannot appear to be unable to poll the data bits of the other logic level, but instead switches back to continue the data bits of the current logic level.

Further, when the bus interface is a USB interface, a frequency difference between the clock frequency of the target sampling clock and the ideal frequency of the standard sampling clock is within a precision range required by the USB protocol, so as to ensure that the working state of the data state machine operates and converts normally at the corresponding clock node. Under this solution, for Full Speed transmission (Full Speed) in the USB1.1 specification, since its Speed is not very high, a 48MHz clock operating locally can be used, and the frequency difference is adaptively compensated by the aforementioned data state machine to generate the target sampling clock for correctly sampling 12Mbit/s data.

A chip comprising the clock adaptive recovery system. Considering hardware implementation, the chip uses the data state machine to control the bus interface receiver to receive the external data transmitted by the bus interface by adopting the stable standard sampling clock generated by the gating clock module, and sends the external data to the data state machine to trigger the data state machine to transfer the working state, so that the phase-locked loop automatically adjusts the width of the sampling period to be suitable for the duration (actual sampling period) of the same bit of the sampled external data in the working state transfer process, and locks one jump edge of the target sampling clock for sampling at a fixed sampling position of the corresponding ideal sampling period by playing the phase locking function of the phase-locked loop, so that the level width of the target sampling clock is suitable for the real-time rate change of the external data, the synchronization of clock signals and digital signals is realized, namely the synchronization precision is ensured in a dynamic compensation mode, the correct clock data recovery function is completed, and the data is not easy to lose.

Drawings

Fig. 1 is a schematic block diagram of a clock adaptive recovery system based on a bus interface according to an embodiment of the present invention.

Fig. 2 is a schematic diagram illustrating transition of an operation state of a data state machine disclosed when a preset sampling number is 4 in another embodiment of the present invention, where a first cycle operation state is sequentially STAT0, STAT1, STAT2, and STAT3, and a second cycle operation state is sequentially STAT4, STAT5, STAT6, and STAT7; RXD is a data input end of the bus interface receiver and is used for receiving data bits of external data transmitted by a host; IDLE represents a first initial operating state, and IDLE1 represents a second initial operating state.

Detailed Description

The present application will be described and illustrated with reference to the accompanying drawings and examples in order to make the objects, technical solutions and advantages of the present application more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the application. All other embodiments, which can be made by a person of ordinary skill in the art based on the embodiments provided by the present application without making any inventive effort, are intended to fall within the scope of the present application.

As an embodiment, a clock self-adaptive recovery system based on a bus interface is disclosed, wherein the clock self-adaptive recovery system is connected with a host through the bus interface to form a master-slave structure system with the clock self-adaptive recovery system (slave equipment) and the host; as shown in fig. 1, the clock adaptive recovery system includes a bus interface receiver, a data state machine, and a phase locked loop. The bus interface receiver is connected with the bus interface, and is used for receiving external data sent by the host by adopting a pre-generated standard sampling clock, specifically, the bus interface receiver receives RXD signals transmitted by the host through serial input pins of the bus interface, which is essential for data transmission. The pre-generated standard sampling clock is output by the gating clock module shown in fig. 1, and the embodiment shown in fig. 1 uses the gating clock module formed by latches to output a stable clock at an output end.

Specifically, the standard sampling clock of the ideal frequency sets the sampling number of one bit of the external data of the ideal rate to a preset sampling number in each ideal sampling period; in some embodiments, the ideal frequency of the external data transmitted from the host is 12Mhz, the standard sampling clock generated by the gating clock module is 48Mhz clock, which is used for sampling the input data by the clock adaptive recovery system or the phase-locked loop, and one bit of the external data is sampled 4 times by the standard sampling clock to correctly recover the data in an ideal sampling period, wherein the preset sampling number is 4, and in the actual USB data transmission, for example, when the rate of the host transmitting the data is greater than or less than 12Mhz, the phase offset exists between the RXD signal of the input data and the local clock, and more importantly, the frequency offset exists, that is, the sampling clock skew phenomenon exists, so that the embodiment needs to be adjusted to complete the correct clock data recovery.

As shown in fig. 1, the bus interface receiver is connected to a data state machine, and the data state machine is configured to start a cycle transition of an operating state when the bus interface receiver starts to receive a specific data bit of external data, specifically, after the system initialization is completed, the bus interface receiver enters into a cycle operating state with a polling function, starts to execute a round of data processing operation, and simultaneously controls the phase-locked loop to start a round of data sampling operation on the received external data so as to introduce some delay in real time. In this embodiment, the phase-locked loop is connected with the data state machine, and the data state machine is used for controlling a cyclic transfer mode of a working state, and controlling the phase-locked loop to adjust and generate a target sampling clock on the basis of the cyclic transfer mode, so that the target sampling clock is adapted to the real-time rate change of external data sent by the host, the period of the target sampling clock is equal to the data period of the external data, and the aim of synchronizing the target sampling clock is achieved. In some embodiments, the phase-locked loop outputs the target sampling clock signal while the operating state transitions; specifically, the phase-locked loop adds or subtracts the ideal sampling period to the delay adjusted in real time, so that the processing result is equal to the integral multiple, preferably 1 time, of the actual sampling period generated under the real-time rate of the external data sent by the host, the purpose that the clock signal edge (rising edge or falling edge) with clock skew after delay compensation is aligned with the edge of the data bit of the external data is achieved, the purpose of clock synchronization is achieved, that is, the actual sampling period generated by the target sampling clock correspondingly adapts to the change of the real-time rate of the external data sent by the host, and meanwhile, one jump edge of the target sampling clock is kept locked in the central sampling interval of the corresponding ideal sampling period. It should be noted that the actual sampling period indicates that the logic level of one bit currently sampled is maintained for the same time.

In this embodiment, in the cooperative operation of the bus interface receiver and the data state machine, the data state machine is used as a protocol engine of the bus interface, in an infinitely cyclic operation process, under the scheduling control of the data state machine, when initialization is completed, the data state machine enters a working mode in a certain state, and jumps between states according to the real-time rate of the external data currently received by the bus interface receiver, the bit width or the level width variation of the sampled data bit, until the sampling clock regulated by the phase-locked loop is aligned with the edge of the currently received external data, so as to ensure the mutual locking of the clock and the data.

In this embodiment, during the cooperation of the phase-locked loop and the data state machine, the phase-locked loop is further configured to input external data transmitted from the bus interface receiver, and in the embodiment of fig. 1, the external data is transmitted to the phase-locked loop through the data state machine, or understood as being transmitted to the phase-locked loop by the bus interface receiver under the scheduling control of the data state machine; a phase-locked loop is composed of a phase discriminator, a low-pass filter and a voltage-controlled oscillator, wherein in the phase-locked loop, after the original input data (external data) and a sampling clock output by the voltage-controlled oscillator are subjected to phase discrimination by the phase discriminator, a voltage difference signal is generated; the low-pass filter completes low-pass filtering of the voltage difference signal, and the stability of a system loop is ensured; under the dispatching of the data state machine, the filtered voltage difference signal acts on the voltage controlled oscillator to drive the output signal frequency of the voltage controlled oscillator to be close to the signal frequency of the input external data along with the transition of the working state of the configuration of the data state machine until the frequency difference is eliminated to finish the frequency and phase locking, namely, the clock signal edge (rising edge or falling edge) with clock skew originally is adjusted to be aligned with the edge of a specific data bit of the external data; the phase-locked loop gradually completes the central sampling of input data (external data) in an ideal sampling period through the feedback adjustment, and keeps the working state, determines that the output signal of the voltage-controlled oscillator is the target sampling clock, and keeps one jump edge of the target sampling clock locked in a central sampling interval of the corresponding ideal sampling period; at this time, the clock self-adaptive recovery system uses a trigger to sample the external data by the target sampling clock and then outputs the data, thus completing the function of correct clock data recovery.

In the cooperation operation of the phase-locked loop and the data state machine, the problems of clock deflection and frequency offset are indispensable links, and at present, clock deflection causes clock edges of various areas of a digital system to deviate, and the deviation may be caused by clock buffering delay, clock network propagation delay and other reasons. The phase-locked loop of the embodiment compares the phase relation between the input clock and the feedback clock to continuously adjust the frequency and the phase of the output clock of the voltage-controlled oscillator, gradually compensates the time delay generated by the clock distribution network, in particular, the phase-locked loop constructs a variable time delay chain structure between the input clock and the feedback clock, the data state machine changes the circulation transfer mode of the working state according to the real-time rate of the external data sent by the host and the magnitude relation of the ideal rate, and further controls the phase-locked loop to adaptively adjust the time delay value of the variable time delay chain access, and the phase-locked loop generates an adaptive compensation time corresponding to the duration of the working state of the data state machine, so as to control the phase alignment of the input clock and the feedback clock, realize the locking function of the phase-locked loop to one jump edge of the target sampling clock, and particularly lock in the central sampling interval of the corresponding ideal sampling period; wherein the central sampling interval comprises a middle position of the ideal sampling period or a preset sampling position ahead of the middle position, and the preset sampling position is determined by clock offset

It should be noted that, the phase-locked loop disclosed in this embodiment may be divided into an analog DLL, a digital DLL, and a digital-analog hybrid DLL according to different implementation methods. The analog DLL and the digital-analog hybrid DLL circuit adopt a voltage-controlled variable delay chain structure. The delay value of the digital DLL variable delay chain delay unit is fixed, the phase relation between the feedback clock and the input clock is adjusted by changing the delay value generated by the input clock passing through the variable delay chain through the data state machine, wherein the data state machine is used as a digital logic control module, and the configured cyclic transfer mode of the working state determines the structure of the variable delay chain. In addition, typical circuit structures for all-digital DLLs include RDLL, SARDLL, and TDCDLL, where the RDLL implementation method in turn includes SRDLL and CRDLL. In consideration of stability of a clock system, the data state machine adopts a counter to control the phase-locked loop to carry out self-adaptive adjustment under a corresponding working state, is not easy to lose lock, has more stable performance, and can meet the requirement of environmental change resistance.

Compared with the prior art, in the clock self-adaptive recovery system, the data state machine controls the bus interface receiver to receive external data transmitted by the bus interface by adopting the stable standard sampling clock generated by the gating clock module, and sends the external data to the data state machine to trigger the data state machine to carry out working state transfer, so that the phase-locked loop automatically adjusts the width of a sampling period to be suitable for the duration (actual sampling period) of sampling one bit of the external data in the working state transfer process, and locks a jump edge for sampling of a target sampling clock at a fixed sampling position of a corresponding ideal sampling period by exerting the phase locking function of the phase-locked loop. Therefore, the relation between the real-time rate of the external data sent by the host and the ideal rate can be monitored to feed back the phase offset and the frequency offset of the external data relative to the standard sampling clock, and the working state of the state machine transfer is dynamically adjusted according to the corresponding offset, so that the level width of the target sampling clock is adapted to the change of the real-time rate of the external data, the synchronization of a clock signal and a digital signal is realized, the correct clock data recovery function is completed, and the data is not easy to lose.

On the basis of the above embodiment, the data state machine is configured to control, in a current round of data processing operation, a working state to automatically track a change of a data bit of external data received by the bus interface receiver in real time, so as to detect a size relationship between a real-time rate at which the host sends the external data and the ideal rate; and controlling the phase-locked loop to generate a target sampling clock according to the actually polled circulation working state of the data state machine in the data processing operation, wherein the phase-locked loop performs a round of data sampling operation on external data in the same time in practice, so as to adjust the frequency of an output clock signal to approach the frequency of the external data input into the phase-locked loop according to the phase comparison result of the external data input into the phase-locked loop and the sampling clock inside the phase-locked loop, the target sampling clock is generated until the frequency is equal, and when the frequency (equivalent to the rate of the external data sent by a host) of the external data input into the phase-locked loop changes, the target sampling clock makes an adaptive change under the feedback regulation effect of the phase-locked loop, and generates a new target sampling clock. Therefore, the level width of the target sampling clock and the level width of the data bit of the external data synchronously change, and the end edge of the target sampling clock in one actual sampling period is aligned with the end edge of one data bit of the external data in one actual sampling period. It should be noted that, the sampling time maintained by the data state machine in each cycle working state is one unit clock period of the standard sampling clock, one unit clock period is taken as a counting unit, and the preset sampling times are one ideal sampling period; specifically, the phase-locked loop samples a data bit of an effective data segment of external data in each cyclic working state, wherein one data bit is one bit; the working state comprises a circulating working state; the external data includes a synchronization field and a valid data segment. The target sampling clock generated in this embodiment not only adapts to the level width variation of the data bit of the external data currently sampled (the data bit of the external data received by the bus interface receiver in real time and polled by the state machine), but also supports the phase-locked loop to sample the external data correctly at the jump edge of the locking.

Specifically, when the real-time rate of external data sent by the host is smaller than the ideal rate, the data state machine is used for completing a round of data processing operation in advance by an adaptive compensation time, so that the actual sampling period is adjusted to be smaller than the ideal sampling period, thereby achieving the purposes of controlling the working state to automatically track the shortening bit width (relative to the level width of the ideal sampling period) of the data bit of the external data received by the bus interface receiver in real time, and generating a target sampling clock by the phase-locked loop according to the cyclic working state actually polled by the data state machine in the data processing operation, wherein the actual sampling period corresponds to the latest generated target sampling clock. The data state machine is used for delaying an adaptive compensation time to complete a round of data processing operation when the real-time rate of external data sent by the host is greater than the ideal rate, so that the actual sampling period is regulated to be greater than the ideal sampling period, the purpose of controlling the working state to automatically track the extended bit width (relative to the level width of the ideal sampling period) of the data bit of the external data received by the bus interface receiver in real time is achieved, and then the phase-locked loop generates a target sampling clock according to the cyclic working state actually polled by the data state machine in the data processing operation. It should be noted that, the ratio of the product of the preset sampling times and the unit clock period to the preset sampling error offset is the adaptive compensation time; the preset sampling error offset is of a pre-configured count and is determined by the frequency offset of the external data relative to the standard sampling clock for the phase-locked loop to generate a time offset. Therefore, the embodiment enables the data state machine to trigger the phase-locked loop to output the adaptive compensation time to change the sampling period length, so as to adjust the number of the cyclic working states which can be transferred in the process of one round of data processing operation.

On the basis of the foregoing embodiment, the cyclic working states configured by the data state machine are divided into a first cyclic working state and a second cyclic working state, where the sum of the number of the first cyclic working states and the number of the second cyclic working states is equal to twice the preset sampling number, the first cyclic working state and the second cyclic working state belong to different types of cyclic working states, and the conditions of triggering transfer of the actions of the first cyclic working state and the second cyclic working state are similar, but the sampling data bits represented by the first cyclic working state and the second cyclic working state are different, and the time periods executed by the first cyclic working state and the second cyclic working state are different; when the duty cycle of a round of data processing operations is equal to an ideal sampling period, a round of data processing operations is set by the data state machine to be performed by a polling operation; the polling operation is divided into a first polling operation and a second polling operation according to the type of the transferred cyclic operation state. And the data state machine is used for starting the cycle transfer of the first cycle working state when the data bit received by the bus interface receiver is started to be logic 1 after entering the cycle working state and finishing the initialization work, so as to start to execute a first polling operation, determine to start to execute a round of data processing operation, and simultaneously control the phase-locked loop to start to sample the corresponding data bit of the external data so as to start to regulate and generate a target sampling clock. And the data state machine is also used for starting the cycle transfer of the second cycle working state to start executing a second polling operation and determining to start executing a round of data processing operation after entering the cycle working state, namely after finishing the initialization work, if the data bit received by the bus interface receiver is started to be logic 0, and simultaneously controlling the phase-locked loop to start sampling the corresponding data bit of the external data so as to synchronously generate a target sampling clock. In this embodiment, for the two state machine loop transition situations where the data bit is at the logic high level (1) and the data bit is at the logic low level (0), two different types of loop working states and two different types of polling operations are set, and loop transition of the working states is started more completely according to the received data bit, so that the data processing operation can monitor the phase offset and the frequency offset.

Specifically, the working states configured by the data state machine include N first cycle working states and M second cycle working states; wherein N is an integer greater than or equal to four, N is the preset sampling times, and the nth first cycle working state is used for indicating the sequence of the working state transition sequence; m is an integer greater than or equal to four, M is the preset sampling times, and the Mth second cycle working state is used for indicating the sequence of the working state transition sequence.

As a general embodiment, as shown in fig. 2, when N is 4, the first cyclic operation state is STAT0, the second first cyclic operation state is STAT1, the third first cyclic operation state is STAT2, the fourth first cyclic operation state is STAT4, the first second cyclic operation state is STAT4, the second cyclic operation state is STAT5, the first second cyclic operation state is STAT4, the second cyclic operation state is STAT5, the third second cyclic operation state is STAT6, and the fourth second cyclic operation state is STAT7; the RXD is a data input end of the bus interface receiver and is used for receiving data bits of external data transmitted by a host. The first logic level is a logic 1 and the second logic level is a logic 0.

As can be seen in conjunction with fig. 2, the loop transition of the first loop operating state controlled by the data state machine is as follows:

Under STAT0, if one data bit RXD of the external data currently sampled by the bus interface receiver is logic 1, the data state machine is transferred from STAT0 to STAT1; if RXD is logic 0, the data state machine is transferred from STAT0 to STAT4. Wherein the initial state of RXD is logic 1 at STAT 0.

At STAT1, the data state machine transitions from STAT1 to STAT2, regardless of whether RXD is logic 1 or logic 0.

Under STAT2, if RXD is logic 1, the data state machine is transferred from STAT2 to STAT3, and the polling operation is completed once; if RXD is logic 0, the data state machine is transferred from STAT2 to STAT4.

Under STAT3, if RXD is logic 1, the data state machine is transferred from STAT3 to STAT0, and then the next polling operation is performed; if RXD is logic 0, the data state machine is transferred from STAT3 to STAT4.

As can be seen in connection with fig. 2, the loop transition of the second loop operating state controlled by the data state machine is as follows:

Under STAT4, if one data bit RXD of the external data currently sampled by the bus interface receiver is logic 0, the data state machine is transferred from STAT4 to STAT5; if RXD is a logic 1, the data state machine is transferred from STAT4 to STAT0.

At STAT5, the data state machine transitions from STAT5 to STAT6, regardless of whether RXD is logic 1 or logic 0.

Under STAT6, if RXD is logic 0, the data state machine is transferred from STAT6 to STAT7 to complete the polling operation once; if RXD is a logic 1, the data state machine is transferred from STAT6 to STAT0.

Under STAT7, if RXD is logic 0, the data state machine is transferred from STAT7 to STAT4 and enters the next polling operation; if RXD is a logic 1, the data state machine is transferred from STAT7 to STAT0.

Thus, for each of the first and second cyclic operating states, when N is an even number, the specific steps of the polling operation include: in each cycle working state, if one data bit of external data sampled by the bus interface receiver currently is a first logic level, the data state machine is transferred from the current cycle working state to the next cycle working state until the data state machine is transferred to the N/2 th cycle working state; in the N/2 th cycle working state, if one data bit of the external data currently sampled by the bus interface receiver is the first logic level or the second logic level, namely in the sampling time of the N/2 th cycle working state, no matter whether a jump edge occurs, the data state machine is transferred from the N/2 th cycle working state to the N/2+1 th cycle working state according to the unit clock period; in each cycle working state, if the bus interface receiver currently samples one data bit of external data to be a first logic level, the data state machine is transferred from the current cycle working state to the next cycle working state until the data state machine is transferred to the Nth cycle working state, so as to complete one polling operation; in the nth cycle working state, if one data bit of the external data currently sampled by the bus interface receiver is at a second logic level, the data state machine is transferred from the nth cycle working state to the first other cycle working state according to the unit clock period; in the nth cycle working state, if the bus interface receiver samples that one data bit of external data is at a first logic level, the data state machine transfers from the nth cycle working state to the first same cycle working state according to the unit clock period so as to enter the next polling operation. Wherein, when the first logic level represents logic 1, the second logic level represents logic 0; or the first logic level represents a logic 0 and the second logic level represents a logic 1.

As an embodiment one, that is, in a scenario that the real-time rate of external data sent by the host is greater than the ideal rate, the data state machine advances one adaptive compensation time to complete one round of data processing operation relative to one first polling operation, that is, ends one first polling operation in a manner of advancing one adaptive compensation time, so as to reduce polling of all first cyclic working states corresponding to one adaptive compensation time, and then sets a sampling period formed by one first polling operation which ends in advance as a first actual sampling period; under the control of the data state machine, the phase-locked loop sets the logic level of a first circulation working state which is transferred to last in a first actual sampling period to be different from the logic level of a first circulation working state which corresponds to other sampling intervals in the same first actual sampling period, and controls the phase-locked loop to output the logic level which is newly set in the first actual sampling period under the corresponding transferred first circulation working state, and generates a first target sampling clock, so that the jump edge of the first target sampling clock is locked in the central sampling interval of the corresponding ideal sampling period; wherein the actual sampling period comprises a first actual sampling period and the target sampling clock comprises a first target sampling clock.

In a first embodiment, when the real-time rate of the external data sent by the host is greater than the ideal rate, that is, when the level width of the signal of RXD is smaller than the length of the ideal sampling period, as can be seen from fig. 2, the data state machine is shifted to STAT2, and when it is detected that RXD is logic 0, the data state machine is shifted from STAT2 to STAT4, which means that the time that RXD remains logic 1 in the current first polling operation is smaller than the ideal sampling period, and the current first polling operation is ended after shifting to STAT4, so as to determine that a round of data processing operation is completed. Therefore, in this embodiment, the data state machine does not transition from STAT2 to STAT3, and the polling of all the first cyclic operating states corresponding to one adaptive compensation time is reduced, one adaptive compensation time is advanced to complete one round of data processing operation, and the first polling operation is ended once in a manner of advancing one adaptive compensation time; in this embodiment, the ideal sampling period is adjusted to reduce STAT3 corresponding to one unit sampling period to adapt to the change of the logic 1 level of RXD, so that the actual sampling period is equal to the level width of RXD in one actual sampling period, and clock data edge alignment is completed. Therefore, when N is even, from the first type of cyclic working state to the N/2-1 th type of cyclic working state, and from the N/2+1 th type of cyclic working state to the N-1 th type of cyclic working state, in each type of cyclic working state, if a jump edge occurs on a data bit currently sampled by the bus interface receiver, corresponding to the first embodiment, the jump from logic 1 to logic 0 is performed, and the current type of cyclic working state is transferred to the first different type of cyclic working state, so that the data state machine does not transfer between the next type of cyclic working state to the N type of cyclic working state, and a round of data processing operation is determined to be completed, thereby realizing that the control working state automatically tracks the change of the data bit of external data received by the bus interface receiver in real time. In the nth/2 first cycle working state (STAT 1), if one data bit of the external data currently sampled by the bus interface receiver is the first logic level or the second logic level, that is, in the sampling time of the nth/2 cycle working state, no matter whether a jump edge occurs, the data state machine is transferred from the nth/2 first cycle working state to the nth/2+1th first cycle working state according to the unit clock period. The type of the cyclic working state at the central position of the ideal sampling period can be controlled to be unchanged, so that the mutual locking function between the clock and the data is realized.

On the basis of the first embodiment, when N is equal to 4, as can be seen from fig. 2, when the data state machine is in STAT0 and STAT1, the phase-locked loop outputs logic 0 in the sampling time of a first cycle working state in which the phase-locked loop is currently located; when the data state machine is at STAT3 and STAT4, the phase-locked loop outputs a logic 1 within the sampling time of the current one-cycle operating state. On the premise that N is an even number, when the data state machine is in any one of the first to N/2 th cyclic working states, the phase-locked loop outputs a second logic level in the sampling time of the current cyclic working state; when the data state machine is in any one of the N/2+1 cycle working state to the N cycle working state, the phase-locked loop outputs a first logic level in the sampling time of the current cycle working state. Wherein, when the first logic level represents logic 1, the second logic level represents logic 0; or the first logic level represents a logic 0 and the second logic level represents a logic 1.

As a second embodiment, when N is an odd number, the loop transfer process of the same type of loop working state controlled by the data state machine includes: in each cycle working state, if the bus interface receiver currently samples one data bit of external data to be a first logic level, the data state machine is transferred from the current cycle working state to the next cycle working state until the data state machine is transferred to the N/2-1/2 th cycle working state; in the N/2-1/2 th cycle working state, if one data bit of the external data currently sampled by the bus interface receiver is a first logic level or a second logic level, namely in the sampling time of the N/2-1/2 th cycle working state, no matter whether a jump edge occurs, the data state machine is transferred from the N/2-1/2 th cycle working state to the N/2+1/2 th cycle working state according to the unit clock period; in each cycle working state, if the bus interface receiver currently samples one data bit of external data to be a first logic level, the data state machine is transferred from the current cycle working state to the next cycle working state until the data state machine is transferred to the Nth cycle working state, so as to complete one polling operation; in the nth cycle working state, if one data bit of the external data sampled by the bus interface receiver currently is a first logic level, the data state machine is transferred from the nth cycle working state to a first same cycle working state according to the unit clock period so as to enter the next polling operation; in the nth cycle operation state, if the bus interface receiver samples that one data bit of the external data is at the second logic level, the data state machine transitions from the nth cycle operation state to the first another cycle operation state according to the unit clock period. Wherein, when the first logic level represents logic 1, the second logic level represents logic 0; or the first logic level represents a logic 0 and the second logic level represents a logic 1.

In an implementation scenario where the real-time rate of sending the external data by the host is greater than the ideal rate, the loop transfer process of the same type of loop working state controlled by the data state machine includes: when N is odd number, from the first same type of circulation working state to the N/2-3/2 th same type of circulation working state, from the N/2+1/2 th same type of circulation working state to the N-1 th same type of circulation working state, in each same type of circulation working state, if the currently sampled data bit of the bus interface receiver has jump edges, the data state machine is transferred from the current same type of circulation working state to the first different type of circulation working state, so that the data state machine does not transfer from the next same type of circulation working state to the N same type of circulation working state, and the real-time rate of the host sending the external data is larger than the ideal rate, namely, the level width of the detected RXD signal is smaller than the length of the ideal sampling period, all circulation working states corresponding to the self-adaptive compensation time are determined to be reduced, and a round of data processing operation is determined to be completed, so that the control working state is controlled to automatically track the change of the data bit of the external data received by the bus interface receiver in real time. On the premise that N is an odd number, when the data state machine is in any one of the first cycle working state to the (N-1)/2 th cycle working state, the phase-locked loop outputs a second logic level in the sampling time of the current cycle working state; when the data state machine is in any one of the (n+1)/2-th cycle working state to the N-th cycle working state, the phase-locked loop outputs a first logic level in the sampling time of the current one cycle working state; and the sum of sampling time of the cyclic working state which is actually transferred by the data state machine is equal to the actual sampling period. Wherein, when the first logic level represents logic 1, the second logic level represents logic 0; or the first logic level represents a logic 0 and the second logic level represents a logic 1.

As a third embodiment, in a scenario where the real-time rate of external data sent by the host is less than the ideal rate, the data state machine delays one of the adaptive compensation times to complete a round of data processing operation with respect to one of the first polling operations, that is, ends one of the first polling operations in a manner of delaying one of the adaptive compensation times, so as to increase polling of all first cyclic operating states corresponding to one of the adaptive compensation times, and then sets a sampling period formed by the delayed one of the first polling operations as a first actual sampling period; under the control of the data state machine, the phase-locked loop sets the logic level of a first circulation working state which is transferred to last in a first actual sampling period to be different from the logic level of a first circulation working state which corresponds to other sampling intervals in the same first actual sampling period, and controls the phase-locked loop to output the logic level which is newly set in the first actual sampling period under the corresponding transferred first circulation working state, and generates a first target sampling clock, so that the jump edge of the first target sampling clock is locked in the central sampling interval of the corresponding ideal sampling period; wherein the actual sampling period comprises a first actual sampling period and the target sampling clock comprises a first target sampling clock. It should be noted that the sampling interval in which the last cycle of operation state transferred to in the actual sampling period is located is a central position of an ideal sampling period matched in advance of the next polling operation, namely: the actual sampling period includes the complete sampling period of the current polling operation and the partial sampling period of the next polling operation, and the last first-cycle operating state transferred to must be transferred to the second-cycle operating state before the central position of the ideal sampling period matched by the next polling operation, because the clock jitter and the frequency offset of the external data and/or the sampling clock (actual sampling clock) in the present embodiment do not exceed the central position of the corresponding ideal sampling period.

In the third embodiment, when the real-time rate of the external data sent by the host is smaller than the ideal rate, that is, the level width of the signal of RXD is greater than the length of the ideal sampling period, as can be seen from fig. 2, the data state machine is shifted to STAT3, and when it is detected that RXD is logic 1, the data state machine is shifted from STAT3 to STAT0, which means that the time for which RXD remains logic 1 in the current first polling operation is greater than the ideal sampling period, and shifted to STAT0, and then it is determined that the next first polling operation is entered, and after the phase-locked loop completes the sampling operation at STAT0, the data state machine determines that a round of data processing operation is completed. Thus, in this embodiment, the data state machine transitions from STAT3 to STAT0 to increment all cyclic operating states corresponding to polling one of the adaptive backoff times in a new polling operation, delaying one of the adaptive backoff times to complete a round of data processing operation relative to one polling operation, ending the first polling operation by delaying one of the adaptive backoff times; in this embodiment, the ideal sampling period is adjusted to increase STAT0 corresponding to one unit sampling period to adapt to the change of the logic 1 level of RXD, so that the actual sampling period is equal to the level width of RXD in one actual sampling period, and clock data edge alignment is completed. When N is even, in the nth cycle operation state, if no jump edge occurs in the sampling time when the data bit currently sampled by the bus interface receiver maintains the same logic level, the data state machine transitions from the nth type of cycle operation state to the first type of cycle operation state according to the unit clock period, so as to determine that the polling operation is finished at the present time, and starts to execute the next polling operation until all types of cycle operation states corresponding to the adaptive compensation time are transitioned in the next polling operation, wherein in the next polling operation, before the transition to the nth/2+1th type of cycle operation state, the last type of cycle operation state corresponding to the adaptive compensation time is transitioned, and a round of data processing operation is determined to be completed, so that the change of the data bit of the external data received by the bus interface receiver in real time is automatically tracked in the data processing operation. In the nth/2 first cycle working state (STAT 1), if one data bit of the external data currently sampled by the bus interface receiver is the first logic level or the second logic level, that is, in the sampling time of the nth/2 first cycle working state, no matter whether a jump edge occurs, the data state machine is transferred from the nth/2 first cycle working state to the nth/2+1th first cycle working state according to the unit clock period. The type of the cyclic working state at the central position of the ideal sampling period can be controlled to be unchanged, so that the mutual locking function between the clock and the data is realized. Wherein, when the first logic level represents logic 1, the second logic level represents logic 0; or the first logic level represents a logic 0 and the second logic level represents a logic 1.

On the basis of the third embodiment, when N is equal to 4, as can be seen from fig. 2, when the data state machine is in STAT0 and STAT1, the phase-locked loop outputs logic 0 in the sampling time of the first cycle working state in which the phase-locked loop is currently located; when the data state machine is at STAT3 and STAT4, the phase-locked loop outputs a logic 1 within the sampling time of the current one-cycle operating state. On the premise that N is an even number, when the data state machine is in any one of the first to N/2 th cyclic working states, the phase-locked loop outputs a second logic level in the sampling time of the current cyclic working state; when the data state machine is in any one of the N/2+1 cycle working state to the N cycle working state, the phase-locked loop outputs a first logic level in the sampling time of the current cycle working state. Wherein, when the first logic level represents logic 1, the second logic level represents logic 0; or the first logic level represents a logic 0 and the second logic level represents a logic 1.

As an embodiment four, for each of the first cyclic operation state and the second cyclic operation state, when N is an odd number, the specific steps of the polling operation include: in each cycle working state, if the bus interface receiver samples that one data bit of external data does not jump, the data state machine is transferred from the current cycle working state to the next cycle working state until the data state machine is transferred to the N/2-1/2 th cycle working state; in the N/2-1/2 th cycle working state, if the bus interface receiver currently samples one data bit of external data to be a first logic level or a second logic level, namely when a jump edge is detected, the data state machine is transferred from the N/2-1/2 th cycle working state to the N/2+1/2 th cycle working state according to the unit clock period; in each cycle working state, if the bus interface receiver currently samples one data bit of external data to be a first logic level, the data state machine is transferred from the current cycle working state to the next cycle working state until the data state machine is transferred to the Nth cycle working state, so as to complete one polling operation; in the nth cycle working state, if one data bit of the external data sampled by the bus interface receiver currently is a first logic level, the data state machine is transferred from the nth cycle working state to a first same cycle working state according to the unit clock period so as to enter the next polling operation; in the nth cycle operation state, if the bus interface receiver samples that one data bit of the external data is at the second logic level, the data state machine transitions from the nth cycle operation state to the first another cycle operation state according to the unit clock period. Wherein, when the first logic level represents logic 1, the second logic level represents logic 0; or the first logic level represents a logic 0 and the second logic level represents a logic 1.

When N is odd, in the nth cycle operation state, if no jump edge occurs in the data bit currently sampled by the bus interface receiver, the data state machine transfers from the nth cycle operation state to the first cycle operation state according to the unit clock period, so as to determine that the polling operation is finished for the first time, and starts to execute the next polling operation until all cycle operation states corresponding to the adaptive compensation time are transferred in the next polling operation, wherein in the next polling operation, before transferring to the last cycle operation state corresponding to the adaptive compensation time, and determining that the real-time rate of sending external data by the host is smaller than the ideal rate, that is, the level width of a signal of RXD is detected to be larger than the length of an ideal sampling period, then determining that all cycle operation states corresponding to the adaptive compensation time are added, and automatically completing the data processing operation is performed, so as to realize that the real-time data of the bus interface receiver receives the data change of the data bit. It should be noted that, on the premise that N is an odd number, when the data state machine is in any one of the first to (N-1)/2 th cyclic operating states, the phase-locked loop outputs a second logic level within a sampling time of the current cyclic operating state; when the data state machine is in any one of the (n+1)/2-th cycle working state to the N-th cycle working state, the phase-locked loop outputs a first logic level in the sampling time of the current one cycle working state; and the sum of sampling time of the cyclic working state which is actually transferred by the data state machine is equal to the actual sampling period.

In the first to fourth embodiments, when the second logic level is represented as logic 0 and the first logic level is represented as logic 1, in the process of transferring between the first cycle operation states, if the current sampled data bit is logic 0, the sampled data bit is changed from logic 1 to logic 0, and a falling edge is detected, the external data is transferred from the first cycle operation state to the second cycle operation state, wherein the external data is configured to be sampled at the falling edge of the standard sampling clock in the second cycle operation state, and the continuously sampled data bit can be maintained to be transferred between the first cycle operation states only when the continuously sampled data bit is logic 1; and if the currently sampled data bit is logic 1 in the process of transferring between the first cycle working states on the premise that the second logic level is expressed as logic 1 and the first logic level is expressed as logic 0, the sampled data bit is changed from logic 1 to logic 1, no jump edge is detected, and the data state machine is not configured to transfer from the first cycle working state to the second cycle working state. Thus, by setting the edge sampling feature of the external data within each of the cyclic operating states, the functionality of the second logic level as a trigger signal for the transition of different types of cyclic operating states is limited.

As an implementation fifth, in the second polling operation, when the real-time rate of the external data sent by the host is greater than the ideal rate, that is, when the level width of the signal of RXD is smaller than the length of the ideal sampling period, as can be seen from fig. 2, on the premise that the signal of RXD maintains logic 0, the data state machine is shifted from STAT4 to STAT5, then from STAT5 to STAT6, and if it is detected that RXD is logic 0, the data state machine is shifted from STAT6 to STAT0, which means that the time that RXD is maintained as logic 1 in the current second polling operation is smaller than the ideal sampling period, and the current second polling operation is ended after shifting to STAT0, so as to determine that a round of data processing operation is completed. Thus, in this embodiment, the data state machine does not transition from STAT6 to STAT7, reduces polling of all second cyclic operating states corresponding to one of the adaptive backoff times, completes one round of data processing operation in advance of one of the adaptive backoff times, and ends one of the second polling operations in advance of one of the adaptive backoff times; in this embodiment, the ideal sampling period is adjusted to reduce STAT7 corresponding to one unit sampling period, so as to adapt to the change of the logic 0 level of RXD, and the actual sampling period is equal to the level width of RXD in one actual sampling period, so that clock data edge alignment is completed.

Therefore, when N is even, from the first same type of cyclic working state to the N/2-1 th same type of cyclic working state and from the N/2+1 th same type of cyclic working state to the N-1 th same type of cyclic working state, in each same type of cyclic working state, if a jump edge occurs on a data bit currently sampled by the bus interface receiver, the data state machine is transferred from the current same type of cyclic working state to the first different type of cyclic working state, so that the data state machine does not transfer from the next same type of cyclic working state to the N same type of cyclic working state, a round of data processing operation is determined to be completed, and the control working state is realized to automatically track the change of the data bit of external data received by the bus interface receiver in real time. In the nth/2 second cycle working state (STAT 5), if the bus interface receiver currently samples one data bit of external data to be at the first logic level or the second logic level, the data state machine transitions from the nth/2 second cycle working state to the nth/2+1th second cycle working state according to the unit clock period. The type of the cyclic working state at the central position of the ideal sampling period can be controlled to be unchanged, so that the mutual locking function between the clock and the data is realized.

On the basis of the fifth embodiment, when N is equal to 4, as can be seen from fig. 2, when the data state machine is in STAT4 and STAT5, the phase-locked loop outputs logic 0 in the sampling time of the current second cycle working state; when the data state machine is in STAT6 and STAT7, the phase-locked loop outputs a logic 1 during the sampling time of a second cyclic operating state currently in. To form a target sampling clock within one actual sampling period.

It should be noted that, in the second polling operation, when N is an odd number, the data state machine may refer to the operation rule of the cyclic working state in the second embodiment to cope with an implementation scenario that the real-time rate of the host sending the external data is greater than the ideal rate, so as to complete a round of data processing operation.

As an embodiment six, when the real-time rate of the external data sent by the host is smaller than the ideal rate, that is, when the level width of the signal of RXD is greater than the length of the ideal sampling period, as can be seen with reference to fig. 2, on the premise that the signal of RXD maintains logic 0, the data state machine is transferred from STAT4 to STAT5, then from STAT5 to STAT6, then from STAT6 to STAT7, if it is detected that RXD is logic 1, the data state machine is transferred from STAT7 to STAT4, which means that the time for RXD to maintain logic 0 in the current second polling operation is greater than the ideal sampling period, and then transfers to STAT4, then it is determined that the next second polling operation is entered, and it is determined that a round of data processing operation is completed. Thus, in this embodiment, the data state machine is shifted from STAT7 to STAT4 to increment all cyclic operating states corresponding to polling one of the adaptive backoff times in a new second polling operation, delaying one of the adaptive backoff times from completing one of the data processing operations relative to one of the second polling operations, ending one of the second polling operations in a manner that delays one of the adaptive backoff times; in this embodiment, the ideal sampling period is adjusted to increase STAT4 corresponding to one unit sampling period to adapt to the change of the logic 0 level of RXD, so that the actual sampling period is equal to the level width of RXD in one actual sampling period, and clock data edge alignment is completed. When N is even, in the nth cycle working state, if the data bit currently sampled by the bus interface receiver does not have a jump edge, the data state machine transfers from the nth same type of cycle working state to the first same type of cycle working state according to the unit clock period so as to determine that the current polling operation is finished, and starts to execute the next polling operation until all the same type of cycle working states corresponding to the self-adaptive compensation time are transferred in the next polling operation, thereby realizing automatic tracking of the change of the data bit of the external data received by the bus interface receiver in real time in the data processing operation; before transferring to the N/2+1-th same-type cyclic working state in the next polling operation, transferring to the last same-type cyclic working state corresponding to the adaptive compensation time, and determining that a round of data processing operation is completed; in the nth/2 th first cycle working state (STAT 1), if the bus interface receiver currently samples one data bit of external data to be at the first logic level or the second logic level, the data state machine is transferred from the nth/2 th first cycle working state to the nth/2+1 th first cycle working state according to the unit clock period. The type of the cyclic working state at the central position of the ideal sampling period can be controlled to be unchanged, so that the mutual locking function between the clock and the data is realized.

On the basis of the sixth embodiment, when N is equal to 4, as can be seen from fig. 2, when the data state machine is in STAT4 and STAT5, the phase-locked loop outputs logic 0 in the sampling time of the current second cycle working state; when the data state machine is in STAT6 and STAT7, the phase-locked loop outputs a logic 1 during the sampling time of a second cyclic operating state currently in. To form a target sampling clock within one actual sampling period.

It should be noted that, in the second polling operation, when N is an odd number, the data state machine may refer to the operation rule of the cyclic operation state according to the fourth embodiment to cope with an implementation scenario that the real-time rate of the host sending the external data is greater than the ideal rate, so as to complete a round of data processing operation.

It should be noted that, in the fifth to sixth embodiments, when the second logic level is denoted as logic 1 and the first logic level is denoted as logic 0, in the process of transferring between the second cycle operating states, if the current sampled data bit is denoted as logic 1, the sampled data bit is changed from logic 0 to logic 1, and the rising edge is detected, the external data is transferred from the second cycle operating state to the first cycle operating state, where the external data is configured to be sampled at the rising edge of the standard sampling clock in the first cycle operating state, and the continuously sampled data bit is maintained to be transferred between the second cycle operating states when the continuously sampled data bit is logic 0; and if the currently sampled data bit is logic 0 in the process of transferring between the second cycle working states on the premise that the second logic level is expressed as logic 0 and the first logic level is expressed as logic 1, the sampled data bit is maintained as logic 0, no jump edge is detected, and the data state machine is not configured to transfer from the second cycle working state to the first cycle working state. Thus, by setting the edge sampling feature of the external data within each of the cyclic operating states, the functionality of the second logic level as a trigger signal for the transition of different types of cyclic operating states is limited.

As an embodiment, the data state machine is further configured with at least one first initial operating state and at least one second initial operating state; the ratio of the number of pulses of the synchronous domain of the external data to the preset sampling times is equal to the number of first initial working states, and the number of the first initial working states is equal to the number of second initial working states; the data bits received by the bus interface receiver in the first initial working state and the second initial working state are synchronous fields belonging to the external data.

The data state machine is used for entering a first initial working state before starting the cycle transfer of the first cycle working state or before starting the cycle transfer of the second cycle working state, and after the clock self-adaptive recovery system is reset, if the data bit received by the bus interface receiver is at a first logic level; in the first initial working state, if the data bit received by the bus interface receiver is at a first logic level, maintaining the first initial working state; in the first initial working state, if the data bit received by the bus interface receiver is at the second logic level, transferring from the first initial working state to the second initial working state; in the second initial working state, if the data bit received by the bus interface receiver is at the second logic level, maintaining the second initial working state; in the second initial working state, if the data bit received by the bus interface receiver is at the first logic level, transferring from the second initial working state to the first initial working state, and circularly transferring until the ratio of the number of pulses of the synchronous domain of the external data to the preset sampling times is equal to the number of traversed second initial working states, and transferring from the second initial working state to the first circular working state so as to adapt to the jump edge of the synchronous domain of the external data transmitted by the bus interface; the phase-locked loop is at a second logic level in a sampling time stage of a first initial working state, and the phase-locked loop is at the second logic level in a sampling time stage of a second initial working state; wherein, when the first logic level represents logic 1, the second logic level represents logic 0; or the first logic level represents a logic 0 and the second logic level represents a logic 1. According to the embodiment, the data bits are synchronously processed in a mode of continuously detecting the jump edges, so that the sampling clock is synchronous with the sampling clock after continuously sampling the jump edges of two identical change trends of the synchronous packet headers of external data transmitted by the host. And the stability and the anti-interference performance of sampling are improved. Avoiding abrupt change in the gap of the synchronous domain from influencing the normal sampling of the data bit. It should be noted that, in each cyclic operation state, the phase-locked loop samples a valid data segment of external data, where the external data includes a synchronization field and a valid data segment.

Preferably, when the bus interface is a USB interface, the synchronization field of the external data transmitted by the USB interface includes 8 pulse signals of 12Mhz, and the preset sampling frequency is 4, and the number of the first initial working states is configured to be 2, so that the standard sampling clock of 48Mhz can detect two rising edges in the synchronization field. As can be seen from fig. 2, IDLE represents a first initial operation state, and IDLE1 represents a second initial operation state; the loop transfer for initialization of the data state machine is as follows: under IDLE, if the bus interface receiver samples one bit RXD of the external data currently as logic 1, the data state machine keeps the IDLE unchanged; if RXD is logic 0, the data state machine is transferred from IDLE to IDLE1, indicating that the first transition edge was detected. Wherein the initial state of RXD is logic 1 under IDLE. Under IDLE1, if the bus interface receiver currently samples one data bit RXD of external data to be logic 0, the data state machine keeps IDLE1 unchanged; if RXD is logic 1, the data state machine is transferred from IDLE1 to STAT0. Indicating that the second jump edge is detected, completing initialization, and starting to sample the effective data segment under the dispatching of the data state machine. And realizing the synchronous processing of the external data transmitted by the bus interface.

When the real-time rate of the external data is smaller than the ideal rate, the time length occupied by the level of one bit of the sampled external data under the sampling action of a standard sampling clock is longer than the length of the ideal sampling period; when the real-time rate of the external data is greater than the ideal rate, the time length occupied by the logic level of one bit of the external data under the sampling action of a standard sampling clock is smaller than the length of the ideal sampling period. The real-time rate of the external data is represented by the time length occupied by the logic level of the bit (the level width of the data bit of the same logic level) based on the clock jitter, the frequency offset and the phase offset of the data bit of the external data relative to the sampling clock, so that the comparison with the ideal rate (corresponding ideal sampling period) is facilitated.

Preferably, when the bus interface is a USB interface, a frequency difference between a clock frequency of the target sampling clock and an ideal frequency of the standard sampling clock is within a precision range required by a USB protocol, so as to ensure that a working state of the data state machine operates and converts normally at a corresponding clock node. Under this solution, for Full Speed transmission (Full Speed) in the USB1.1 specification, since its Speed is not very high, a 48MHz clock operating locally can be used, and the frequency difference is adaptively compensated by the aforementioned data state machine to generate the target sampling clock for correctly sampling 12Mbit/s data.

A chip comprising the clock adaptive recovery system. Considering hardware implementation, the chip uses the data state machine to control the bus interface receiver to receive the external data transmitted by the bus interface by adopting the stable standard sampling clock generated by the gating clock module, and sends the external data to the data state machine to trigger the data state machine to transfer the working state, so that the phase-locked loop automatically adjusts the width of the sampling period to be suitable for the duration (actual sampling period) of the same bit of the sampled external data in the working state transfer process, and locks one jump edge of the target sampling clock for sampling at a fixed sampling position of the corresponding ideal sampling period by playing the phase locking function of the phase-locked loop, so that the level width of the target sampling clock is suitable for the real-time rate change of the external data, the synchronization of clock signals and digital signals is realized, namely the synchronization precision is ensured in a dynamic compensation mode, the correct clock data recovery function is completed, and the data is not easy to lose.

The foregoing embodiments are merely representative of several embodiments of the application, which are described in more detail and are not to be construed as limiting the scope of the application. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the application, which are all within the scope of the application.

Claims (16)

1. The clock self-adaptive recovery system based on the bus interface is characterized in that the clock self-adaptive recovery system is connected with a host through the bus interface; the clock self-adaptive recovery system comprises a bus interface receiver, a data state machine and a phase-locked loop;

The bus interface receiver is connected with the bus interface; the bus interface receiver is used for receiving external data sent by the host computer by adopting a pre-generated standard sampling clock; the standard sampling clock of the ideal frequency sets the sampling frequency of one bit of external data of the ideal rate as the preset sampling frequency in each ideal sampling period;

the bus interface receiver is connected with the data state machine, and the data state machine is used for starting the cyclic transition of the working state when the bus interface receiver starts to receive specific data bits of external data so as to start to execute a round of data processing operation;

The phase-locked loop is connected with the data state machine, and the data state machine is used for controlling a cyclic transfer mode of the working state, controlling the phase-locked loop to regulate and generate a target sampling clock on the basis, enabling an actual sampling period generated by the target sampling clock to adapt to the change of the real-time rate of external data sent by the host, and maintaining one jump edge of the target sampling clock to be locked in a central sampling interval of a corresponding ideal sampling period;

wherein the actual sampling period indicates that the logic level of the currently sampled bit remains the same for the same time.

2. The clock adaptive recovery system according to claim 1, wherein the data state machine is configured to control an operation state to automatically track a change of a data bit of external data received by the bus interface receiver in real time, and control a phase-locked loop to generate a target sampling clock according to a cyclic operation state actually polled by the data state machine in the data processing operation, so that a level width of the target sampling clock and a level width of the data bit of the external data are synchronously changed;

The sampling time maintained by the data state machine in each cycle working state is one unit clock period of the standard sampling clock, and the phase-locked loop samples one data bit of external data in each cycle working state and one data bit is one bit; the operating state includes a cyclical operating state.

3. The clock adaptive recovery system of claim 2, wherein the data state machine is configured to advance an adaptive compensation time to complete a round of data processing operation when a real-time rate at which external data is transmitted from the host is less than the ideal rate, such that the actual sampling period is adjusted to be less than the ideal sampling period;

the data state machine is used for delaying one self-adaptive compensation time to finish one round of data processing operation when the real-time rate of external data sent by the host is greater than the ideal rate, so that the actual sampling period is regulated to be greater than the ideal sampling period;

the ratio of the product of the preset sampling times and the unit clock period to the preset sampling error offset is the self-adaptive compensation time; the preset sampling error offset is of a pre-configured count and is determined by the frequency offset of the external data relative to the standard sampling clock.

4. The clock-adaptive recovery system of claim 3, wherein the cyclic operating states configured by the data state machine are divided into a first cyclic operating state and a second cyclic operating state, wherein a sum of the number of the first cyclic operating states and the number of the second cyclic operating states is equal to twice the preset sampling number, and the first cyclic operating state and the second cyclic operating state are cyclic operating states belonging to different types;

When the duty cycle of a round of data processing operations is equal to an ideal sampling period, a round of data processing operations is set by the data state machine to be performed by a polling operation; the polling operation is divided into a first polling operation and a second polling operation according to the type of the transferred cyclic working state;

the data state machine is used for starting the cycle transfer of the first cycle working state when the data bit received by the bus interface receiver is logic 1 after entering the cycle working state so as to start to execute a first polling operation and determine to start to execute a round of data processing operation;

And the data state machine is further used for starting the cycle transfer of the second cycle working state to start to execute a second polling operation and determining to start to execute a round of data processing operation if the data bit received by the bus interface receiver is logic 0 after entering the cycle working state.

5. The clock adaptive recovery system of claim 4, wherein the data state machine is configured to complete a round of data processing operation in advance of one round of polling operation by one adaptive compensation time, so as to reduce polling of all cyclic operating states corresponding to one adaptive compensation time in a corresponding round of polling operation, and set a sampling period formed by a currently completed round of data processing operation as an actual sampling period;

The data state machine controls the phase-locked loop to set the logic level from the central position of the ideal sampling period matched with the current polling operation to the logic level of the cyclic working state which is transferred to by the last in the actual sampling period to be different from the logic level of the cyclic working state which corresponds to the rest sampling periods in the same actual sampling period, and controls the phase-locked loop to output the logic level which is set in the actual sampling period under the corresponding cyclic working state which is transferred to the phase-locked loop, and a target sampling clock is generated, so that the jump edge of the target sampling clock is locked in the central sampling period of the corresponding ideal sampling period.

6. The clock-adaptive recovery system of claim 5, wherein the cyclic operating states of the data state machine configuration include N first cyclic operating states and M second cyclic operating states; wherein N is an integer greater than or equal to four, N is the preset sampling times, and the nth first cycle working state is used for indicating the sequence of the working state transition sequence; m is an integer greater than or equal to four, M is equal to N, and the Mth second cycle working state is used for indicating the sequence of the working state transition sequence;

when detecting that the real-time rate of the external data sent by the host is greater than the ideal rate, the cyclic transfer process of the cyclic working state of the same type controlled by the data state machine comprises the following steps:

When N is even, from the first same type of circulation working state to the N/2-1 th same type of circulation working state and from the N/2+1 th same type of circulation working state to the N-1 th same type of circulation working state, in each same type of circulation working state, if the bus interface receiver currently detects that a jump edge occurs on a data bit, the data state machine is transferred from the current same type of circulation working state to the first different type of circulation working state, so that the data state machine does not transfer from the next same type of circulation working state to the N same type of circulation working state, a round of data processing operation is determined to be completed, and the control working state is realized to automatically track the change of the data bit of external data received by the bus interface receiver in real time;

Or when N is odd number, from the first same type of circulation working state to the N/2-3/2 th same type of circulation working state, from the N/2+1/2 th same type of circulation working state to the N-1 th same type of circulation working state, in each same type of circulation working state, if the bus interface receiver currently detects that a jump edge occurs on a data bit, the data state machine is transferred from the current same type of circulation working state to the first different type of circulation working state, so that the data state machine does not transfer from the next same type of circulation working state to the N same type of circulation working state, a round of data processing operation is determined to be completed, and the control working state is realized to automatically track the change of the data bit of external data received by the bus interface receiver in real time.

7. The clock adaptive recovery system of claim 4, wherein the data state machine is further configured to delay one of the adaptive compensation times relative to one polling operation to complete one of the data processing operations, to increment all cyclic operating states corresponding to one of the adaptive compensation times for polling in a new polling operation, and to set a sampling period formed by the currently completed one of the data processing operations to an actual sampling period;

The data state machine controls the phase-locked loop to set the logic level from the central position of the ideal sampling period matched with the current polling operation to the logic level of the cyclic working state which is transferred to by the last in the actual sampling period to be different from the logic level of the cyclic working state which corresponds to the rest sampling periods in the same actual sampling period, and controls the phase-locked loop to output the logic level which is set in the actual sampling period under the corresponding transferred cyclic working state, and generates a target sampling clock, so that the jump edge of the target sampling clock is locked in the central sampling period of the corresponding ideal sampling period;

The last cycle working state transferred to in the actual sampling period is the central position of an ideal sampling period matched in advance of the next polling operation.

8. The clock-adaptive recovery system of claim 7, wherein the data state machine configured operating states comprise N first cycle operating states and M second cycle operating states; wherein N is an integer greater than or equal to four, N is equal to the preset sampling times, and the Nth first cycle working state is used for indicating the sequence of the working state transition sequence; m is an integer greater than or equal to four, M is equal to N, and the Mth second cycle working state is used for indicating the sequence of the working state transition sequence;

When the real-time rate of the external data sent by the host is smaller than the ideal rate, the cyclic transfer process of the cyclic working state of the same type controlled by the data state machine comprises the following steps:

When N is even, in the nth cycle operation state, if no jump edge occurs in the data bit currently sampled by the bus interface receiver, the data state machine transfers from the nth cycle operation state to the first cycle operation state according to the unit clock period, so as to determine that the polling operation is finished at the present time, and starts to execute the next polling operation until all the cycle operation states of the same type corresponding to the adaptive compensation time are transferred in the next polling operation, wherein in the next polling operation, before transferring to the nth/2+1th cycle operation state, the data state machine transfers to the last cycle operation state of the same type corresponding to the adaptive compensation time, and determines to complete a round of data processing operation, so as to automatically track the change of the data bit of the external data received by the bus interface receiver in real time in the data processing operation;

Or when N is an odd number, in the nth cycle operation state, if no jump edge occurs on the data bit currently sampled by the bus interface receiver, the data state machine transfers from the nth cycle operation state to the first cycle operation state according to the unit clock period, so as to determine that the polling operation is finished at the present time, and starts to execute the next polling operation until all cycle operation states of the same type corresponding to the adaptive compensation time are transferred in the next polling operation, wherein in the next polling operation, before transferring to the last cycle operation state of the same type corresponding to the adaptive compensation time, and determining to finish a round of data processing operation, so as to automatically track the change of the data bit of the external data received by the bus interface receiver in real time in the data processing operation.

9. The clock-adaptive recovery system according to any one of claims 5 to 8, wherein for each of the first cyclic operation state and the second cyclic operation state, when N is an even number, the specific step of the polling operation includes:

In each cycle working state, if one data bit of external data sampled by the bus interface receiver currently is a first logic level, the data state machine is transferred from the current cycle working state to the next cycle working state until the data state machine is transferred to the N/2 th cycle working state;

In the N/2 th cycle working state, if one data bit of the external data currently sampled by the bus interface receiver is at a first logic level or a second logic level, the data state machine is transferred from the N/2 th cycle working state to the N/2+1 th cycle working state according to the unit clock period;

In each cycle working state, if the bus interface receiver currently samples one data bit of external data to be a first logic level, the data state machine is transferred from the current cycle working state to the next cycle working state until the data state machine is transferred to the Nth cycle working state, so as to complete one polling operation;

in the nth cycle working state, if one data bit of the external data currently sampled by the bus interface receiver is at a second logic level, the data state machine is transferred from the nth cycle working state to the first other cycle working state according to the unit clock period; in the nth cycle working state, if one data bit of the external data sampled by the bus interface receiver currently is a first logic level, the data state machine is transferred from the nth cycle working state to a first same cycle working state according to the unit clock period so as to enter the next polling operation;

Wherein, when the first logic level represents logic 1, the second logic level represents logic 0; or the first logic level represents a logic 0 and the second logic level represents a logic 1.

10. The clock-adaptive recovery system according to any one of claims 5 to 8, wherein for each of the first cyclic operation state and the second cyclic operation state, when N is an odd number, the specific step of the polling operation includes:

In each cycle working state, if the bus interface receiver currently samples one data bit of external data to be a first logic level, the data state machine is transferred from the current cycle working state to the next cycle working state until the data state machine is transferred to the N/2-1/2 th cycle working state;

In the N/2-1/2 th cycle working state, if the bus interface receiver currently samples one data bit of external data to be a first logic level or a second logic level, the data state machine is transferred from the N/2-1/2 th cycle working state to the N/2+1/2 th cycle working state according to the unit clock period;

in each cycle working state, if the bus interface receiver currently samples one data bit of external data to be a first logic level, the data state machine is transferred from the current cycle working state to the next cycle working state until the data state machine is transferred to the Nth cycle working state, so as to complete one polling operation;

In the nth cycle working state, if one data bit of the external data sampled by the bus interface receiver currently is a first logic level, the data state machine is transferred from the nth cycle working state to a first same cycle working state according to the unit clock period so as to enter the next polling operation; in the nth cycle working state, if one data bit of the external data currently sampled by the bus interface receiver is at a second logic level, the data state machine is transferred from the nth cycle working state to the first other cycle working state according to the unit clock period;

Wherein, when the first logic level represents logic 1, the second logic level represents logic 0; or the first logic level represents a logic 0 and the second logic level represents a logic 1.

11. The clock-adaptive recovery system according to any one of claims 5 to 8, wherein for each of the first and second cyclic operating states, the target sampling clock is specifically:

On the premise that N is an even number, when the data state machine is in any one of a first cycle working state to an N/2 th cycle working state, the phase-locked loop outputs a second logic level in the sampling time of the current cycle working state; when the data state machine is in any one of the (N/2+1) th to (N) th cyclic working states, the phase-locked loop outputs a first logic level in the sampling time of the current cyclic working state;

on the premise that N is an odd number, when the data state machine is in any one of the first cycle working state to the N/2-1/2 th cycle working state, the phase-locked loop outputs a second logic level in the sampling time of the current cycle working state; when the data state machine is in any one of the N/2+1/2 cycle working state to the N cycle working state, the phase-locked loop outputs a first logic level in the sampling time of the current cycle working state;

wherein, when the first logic level represents logic 1, the second logic level represents logic 0; or the first logic level represents a logic 0 and the second logic level represents a logic 1;

And the sum of sampling time of the cyclic working state which is actually transferred by the data state machine is equal to the actual sampling period.

12. The clock-adaptive recovery system of any one of claims 4 to 8, wherein the data state machine is further configured with at least one first initial operating state and at least one second initial operating state; the ratio of the number of pulses of the synchronous domain of the external data to the preset sampling times is equal to the number of first initial working states, and the number of the first initial working states is equal to the number of second initial working states; the bus interface receiver receives data bits in a first initial working state and a second initial working state, wherein the data bits received by the bus interface receiver in the first initial working state and the second initial working state are synchronous fields belonging to the external data;

the data state machine is used for entering a first initial working state before starting the cycle transfer of the first cycle working state or before starting the cycle transfer of the second cycle working state, and after the clock self-adaptive recovery system is reset, if the data bit received by the bus interface receiver is at a first logic level;

In the first initial working state, if the data bit received by the bus interface receiver is at a first logic level, maintaining the first initial working state; in the first initial working state, if the data bit received by the bus interface receiver is at the second logic level, transferring from the first initial working state to the second initial working state;

In the second initial working state, if the data bit received by the bus interface receiver is at the second logic level, maintaining the second initial working state; in the second initial working state, if the data bit received by the bus interface receiver is at the first logic level, transferring from the second initial working state to the first initial working state, and circularly transferring until the ratio of the number of pulses of the synchronous domain of the external data to the preset sampling times is equal to the number of traversed second initial working states, and transferring from the second initial working state to the first circular working state so as to adapt to the jump edge of the synchronous domain of the external data transmitted by the bus interface;

The phase-locked loop is at a second logic level in a sampling time stage of a first initial working state, and the phase-locked loop is at the second logic level in a sampling time stage of a second initial working state;

Wherein, when the first logic level represents logic 1, the second logic level represents logic 0; or the first logic level represents a logic 0 and the second logic level represents a logic 1.

13. The clock-adaptive recovery system of claim 12, wherein when the real-time rate of the external data is less than the ideal rate, it means that the external data is occupied by the level of one bit sampled by the sampling action of one standard sampling clock for a longer period of time than the ideal sampling period; when the real-time rate of the external data is greater than the ideal rate, the time length occupied by the logic level of one bit of the external data under the sampling action of a standard sampling clock is smaller than the length of the ideal sampling period.

14. The clock adaptive recovery system of claim 10, wherein if the currently sampled data bit is a logical 0 during the transition between the first loop operating states, the data state machine is configured to transition from the first loop operating state to the second loop operating state if the second logic level is a logical 0 and the first logic level is a logical 1;

If the currently sampled data bit is logic 0 in the process of transferring between the second cycle working states on the premise that the second logic level is expressed as logic 0 and the first logic level is expressed as logic 1, the data state machine is not configured to transfer from the second cycle working state to the first cycle working state;

If the currently sampled data bit is logic 1 in the process of transferring between the second cyclic working states on the premise that the second logic level is expressed as logic 1 and the first logic level is expressed as logic 0, the data state machine is configured to transfer from the second cyclic working state to the first cyclic working state;

in the process of transferring between the first cycle working states, if the currently sampled data bit is logic 1, the data state machine is not configured to transfer from the first cycle working state to the second cycle working state on the premise that the second logic level is expressed as logic 1 and the first logic level is expressed as logic 0.

15. The clock-adaptive recovery system according to any one of claims 1 to 8, wherein when the bus interface is a USB interface, a frequency difference between a clock frequency of the target sampling clock and an ideal frequency of the standard sampling clock is within a precision range required by a USB protocol, so as to ensure that an operating state of the data state machine is normally operated and converted at a corresponding clock node.

16. A chip, characterized in that the chip comprises the clock-adaptive recovery system according to any one of claims 1 to 15 inside.