CN107329915A - Recover the method and system of low speed data by high speed SerDes interfaces - Google Patents
Recover the method and system of low speed data by high speed SerDes interfaces Download PDFInfo
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- CN107329915A CN107329915A CN201710399941.0A CN201710399941A CN107329915A CN 107329915 A CN107329915 A CN 107329915A CN 201710399941 A CN201710399941 A CN 201710399941A CN 107329915 A CN107329915 A CN 107329915A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/10—Program control for peripheral devices
- G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
- G06F13/124—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine
- G06F13/128—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine for dedicated transfers to a network
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
Abstract
The invention discloses a kind of method and system for recovering low speed data by high speed SerDes interfaces, it is related to communication technical field.This method comprises the following steps：The low speed data of input is converted to by over-sampling parallel data by high speed SerDes interfaces, the bit wide of over-sampling parallel data is over-sampling multiplying power m integral multiple；Over-sampling parallel data is extracted in batches is used as target data, the data bit digit of every batch of target data is identical with the bit wide of over-sampling parallel data, target data is carried out after 1bit displacements with target data two-by-two XOR to obtain the hopping edge position of over-sampling parallel data；The sampling point position of over-sampling parallel data is determined according to hopping edge position, the data corresponding to sampling point position are the valid data of low speed data, from the sampling point position extracted valid data of over-sampling parallel data.The present invention recovers low speed data, reduction chip design risk and cost using existing high speed SerDes interfaces, shortens the construction cycle.
Description
The present invention relates to communication technical field, it is specifically related to a kind of recover low speed data by high speed SerDes interfaces
Method and system.
Background technology
With the fast development of ASIC design and IC making technologies, it is used for high speed data transfer in the chip of communication equipment
Serializer-deserializerSERDES (Serializer/Deserializer, SerDes) interface rate is quickly improved, at present major IC manufactures
The general SerDes interface rates of manufacturer are general between 1Gbps and 28Gbps, can meet from 1G Ethernets
(IEEE802.3z/ab) demand of 100G Ethernets (IEEE802.3ba/bj) is arrived.Due to historical reasons, current Ethernet net
There are still the interface that a large amount of speed are less than 1Gbps in network, typical low speed Ethernet interface speed is 100Mbps
Or 10Mbps (IEEE802.3u).Lock is improved to support higher rate signal due to existing high speed SerDes interfaces IP
Phase ring centre frequency, existing high speed SerDes interfaces IP can not have been supported directly by its clock data recovery unit
(Clock Data Recovery CDR) recovers 100,000,000 data.
In order to support the low speed SerDes interface IP in ethernet network, continue to use past low speed processes and low speed
SerDes interface IP design chips, will cause the defect of whole chip low speed and high power consumption.Under existing manufacturing process again
Low speed SerDes interface IP are researched and developed, or old low speed SerDes interfaces IP is transplanted on new deep submicron process,
The cost that it is researched and developed is very big, the risk that there is adaptation new technology, and old SerDes interfaces IP demand is little, leads
Cause cost higher, deficiency in economic performance.
The content of the invention
For defect present in prior art, it is a primary object of the present invention to provide one kind to connect by high speed SerDes
The method that mouth recovers low speed data, another object of the present invention is to provide a kind of high speed SerDes interfaces that pass through to recover low speed number
According to system, using existing high speed SerDes sampling interfaces are by the low speed data of input and are converted to over-sampling parallel data,
Low speed data is recovered from over-sampling parallel data by Digital Logic method, existing high speed can maximally utilised
On the basis of SerDes interfaces, meet the requirement of low speed Ethernet interface, save the port of chip, reduction chip design risk with
And cost, shorten the construction cycle.
The present invention provides a kind of method for recovering low speed data by high speed SerDes interfaces, and methods described includes following step
Suddenly：
The low speed data of input is converted to by over-sampling parallel data, over-sampling parallel data by high speed SerDes interfaces
Bit wide be over-sampling multiplying power integral multiple；
Over-sampling parallel data is extracted in batches as target data, and the data bit digit and over-sampling of every batch of target data are simultaneously
The bit wide of row data is identical, target data is carried out after 1bit displacements with target data two-by-two XOR to obtain over-sampling and line number
According to hopping edge position；
The sampling point position of over-sampling parallel data is determined according to hopping edge position, the data corresponding to sampling point position are
The valid data of low speed data, from the sampling point position extracted valid data of over-sampling parallel data.
On the basis of above-mentioned technical proposal, after being shifted to target data with target data two-by-two XOR to obtain
Before the hopping edge position of over-sampling parallel data, methods described also includes：N number of accumulator, N number of accumulator and number of targets are set
According to N number of data bit correspond.
On the basis of above-mentioned technical proposal, target data is carried out after 1bit displacements with target data two-by-two XOR to obtain
Obtaining the hopping edge position of over-sampling parallel data includes：
By the every batch of target data shift after 1bit with target data XOR two-by-two, according to each data bit of target data
XOR result determine whether hopping edge, be determined as the accumulative saltus step time of accumulator corresponding to the data bit of hopping edge
Number；
In the preceding m data position of the every batch of target data, will add up in default period of time T transition times it is most and
More than the hopping edge position that the data bit corresponding to the accumulator of given threshold is determined as over-sampling parallel data.
On the basis of above-mentioned technical proposal, judging the hopping edge position of over-sampling parallel data includes：
, will be in default period of time T in the preceding m data position of every batch of target data into hopping edge search condition
Interior accumulative transition times at most and more than given threshold accumulator corresponding to data bit be determined as over-sampling parallel data
Hopping edge position, into hopping edge accumulated state, otherwise re-searches for the hopping edge position in target data；
In hopping edge accumulated state, when the hopping edge position in continuous n period of time T is identical, into hopping edge lock
Determine state, otherwise re-search for the hopping edge position in target data；
In hopping edge lock-out state, the accumulator corresponding to real-time detection hopping edge position and adjacent data bit is pre-
If period of time T in the transition times that add up, by accumulative transition times at most and more than the accumulator correspondence of given threshold
Data bit as the hopping edge position after renewal, otherwise, re-search for the hopping edge position in target data.
On the basis of above-mentioned technical proposal, the sampling point position of over-sampling parallel data is determined according to hopping edge position
Method is：Sampling point position=hopping edge position+over-sampling multiplying power m/2.
On the basis of above-mentioned technical proposal, include from the sampling point position extracted valid data of over-sampling parallel data：
Real-time reception target data and sampling point position；
When currently received sampling point position is in m-1 of target data, and the last sampling point position received
At the 0th, judge that SF occurs for sampling point position, regard the 0th of target data the, m-1 and 2m-1 as valid data
Output；
When currently received sampling point position exists in the 0th of target data, and the last sampling point position received
At m-1, judge that shift reverse occurs for sampling point position, m-1 of target data are exported as valid data；
Otherwise, the data bit of the target data corresponding to currently received sampling point position and the second sampling point position is made
Exported for valid data, the second sample is set to currently received sampling point position+m divided by the digit of every batch of target data takes
Remainder.
On the basis of above-mentioned technical proposal, methods described also includes：By the valid data of low speed data according to predetermined
Bit wide and clock frequency are converted to the output of NRZI codes.
The present invention also provides a kind of system for recovering low speed data by high speed SerDes interfaces, and it includes：
Sampling module, it is used to the low speed data of input is converted into over-sampling and line number by high speed SerDes interfaces
According to the bit wide of over-sampling parallel data is over-sampling multiplying power m integral multiple；
Hopping edge judging module, it is used to extract over-sampling parallel data in batches as target data, every batch of target data
Data bit digit it is identical with the bit wide of over-sampling parallel data, to target data carry out 1bit displacements after with target data two-by-two
XOR is to obtain the hopping edge position of over-sampling parallel data；
Data recovery module, it is used for the sampling point position that over-sampling parallel data is determined according to hopping edge position, sampling
Data corresponding to point position are the valid data of low speed data, and significant figure is extracted from the sampling point position of over-sampling parallel data
According to.
On the basis of above-mentioned technical proposal, the system also includes：
Data outputting module, it is used to be converted to the valid data of low speed data according to predetermined bit wide and clock frequency
NRZI codes are exported.
On the basis of above-mentioned technical proposal, hopping edge judging module includes N number of accumulator, N number of accumulator and number of targets
According to digit N correspond.
Compared with prior art, advantages of the present invention is as follows：
(1) using existing high speed SerDes sampling interfaces are by the low speed data of input and are converted to over-sampling and line number
According to recovering low speed data from over-sampling parallel data by Digital Logic method, existing height can maximally utilised
On the basis of fast SerDes interfaces, the requirement of low speed Ethernet interface is met, the port of chip, reduction chip design risk is saved
And cost, shorten the construction cycle.
(2) method searched in real time and lock hopping edge position is used for unstable over-sampling parallel data, not only
Data transfer is able to ensure that without error code, and in hopping edge lock-out state, it is only necessary to hopping edge position is detected in real time and adjacent
Data bit corresponding to accumulator in default period of time T add up transition times, effectively improve the effect of data recovery
Rate, meets the requirement of data transfer.
(3) sampling point position is adjusted according to the change of sampling point position in real time, further improves the correctness of data recovery,
Ensure data transfer without error code.
Brief description of the drawings
Fig. 1 is the method flow diagram that the embodiment of the present invention recovers low speed data by high speed SerDes interfaces；
Fig. 2 is the over-sampling parallel data hopping edge position that the embodiment of the present invention carries out ten sampling acquisitions to low speed data
Figure；
Fig. 3 is the system schematic that the embodiment of the present invention recovers low speed data by high speed SerDes interfaces.
Embodiment
The principle of the present invention is：100,000,000 low speed datas of input were adopted using existing high speed SerDes interfaces
Sample, and after serioparallel exchange, 100,000,000 low speed datas are reverted to the gigabit rate data stream of extension.Pass through Digital Logic
Method carries out signal hopping edge judgement, the result adjudicated according to hopping edge, in the gigabit speed data to gigabit rate data stream
The optimum sampling point of 100,000,000 low speed datas is found in stream.The 100000000 low speed numbers recovered are used as using the data-signal of sampled point
According to realization recovers 100,000,000 original data from high speed SerDes interfaces.
Below in conjunction with the accompanying drawings and specific embodiment the present invention is described in further detail.
Shown in Figure 1, the embodiment of the present invention provides a kind of method for recovering low speed data by high speed SerDes interfaces,
This method comprises the following steps：
S1. the low speed data of input is converted to by over-sampling parallel data by high speed SerDes interfaces, over-sampling is parallel
The bit wide of data is over-sampling multiplying power m integral multiple.
High speed Serdes interfaces provide sampling clock and work clock using phase-locked loop pll (Phase Locked Loop),
Using clock data recovery unit CDR (Clock and Data Recovery) according to sampling clock to low speed data (serial number
According to) m times of time over-sampling is carried out, and obtain over-sampling parallel data by serioparallel exchange.The bit wide of over-sampling parallel data is small
The maximum bit wide that can be exported in high speed SerDes interfaces, the bit wide M of over-sampling parallel data is over-sampling multiplying power m integral multiple a,
For example, over-sampling multiplying power m=10, a=2, then bit wide M=a*m=20bit, clock frequency is 62.5MHz, and high speed SerDes connects
Mouth speed is 1.25Gbps.
S2. over-sampling parallel data is extracted in batches as target data, and the data bit digit of every batch of target data is adopted with crossing
The bit wide of sample parallel data is identical, target data is carried out after 1bit displacements with target data two-by-two XOR to obtain over-sampling simultaneously
The hopping edge position of row data.
Before step S2, N number of data bit one-to-one corresponding of N number of accumulator, N number of accumulator and target data is set.Step
Rapid S2 includes：
By the every batch of target data shift after 1bit with target data XOR two-by-two, according to each data bit of target data
XOR result determine whether hopping edge, be determined as the accumulative saltus step time of accumulator corresponding to the data bit of hopping edge
Number.
In the preceding m data position of the every batch of target data, will add up in default period of time T transition times it is most and
More than the hopping edge position that the data bit corresponding to the accumulator of given threshold is determined as over-sampling parallel data.Wherein, judge
The hopping edge position of over-sampling parallel data includes：
, will be in default period of time T in the preceding m data position of every batch of target data into hopping edge search condition
Interior accumulative transition times at most and more than given threshold accumulator corresponding to data bit be determined as over-sampling parallel data
Hopping edge position, into hopping edge accumulated state, otherwise re-searches for the hopping edge position in target data.
In hopping edge accumulated state, when the hopping edge position in continuous n period of time T is identical, into hopping edge lock
Determine state, otherwise re-search for the hopping edge position in target data.
In hopping edge lock-out state, the accumulator corresponding to real-time detection hopping edge position and adjacent data bit is pre-
If period of time T in the transition times that add up, by accumulative transition times at most and more than the accumulator correspondence of given threshold
Data bit as the hopping edge position after renewal, otherwise, re-search for the hopping edge position in target data.
Adjacent data bit can be the previous position and latter position of hopping edge position when entering hopping edge lock-out state,
Adjacent data bit can be flexibly determined according to actual conditions, for example, can be hopping edge position when entering lock-out state
Front and rear each two, or front and rear each three etc..
For unstable over-sampling parallel data using the method searched in real time and lock hopping edge position, it is not only able to
Data transfer is ensured without error code, and in hopping edge lock-out state, it is only necessary to hopping edge position and adjacent number are detected in real time
The transition times added up according to the accumulator corresponding to position in default period of time T, effectively improve the efficiency of data recovery, full
The requirement of sufficient data transfer.
S3. the sampling point position of over-sampling parallel data, the number corresponding to sampling point position are determined according to hopping edge position
According to the valid data for low speed data, from the sampling point position extracted valid data of over-sampling parallel data.
The method that the sampling point position of over-sampling parallel data is determined according to hopping edge position is：Sampling point position=saltus step
Along position+over-sampling multiplying power m/2.
Include from the sampling point position extracted valid data of over-sampling parallel data：
When currently received sampling point position is in m-1 of target data, and the last sampling point position received
At the 0th, judge that SF occurs for sampling point position, regard the 0th of target data the, m-1 and 2m-1 as valid data
Output.
When currently received sampling point position exists in the 0th of target data, and the last sampling point position received
At m-1, judge that shift reverse occurs for sampling point position, m-1 of target data are exported as valid data.
Otherwise, the data bit of the target data corresponding to currently received sampling point position and the second sampling point position is made
Exported for valid data, the second sampling point position is calculated according to currently received sampling point position and obtained, the second sampling point position
=(digit of currently received every batch of target data of sampling point position+mMOD), MOD is that currently received sampling point position+m is removed
Taken the remainder with the digit of every batch of target data.
Sampling point position is adjusted according to the change of sampling point position in real time, the correctness of data recovery is further improved, really
Data transfer is protected without error code.
It is right exemplified by clock frequency is 62.5MHz over-sampling parallel data below using the bit wide that is converted to as 20bit
Step S2 and S3 are specifically described.
Low speed data is carried out shown in the over-sampling parallel data hopping edge figure of ten sampling acquisitions referring to Fig. 2, over-sampling
Multiplying power m=10, a=2, bit wide M=a*m=20bit, clock frequency is 62.5MHz, and high speed SerDes interface rates are
1.25Gbps.The data bit digit N of every batch of target data is identical with the bit wide of over-sampling parallel data, i.e. N=M, then every batch of mesh
Mark the data bit digit N=M=20bit of data.
Over-sampling parallel data is extracted in batches as target data, target data is carried out after 1bit displacements with target data
XOR is as follows with the state transition flow for obtaining the hopping edge position of over-sampling parallel data two-by-two：.System electrification is laggard first
Enter hopping edge search condition, the transition detection result for now every time obtaining 20bit data XORs is added up by 20 accumulators, when
When some data bit bit is determined as hopping edge, then the transition times increase by 1 of the corresponding accumulator of the data bit, every default
Period of time T just finds out the most data bit bit of accumulative transition times from accumulator, exceedes in advance if there are accumulative transition times
The threshold value Threshold first set data bit Edge_cnt [i], that is, meet Edge_cnt [i]>Threshold, wherein, 0≤
I≤m-1, then be determined as hopping edge position by Edge_cnt [i], into hopping edge accumulated state.
In saltus step accumulated state, in continuous n period of time T, i.e. Iteration >=3 can for example set n=3,
If hopping edge position Edge_cnt [i] when entering saltus step accumulated state in continuous three period of time T is constant, and Edge_
cnt[i]>Threshold, then into hopping edge lock-out state, otherwise reenter hopping edge search condition.
Under the lock-out state of hopping edge, in every period of time T period, hopping edge position Edge_cnt can be only detected
The transition times of [i], previous and latter data bit bit (Edge_cnt [i-1] and Edge_cnt [i+1]).Continuous
In three period of time T periods, if hopping edge position Edge_cnt [i] accumulative transition times is at most and more than settings
Threshold value Threshold, then remain unchanged.When previous or latter data bit for detecting hopping edge position Edge_cnt [i]
The accumulative transition times in bit positions are at most and more than the threshold value Threshold of setting, then by hopping edge position Edge_cnt [i]
1 data bit bit is moved forward or rearward, if three data bit (Edge_cnt [i], Edge_cnt in continuous three T times
[i] and Edge_cnt [i+1]) be all not above threshold value Threshold, then reenter hopping edge search condition.
The hopping edge position detected according to step S2 hopping edges, sampling point position is obtained in SerDes outputs by calculating
20bit target datas in specific any two data bit, export just export two sampled points per 2mbit data under normal circumstances
Bitindx and bitindx+10.Bitindx and bitindx+10, sampling point position=hopping edge position Edge_cnt [i]+mistake
Sample multiplying power m/2, and during over-sampling multiplying power m=10, bitindx adds 5 equal to hopping edge position.
Real-time reception target data and sampling point position, when judging sampling point position, first determine whether currently received adopt
Whether the relation of sampling point position and the last sampling point position received, judge currently received sampling point position in target data
[m-1] bit bit, and the last sampling point position received is in the 0th bit bit of target data, if so, then sampling
Point position there occurs positive excursion, now should export [0], [m-1] and [2m- in currently received 2m bits bit target datas
1] three bits as low speed data valid data.If positive excursion does not occur for sampling point position, continue to judge currently to connect
The sampling point position of receipts whether target data the 0th bit bit, and the last sampling point position received is at [m-1]
Bit bit, if so, then sampling point position there occurs that negative sense drifts about, now should only output the in currently received target data
[m-1] bit is used as valid data.Otherwise, by the target corresponding to currently received sampling point position and the second sampling point position
The data bit of data is exported as valid data, and the second sampling point position is calculated according to currently received sampling point position and obtained,
Second sampling point position=(currently received sampling point position+m MOD M), MOD are that currently received sampling point position+m is removed
Taken the remainder with the digit M of every batch of target data.
Using existing high speed SerDes sampling interfaces are by the low speed data of input and are converted to over-sampling parallel data, lead to
Cross Digital Logic method and recover low speed data from over-sampling parallel data, existing high speed can maximally utilised
On the basis of SerDes interfaces, meet the requirement of low speed Ethernet interface, save the port of chip, reduction chip design risk with
And cost, shorten the construction cycle.
This method also includes：
S4. the valid data of low speed data are converted into the output of NRZI codes according to predetermined bit wide and clock frequency.
Using a register group come variable First Input First Output FIFO (the First Input of simulation input bit wide
First Output), FIFO input clock is 62.5Mhz, according to the result of low speed data regenerative process, will in each cycle
1st, 2 or 3 sampling point position bit write-ins FIFO, FIFO output clock are that the 25Mhz clocks produced are divided from 62.5Mhz, often
The individual cycle exports non-return-to-zero reversal phase coding NRZI (No Return Zero-Inverse) code element of 5bit bit wides from FIFO.
Shown in Figure 3, the embodiment of the present invention, which is also provided, a kind of to be recovered low speed data by high speed SerDes interfaces and is
System, the system includes sampling module, hopping edge judging module, data recovery module.
Sampling module is used to the low speed data of input is converted into over-sampling parallel data, mistake by high speed SerDes interfaces
The bit wide of sample-parallel data is over-sampling multiplying power m integral multiple.
Hopping edge judging module is used for extraction over-sampling parallel data in batches and is used as target data, the number of every batch of target data
It is identical with the bit wide of over-sampling parallel data according to position digit, target data is carried out after 1bit displacements with target data XOR two-by-two
To obtain the hopping edge position of over-sampling parallel data.Hopping edge judging module includes N number of accumulator, N number of accumulator and target
The digit N of data is corresponded.
Data recovery module is used for the sampling point position that over-sampling parallel data is determined according to hopping edge position, sample
The valid data that corresponding data are low speed data are put, from the sampling point position extracted valid data of over-sampling parallel data.
The system also includes data outputting module, and data outputting module is used for the valid data of low speed data according to predetermined
Bit wide and clock frequency be converted to after NRZI codes export.
The present invention is not limited to the above-described embodiments, for those skilled in the art, is not departing from
On the premise of the principle of the invention, some improvements and modifications can also be made, these improvements and modifications are also considered as the protection of the present invention
Within the scope of.The content not being described in detail in this specification belongs to prior art known to professional and technical personnel in the field.
Claims (10)
1. a kind of method for recovering low speed data by high speed SerDes interfaces, it is characterised in that methods described includes following step
Suddenly：
The low speed data of input is converted to by over-sampling parallel data, the position of over-sampling parallel data by high speed SerDes interfaces
A width of over-sampling multiplying power m integral multiple；
Over-sampling parallel data is extracted in batches as target data, data bit digit and over-sampling and the line number of every batch of target data
According to bit wide it is identical, target data is carried out after 1bit displacements with target data two-by-two XOR to obtain over-sampling parallel data
Hopping edge position；
The sampling point position of over-sampling parallel data is determined according to hopping edge position, the data corresponding to sampling point position are low speed
The valid data of data, from the sampling point position extracted valid data of over-sampling parallel data.
2. the method as claimed in claim 1 for recovering low speed data by high speed SerDes interfaces, it is characterised in that to mesh
Mark data shifted after with before target data two-by-two hopping edge position of the XOR to obtain over-sampling parallel data, the side
Method also includes：N number of data bit one-to-one corresponding of N number of accumulator, N number of accumulator and target data is set.
3. the method as claimed in claim 2 for recovering low speed data by high speed SerDes interfaces, it is characterised in that to target
XOR is included with the hopping edge position for obtaining over-sampling parallel data two-by-two with target data after data progress 1bit displacements：
By the every batch of target data shift after 1bit with target data XOR two-by-two, according to the different of each data bit of target data
Or result determines whether hopping edge, it is determined as that the accumulator corresponding to the data bit of hopping edge adds up a transition times；
In the preceding m data position of every batch of target data, transition times will be added up in default period of time T at most and be more than
Data bit corresponding to the accumulator of given threshold is determined as the hopping edge position of over-sampling parallel data.
4. the method as claimed in claim 3 for recovering low speed data by high speed SerDes interfaces, it is characterised in that judged
The hopping edge position of sample-parallel data includes：
Into hopping edge search condition, in the preceding m data position of every batch of target data, it will tire out in default period of time T
Meter transition times at most and more than the data bit corresponding to the accumulator of given threshold are determined as the saltus step of over-sampling parallel data
Along position, into hopping edge accumulated state, the hopping edge position in target data is otherwise re-searched for；
In hopping edge accumulated state, when the hopping edge position in continuous n period of time T is identical, shape is locked into hopping edge
State, otherwise re-searches for the hopping edge position in target data；
In hopping edge lock-out state, the accumulator corresponding to real-time detection hopping edge position and adjacent data bit is default
The transition times added up in period of time T, by accumulative transition times at most and more than the corresponding number of accumulator of given threshold
According to position as the hopping edge position after renewal, otherwise, the hopping edge position in target data is re-searched for.
5. the method as claimed in claim 1 for recovering low speed data by high speed SerDes interfaces, it is characterised in that according to jump
Become along position determine over-sampling parallel data sampling point position method into：Sampling point position=hopping edge position+over-sampling
Multiplying power m/2.
6. the method as claimed in claim 1 for recovering low speed data by high speed SerDes interfaces, it is characterised in that adopted from crossing
The sampling point position extracted valid data of sample parallel data includes：
Real-time reception target data and sampling point position；
When currently received sampling point position is in m-1 of target data, and the last sampling point position received is the 0th
During position, judge that SF occurs for sampling point position, the 0th of target data the, m-1 and 2m-1 are exported as valid data；
When currently received sampling point position is in the 0th of target data, and the last sampling point position received is in m-1
During position, judge that shift reverse occurs for sampling point position, m-1 of target data are exported as valid data；
Otherwise, using the data bit of the target data corresponding to currently received sampling point position and the second sampling point position as having
Data output is imitated, the second sample is set to the digit remainder of currently received sampling point position+m divided by every batch of target data
Number.
7. the method as claimed in claim 1 for recovering low speed data by high speed SerDes interfaces, it is characterised in that the side
Method also includes：The valid data of low speed data are converted to according to predetermined bit wide and clock frequency and exported after NRZI codes.
8. a kind of system for recovering low speed data by high speed SerDes interfaces, it is characterised in that including：
Sampling module, it is used to the low speed data of input is converted into over-sampling parallel data, mistake by high speed SerDes interfaces
The bit wide of sample-parallel data is over-sampling multiplying power m integral multiple；
Hopping edge judging module, it is used to extract over-sampling parallel data in batches as target data, the number of every batch of target data
It is identical with the bit wide of over-sampling parallel data according to position digit, target data is carried out after 1bit displacements with target data XOR two-by-two
To obtain the hopping edge position of over-sampling parallel data；
Data recovery module, it is used for the sampling point position that over-sampling parallel data is determined according to hopping edge position, sample
The valid data that corresponding data are low speed data are put, from the sampling point position extracted valid data of over-sampling parallel data.
9. the system as claimed in claim 7 for recovering low speed data by high speed SerDes interfaces, it is characterised in that the system
System also includes：
Data outputting module, it is used to the valid data of low speed data being converted to NRZI according to predetermined bit wide and clock frequency
Exported after code.
10. the system as claimed in claim 7 for recovering low speed data by high speed SerDes interfaces, it is characterised in that：Saltus step
Include the digit N one-to-one corresponding of N number of accumulator, N number of accumulator and target data along judging module.
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| CN112994684A (en) * | 2021-02-06 | 2021-06-18 | 北京集睿致远科技有限公司 | Clock data recovery circuit and serial data transmission method |
| CN113886300A (en) * | 2021-09-23 | 2022-01-04 | 珠海一微半导体股份有限公司 | Clock data self-adaptive recovery system and chip of bus interface |
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