CN102819282B - A kind of clock recovery circuit device and corresponding method - Google Patents
A kind of clock recovery circuit device and corresponding method Download PDFInfo
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- CN102819282B CN102819282B CN201210262622.2A CN201210262622A CN102819282B CN 102819282 B CN102819282 B CN 102819282B CN 201210262622 A CN201210262622 A CN 201210262622A CN 102819282 B CN102819282 B CN 102819282B
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Abstract
The present invention discloses a kind of clock recovery circuit device and corresponding method, wherein this device comprises: the traffic spike received is converted to the digital signal of standard by data prediction circuit, and exports to clock recovery circuitry; Clock recovery circuitry is by oscillator clocking, frequency information is obtained from the digital signal of standard, obtain control signal by the difference of the actual frequency obtained and target frequency, according to this control signal clock signal is calibrated in the accuracy rating met the demands; Control circuit opens and closes the calibration process of clock recovery circuitry, and configurable clock generator recovers corresponding parameter.The present invention can make the frequency of local clock and precision reach accuracy requirement required for decoded data stream.
Description
Technical field
The present invention relates to the clock circuit device in computer system, particularly relate to the clock recovery circuit device of system and corresponding method.
Background technology
Clock has vital role in the data transmission procedure of computer system.Receiving equipment needs clock signal to reception data of sampling; Transmitting apparatus needs data to be sent with certain speed.Therefore produce meet the demands frequency and the clock signal of precision also just become data to transmit in key.Such as, USB (UniversalSerialBus) 2.0 specification generally used, just proposes corresponding requirement to the clock used in data transmission, it specify the data pattern of quick data transfering stream signal.According to this USB2.0 specification, USB device can be divided into three kinds according to the height of traffic rate: low-speed mode, Full-Speed mode and fast mode.Meanwhile, having comparatively strict regulation for the work clock under different rates, is 1.5MHZ under low-speed mode, and precision is ± 1.5%; Be 12MHZ under Full-Speed mode, precision is ± 0.25%; Be 480MHZ under fast mode, precision is ± 0.05%.
Traditional clock generator is that this clock source elects crystal oscillator as usually, such as quartz crystal oscillator circuits or piezoelectric oscillator circuit based on using the clock source of chip exterior of clock to realize.Chip adjusts the reference clock that crystal oscillator produces, and makes it meet frequency needed for decoded data stream and accuracy requirement.But because crystal oscillator cannot be integrated on silicon circle crystalline substance usually, therefore this outer oscillator adds the cost of design for needing the chip of sheet internal oscillator, is thus not suitable for the embedded device harsher to the requirement such as area, power consumption.And, because crystal oscillator is easy to the destruction being subject to physical impact, be not thus suitable for portable equipment.There is provided in the computer system of reference clock traditional by external clock reference, conventional delay lock loop (DLL, or phase-locked loop (PLL DelayLockLoop), PhaseLockLoop) circuit comes with reference to clock lock to the frequency specified and precision, to meet the rate requirement of Received signal strength.This also can increase the cost of equipment.
At present, clock generator is generally to utilize on sheet oscillator to produce local clock.
What patent documentation 1 (US7093151) described is a kind of device producing local clock according to oscillator on sheet, and its structure as shown in Figure 3, comprises detecting device, counter, controller, programmable oscillator; Its course of work is: detecting device detects the time signal comprised in data stream, and counter counts clock signal clk between adjacent time signal, obtains count value CNT; Controller according to count value CNT query counts value-Configuration Values record sheet, and generates Configuration Values CN; Frequency to be adjusted within the accuracy rating of regulation according to this CN Configuration Values by programmable oscillator.This patent documentation 1 utilizes the mode of tabling look-up to carry out the frequency of oscillator on trim tab, and this needs larger internal memory to carry out data in storage list, and can increase the area of chip.And the method requires that the curve of oscillator frequency and parameter has strict linear corresponding relation, this just proposes very strict requirement to the technique of oscillator.Be difficult to reach this requirement in the occasion that range of temperature is larger.
The implementation that patent documentation 2 (US7120813) describes is: use the oscillator of a high speed to produce the clock signal of multiple out of phase, the frequency of these clock signals is more much higher than assigned frequency; Then the temporal information synthesis contained according to data stream packets meets the clock signal of accuracy requirement.The method of this patent documentation 2 will use the very high oscillator of a frequency, can increase the cost of design, needs the internal memory that larger simultaneously, and this also can increase the area of chip.
In current computer system, USB2.0 specification defines a kind of form of quick data transfering between main process equipment and USB device.As shown in Figure 1, traffic rate is under Full-Speed mode, and the transmission of data is in units of frame, and each frame data is all start with start frame (SOF, StartOfFrame) packet, terminates with end frame (EOF, EndOfFrame) mark.Main process equipment periodically sends SOF packet, and Frame is by strict time and accuracy limitations: the time span of each Frame in usb data stream is 1ms ± 500ns, and that is SOF packet can transmit on the data line with the time interval of 1ms.
According to the regulation of USB2.0 agreement, main frame and USB device realize the mutual of data by the differential signal transmitting a pair data-signal.In order to strengthen the anti-interference of data and maintain the activity of bus, data had carried out bit padding (Bit-Stuff) and reverse non-return-to-zero (NRZI, NonReturnToZeroInverted) coding before sending to bus.Bit padding refers to after data bus having occurred continuous print 61, will introduce 1 redundant digit 0 forcibly.Nrzi encoding mode and index according in " 0 " adopt the logic level saltus step of data starting point to represent, " 1 " in data then adopts and represents without level saltus step.Structural information and the nrzi encoding information of SOF packet as shown in Figure 2.Usb data bag is all with synchronizing sequence (Sync, 80H for fixing) start, then be the mark (PID of this packet, and the check field of PID (PIDB) PacketIdentifier), then be the CRC (CRC of the concrete data message of this packet and this data message again, CyclicRedundancyCheck), be finally this packet end mark EOP.Different data are surrounded by different PID, and have fixing coding; The data message of SOF packet is the frame number of this Frame, and the scope of frame number is 0 ~ 1023, and after reaching maximal value, zero restarts counting.Sync/PID/PIDB/EOP (2SE0+J) is fixing signal, can by realizing the detection of synchronizing sequence and PID sequence to the detection of SOF packet.
Can design so a kind of clock recovery circuit device, by USB full-speed device while reception SOF packet, the timing information using it to carry is to recover local clock.And it does not need look-up table, and multiple reference signal can be obtained in timing information interval.
Summary of the invention
Technical matters to be solved by this invention is to provide a kind of clock recovery circuit device and corresponding method, can make the requirement that the frequency accuracy of local clock reaches required.
In order to solve the problems of the technologies described above, the invention provides a kind of clock recovery circuit device, comprise the data prediction circuit, clock recovery circuitry and the control circuit that connect successively, wherein:
Data prediction circuit, for the traffic spike received being converted to the digital signal of standard, and exports to clock recovery circuitry;
Clock recovery circuitry, for passing through oscillator clocking, from the digital signal of described standard, obtain frequency information, obtain control signal by the difference of the actual frequency obtained and target frequency, according to this control signal clock signal is calibrated in the accuracy rating met the demands;
Control circuit, for opening and closing the calibration process of clock recovery circuitry, and configurable clock generator recovers corresponding parameter.
Further, clock recovery circuitry comprises the testing circuit, calibration pulse generative circuit, counter circuit, calibration circuit and the Parameter adjustable pierce circuit that connect successively, wherein:
Testing circuit, Connecting quantity tunable oscillator circuit, for producing detection signal according to the temporal information detected, and exports to calibration pulse generative circuit;
Calibration pulse generative circuit, for producing multiple calibration pulse signal according to detection signal, with the opening and closing of Time-sharing control counter circuit;
Counter circuit, for counting clock signal under the Time-sharing control of two calibration pulse signals, and exports to calibration circuit by count value;
Calibration circuit, under the control of control circuit according to the difference of the parameter value of count value and local maintenance, export to Parameter adjustable pierce circuit the control signal that data width is M position, M is positive integer;
Parameter adjustable pierce circuit, for also exporting to testing circuit sum counter circuit respectively by oscillator clocking, calibrates the frequency of clock signal by turn according to the control signal of M position;
The parameter of control circuit configuration comprises the reference value of counter circuit and the figure place of control signal participation calibration.
Further, testing circuit is also connected with counter circuit, wherein:
Testing circuit utilizes synchronization signal detection to produce detection signal after last bit of Packet Identifier, while exporting to calibration pulse generative circuit, also exports to counter circuit;
Counter circuit counts clock signal in course of normal operation under the control of two detection signals, and count value is exported to calibration circuit, determine whether clock signal is calibrated by this calibration circuit according to the difference of the parameter value of this count value and local maintenance.
Further, testing circuit comprises data recovery circuit and detection signal statement circuit, wherein:
Data prediction circuit is connected with data recovery circuit, the differential signal of a pair usb data received is converted to the reverse non-return-to-zero signal of standard, and exports to data recovery circuit;
Data recovery circuit, is connected with Parameter adjustable pierce circuit, for decoding to the reverse non-return-to-zero signal of standard according to clock signal, and the numeric string of generation is sent to detection signal statement circuit;
Detection signal statement circuit, produces circuit with described calibration pulse and is connected, for each generation detection signal of the digital signal that transmits according to data recovery circuit, and exports to calibration pulse generation circuit or counter circuit;
Counter circuit is opened and is counted clock signal after receiving first calibration pulse signal or first detection signal, after receiving next calibration pulse signal or next detection signal, close the counting to clock signal, export count value between adjacent calibration pulse signal or adjacent detection signal to calibration circuit;
Calibration circuit is L, L≤M by control circuit setup control signal adjustment figure place, first the L position of control signal is set to 0 entirely; Successively compare count value and reference value according to the L position of control signal, if count value is greater than described reference value, then successively the corresponding positions of the control signal of L position is adjusted to 1; If count value is less than or equal to reference value, then successively the corresponding positions of the control signal of L position is adjusted to 0; Until the lowest order of L position has adjusted, produce look-at-me to control circuit, the control signal of M position has been exported to Parameter adjustable pierce circuit simultaneously;
Parameter adjustable oscillator according to the frequency of the control signal of described M position alignment oscillator clock signal by turn, that is: f
cLOCK=k
0* f+k
1* f+......+k
m* f, this f are the frequency signal of oscillator reference, this k
m=0 or 1.
Further, also comprising the functional circuit of the clock signal using Parameter adjustable pierce circuit through calibration, realizing corresponding application function for using the clock signal through calibration.
In order to solve the problems of the technologies described above, the invention provides a kind of clock recovery method, relate to foregoing clock recovery circuit device, the method comprises:
Clock recovery circuitry is by internal oscillator clocking, frequency information is obtained in the digital signal of the standard received according to data prediction circuit and change, obtain control signal by the difference of the actual frequency obtained and target frequency, clock signal is calibrated in the accuracy rating met the demands according to this control signal.
Further, also comprised before the method performs:
After clock recovery circuit device electrification reset, clock recovery circuitry opened by control circuit, configures corresponding parameter simultaneously.
Further, frequency information is obtained in the digital signal of the standard that clock recovery circuitry receives according to data prediction circuit and changes, control signal is obtained by the difference of the actual frequency obtained and target frequency, clock signal is calibrated in the accuracy rating met the demands according to this control signal, specifically comprises:
Differential signal is converted to the reverse non-return-to-zero signal with usb data numerical coding form of standard, and exports to clock recovery circuitry after receiving the differential signal of two-way usb data by data prediction circuit;
Clock recovery circuitry produces detection signal by testing circuit according to the temporal information detected; Multiple calibration pulse signal is produced according to described detection signal by calibration pulse generative circuit; By counter circuit in a calibration process under the Time-sharing control of two calibration pulse signals, clock signal is counted; By the difference of calibration circuit according to the count value of counter circuit and the reference value of local maintenance, export the control signal that data width is M position, M is positive integer; Calibrated the frequency of clock signal by turn according to the control signal of M position by Parameter adjustable pierce circuit.
Further, testing circuit produces detection signal according to the temporal information detected, specifically comprises:
Testing circuit utilizes synchronization signal detection to produce detection signal after last bit of Packet Identifier, exports as the mark detecting start frame packet.
Further, the method also comprises:
Counter circuit counts clock signal in course of normal operation under the Time-sharing control of two detection signals, and count value is exported to described calibration circuit, by the difference of this calibration circuit according to the reference value of this count value and local maintenance, determine the calibration process whether entered clock signal.
Further, counter circuit, under the Time-sharing control of two calibration pulse signals or two detection signals, counts clock signal, specifically comprises:
The counting to clock signal opened by counter circuit after receiving first calibration pulse signal or first detection signal, after receiving next calibration pulse signal or next detection signal, close the counting to clock signal, and export the count value between adjacent calibration pulse signal or adjacent detection signal.
Further, calibration circuit, according to the difference of the count value of counter circuit and the reference value of local maintenance, exports the control signal that data width is M position, specifically comprises:
Calibration circuit is L, L≤M by control circuit setup control signal adjustment figure place, first the L position of control signal is set to 0 entirely; Successively compare count value and reference value according to the L position of control signal, if count value is greater than reference value, then successively the corresponding positions of the control signal of L position is adjusted to 1; If count value is less than or equal to reference value, then successively the corresponding positions of the control signal of L position is adjusted to 0; Until the lowest order of L position has adjusted, produce look-at-me to control circuit, the control signal of M position has been exported to Parameter adjustable pierce circuit simultaneously.
Further, Parameter adjustable pierce circuit calibrates the frequency of clock signal by turn according to the control signal of M position, specifically comprises:
Parameter adjustable oscillator according to the frequency of the control signal of M position alignment oscillator clock signal by turn, that is: f
cLOCK=k
0* f+k
1* f+......+k
m* f, this f are the frequency signal of oscillator reference, this k
m=0 or 1.
The present invention produces the lower clock signal of initial precision by the simple sheet internal oscillator of use one, adjusted the parameter of oscillator by control circuit according to the temporal information that data stream packets contains by turn, thus make the frequency of local clock and precision reach accuracy requirement required for decoded data stream.
Accompanying drawing explanation
Fig. 1 is the data stream transmitting pattern diagram that existing USB specification specifies;
Fig. 2 is SOF bit mode information and coding schematic diagram in existing usb data stream;
Fig. 3 is the existing device and the structural representation thereof that produce local clock according to oscillator on sheet;
Fig. 4 is the structured flowchart of clock recovery circuit device embodiment of the present invention;
Fig. 5 is the clock recovery circuit device embodiment alignment circuit working process flow diagram shown in Fig. 4;
Fig. 6 is clock recovery circuit device course of work process flow diagram of the present invention.
Embodiment
Below in conjunction with accompanying drawing and preferred embodiment, technical scheme of the present invention is further described.Should be appreciated that, the embodiment below enumerated only for instruction and explanation of the present invention, and does not form the restriction to technical solution of the present invention.
As shown in Figure 4, illustrate the structure of clock recovery circuit device embodiment of the present invention, comprise the data prediction circuit, clock recovery circuitry (in the empty frame of Fig. 4) and the control circuit that connect successively, wherein:
Data prediction circuit, for the traffic spike received (DATA) being converted to the digital signal (NRZI signal) of standard, and exports to clock recovery circuitry;
Clock recovery circuitry, for passing through oscillator clocking, from the digital signal of the standard of input, obtain frequency information, obtain control signal by the difference of the actual frequency obtained and target frequency, according to this control signal clock signal is calibrated in the accuracy rating met the demands;
Control circuit, for opening and closing the calibration process of clock recovery circuitry, and configurable clock generator recovers corresponding parameter.
In said apparatus embodiment, clock recovery circuitry comprises the testing circuit, calibration pulse generative circuit, counter circuit, calibration circuit and the Parameter adjustable pierce circuit that connect successively, wherein:
Testing circuit, Connecting quantity tunable oscillator circuit, produces detection signal (DET) for testing circuit according to the temporal information detected, and DET signal is exported to calibration pulse generative circuit;
Calibration pulse generative circuit, for producing multiple calibration pulse signal (TDs), with the opening and closing of Time-sharing control counter circuit according to the detection signal of input;
Counter circuit, for counting clock signal (CLOCK) under the Time-sharing control of two calibration pulse signals (TDs) in a calibration process, and exports to calibration circuit by count value;
USB2.0 specification specifies, the time interval between adjacent SOF packet is 1ms, and precision is ± 0.05%.Calibration pulse generative circuit produces N number of calibration pulse signal in 1ms, and wherein N is positive integer.
Calibration circuit, for under the control of control circuit according to the count value (representing actual frequency) of input and the difference of parameter value (representing target frequency) of local maintenance, be the control signal CON of M (M is positive integer) position to Parameter adjustable pierce circuit output data width;
Parameter adjustable pierce circuit, for exporting to testing circuit sum counter circuit respectively by oscillator clocking (CLOCK), will calibrate the frequency of clock signal by turn according to the control signal of M position;
The parameter of control circuit configuration comprises the reference value of counter circuit and the figure place of control signal participation calibration.
In said apparatus embodiment, testing circuit is also connected with counter circuit, wherein:
The detection signal (DET) that testing circuit produces also exports to counter circuit;
Counter circuit counts clock signal (CLOCK) in course of normal operation under the control of two detection signals (DET), and count value is exported to calibration circuit, by the difference of this calibration circuit according to the parameter value of this count value and local maintenance, determine whether clock signal is calibrated.
In said apparatus embodiment, testing circuit comprises data recovery circuit and detection signal statement circuit, wherein:
The differential signal of a pair usb data received (the usb data stream that usb host or router send) is converted to standard NRZI signal by data prediction circuit, and this NRZI signal is such as that the numerical coding form of usb data exports to data recovery circuit;
Data recovery circuit, be connected with data prediction circuit and Parameter adjustable pierce circuit respectively, the standard NRZI signal of clock signal to input for exporting according to Parameter adjustable pierce circuit is decoded, and the numeric string (0 or 1) produced is sent to detection signal statement circuit;
Detection signal statement circuit, produce circuit with calibration pulse to be connected, produce a detection signal (DET) for each of the digital signal (0 or 1) that transmits according to data recovery circuit, export to calibration pulse and produce circuit or counter circuit;
The clock signal counting to input opened by counter circuit after receiving first TD signal or first detection signal, close after receiving next TD signal or next detection signal clock signal counting, to export thus between adjacent TD signal or detection signal the count value of clock signal to calibration circuit;
It is L (L≤M) that calibration circuit adjusts figure place by control circuit setup control signal CON, first the L position of CON is set to 0 entirely; Count value and reference value (namely comparing actual frequency and target frequency) is successively compared from high to low according to the L position of CON, be greater than reference value (representing that actual frequency is higher than target frequency) if this comparative result is count value, then successively the corresponding positions of the CON of L position be adjusted to 1; If count value is less than or equal to reference value (representing that actual frequency is lower than target frequency), then successively the corresponding positions of the CON of L position is adjusted to 0; Until the lowest order of L position has adjusted, produce look-at-me (INT) to control circuit, the CON of M position has been exported to Parameter adjustable pierce circuit simultaneously;
Parameter adjustable pierce circuit according to the frequency of the control signal of M position (or reverse order) alignment oscillator clock signal by turn from high to low, that is: f
cLOCK=k
0* f+k
1* f+......+k
m* (f is the frequency signal of oscillator reference to f, k
m=0,1; M be more than or equal to zero integer).
By realizing the calibration of oscillator clock frequency to the adjustment by turn of control signal CON.Be spaced apart 1ms due to adjacent two SOF packets, precision is ± 0.05%, the precision of oscillator can be calibrated to ± 0.25% within.
In general, the initial precision forming the oscillator of local clock does not reach the requirement of decoded data stream, and after adjustment, the precision of local clock can meet application requirement.Such as, in certain application realizes, the frequency of clock is 12MHZ, and initial precision is less than 5%; After clock recovery circuitry calibration of the present invention, its precision can reach more than 0.25%, can meet the requirement of decoded data stream completely.
Said apparatus embodiment also comprises USB functional circuit, realizes USB transfer function for operation parameter tunable oscillator circuit through the clock signal of calibration.
Certainly, Parameter adjustable pierce circuit of the present invention also can be used for other function through the clock signal of calibration, such as the signal transfer functions of smart card, the inscription of CD or read functions etc.
In said apparatus embodiment, control circuit is made up of CPU, as shown in Figure 4.
The present invention is directed to said apparatus embodiment, correspondingly additionally provide clock recovery method embodiment, relate to clock recovery circuit device of the present invention, the method comprises the steps:
The traffic spike received is converted to the digital signal of standard by data prediction circuit, and exports to clock recovery circuitry;
Clock recovery circuitry is by oscillator clocking, frequency information is obtained from the digital signal of standard, obtain control signal by the difference of the actual frequency obtained and target frequency, clock signal is calibrated in the accuracy rating met the demands according to this control signal.
Said method embodiment also comprises:
After clock recovery circuit device electrification reset, clock recovery circuitry opened by control circuit, configures corresponding parameter simultaneously.
In said method embodiment, the traffic spike received is converted to the digital signal of standard by data prediction circuit, specifically comprises:
The differential signal of the two-way usb data received is converted to the NRZI signal with usb data numerical coding form of standard by data prediction circuit.
In said method embodiment, clock recovery circuitry is by oscillator clocking, frequency information is obtained from the digital signal of the standard of input, control signal is obtained by the difference of the actual frequency obtained and target frequency, clock signal is calibrated in the accuracy rating met the demands according to this control signal, specifically comprises:
Testing circuit produces detection signal according to the temporal information detected, and exports to calibration pulse generative circuit;
Calibration pulse generative circuit produces multiple calibration pulse signal (TDs), with the opening and closing of Time-sharing control counter circuit according to the detection signal of input;
Counter circuit, in a calibration process under the Time-sharing control of two calibration pulse signals, counts the clock signal that Parameter adjustable pierce circuit exports;
Calibration circuit according to the difference of the count value of counter circuit and the reference value of local maintenance, exports to Parameter adjustable pierce circuit the control signal CON that data width is M (M is positive integer) position under the control of control circuit;
Parameter adjustable pierce circuit calibrates the frequency of clock signal by turn according to the control signal of M position.
In said method embodiment, testing circuit produces detection signal according to the temporal information detected, and exports to calibration pulse generative circuit, specifically comprises:
Testing circuit utilizes synchronization signal detection to produce detection signal after Packet Identifier (PID) last bit, as detecting that the mark of SOF packet exports to calibration pulse generative circuit.
USB2.0 specification specifies, the time interval between adjacent SOF packet is 1ms, and precision is ± 0.05%.Full sized pules generative circuit produces N number of calibration pulse signal in 1ms, and wherein N is positive integer.
In said method embodiment, also comprise:
Counter circuit counts clock signal in course of normal operation under the Time-sharing control of two detection signals, and count value is exported to calibration circuit, by the difference of this calibration circuit according to the reference value of this count value and local maintenance, determine the calibration process whether entered clock signal.
In said method embodiment, counter circuit, in a calibration process under the Time-sharing control of two calibration pulse signals or two detection signals, counts the clock signal that Parameter adjustable pierce circuit exports, specifically comprises:
The counting to clock signal opened by counter circuit after receiving first calibration pulse signal TD or first detection signal DET, after receiving next TD signal or next DET signal, close the counting to clock signal, and export the count value between adjacent TD signal or DET signal.
Fig. 5 illustrates clock recovery circuit device embodiment alignment circuit working flow process, comprises the steps:
50: control signal CON most significant digit is set to 1, all the other positions are set to 0;
51: judge whether count value > reference value, be, represent that actual frequency is greater than target frequency, CON most significant digit is remained 1; Otherwise represent that actual frequency is less than or equal to target frequency, CON most significant digit is set to 0;
52: a CON high position is set to 1, all the other positions remain unchanged;
53: judge whether count value > reference value, be, a CON high position is set to 1; Otherwise a CON high position is set to 0;
……
57: until CON lowest order is set to 1, all the other positions remain unchanged;
58: judge whether count value > reference value, be, CON lowest order is set to 1; Otherwise CON lowest order is set to 0;
59: calibration terminates to produce look-at-me INT to control circuit.
Fig. 6 illustrates clock recovery circuit device course of work flow process of the present invention, comprises the steps:
60: after device powers on, carry out calibration process, meet accuracy requirement until clock signal be calibrated to;
According to the regulation of USB2.0 agreement, main process equipment is after new USB device access being detected, and first reset this USB device, and now this USB device has the address 0 of acquiescence.USB full-speed device can the SOF packet that sends of Receiving Host or router.The clock signal that the present invention can meet application and require by using front several SOF packet to obtain, this is called the calibration process that powers on.
Above-mentioned steps is exactly once the complete calibration operation that powers on.
61,62: once and again carry out Real-Time Monitoring clock signal process, until monitor clock signal not meet accuracy requirement;
Oscillator obtains the local clock pulses meeting accuracy requirement after the calibration process that powers on.
But along with the continuous work of oscillator, the oscillation frequency that the change of surrounding environment can cause the frequency departure of oscillator original, thus cause the frequency of oscillator to produce larger error, in order to prevent oscillator frequency from departing from accuracy rating required for decoded data stream signal for a long time, invention increases the process to oscillator frequency Real-Time Monitoring.
In the process of Real-Time Monitoring oscillator frequency, counter works under the control of detection signal DET.Counter is counting clock pulse between adjacent SOF packet, and compares with the reference value that this locality is preserved; If compare the scope of difference beyond regulation, then produce look-at-me, control circuit (CPU) starts the clock alignment in the course of work according to this look-at-me.
63: calibrate in the course of work, meet accuracy requirement until clock signal be calibrated to.
64: after course of work calibration terminates, continue to monitor clock signal.
Course of work alignment and upper electric calibration similar, be also through calibration process mentioned above.Its adjustment figure place can set, and opening and closing are controlled by CPU equally.
The present invention produces the low clock signal of initial precision comparison by the simple sheet internal oscillator of use one, control circuit adjusts the parameter of oscillator by turn according to the temporal information that data stream packets contains, thus makes the frequency of local clock and precision reach accuracy requirement required for decoded data stream.
The present invention detects accurate timing information from traffic spike, and repeatedly adjusts within the time interval that timing information is determined, thus realizes calibration fast.
The present invention is applicable to USB Full-Speed mode.SOF packet in usb data stream carries timing information, and the time interval between two adjacent SOF packets is strictly defined as 1ms ± 500ns, the precision of namely ± 0.05%.According to the design, counter within a certain period of time (such as 1/Nms) counts local clock pulse, and compares with corresponding reference value, thus realizes the calibration of local clock pulses.The precision of oscillator clock signal can be calibrated to ± 0.25% within.
Although the embodiment disclosed by the present invention is as above, the embodiment that described content just adopts for the ease of understanding the present invention, and be not used to limit the present invention.Technician in any the technical field of the invention; under the prerequisite not departing from the spirit and scope disclosed by the present invention; any amendment and change can be done what implement in form and in details; but scope of patent protection of the present invention, the scope that still must define with appending claims is as the criterion.
Claims (12)
1. a clock recovery circuit device, comprises the data prediction circuit, clock recovery circuitry and the control circuit that connect successively, it is characterized in that:
Data prediction circuit, for the traffic spike received being converted to the digital signal of standard, and exports to clock recovery circuitry;
Clock recovery circuitry, for passing through oscillator clocking, from the digital signal of described standard, obtain frequency information, obtain control signal by the difference of the actual frequency obtained and target frequency, according to this control signal clock signal is calibrated in the accuracy rating met the demands;
Control circuit, for opening and closing the calibration process of clock recovery circuitry, and configurable clock generator recovers corresponding parameter;
Wherein, described clock recovery circuitry comprises the testing circuit, calibration pulse generative circuit, counter circuit, calibration circuit and the Parameter adjustable pierce circuit that connect successively;
Described counter circuit, for counting described clock signal under the Time-sharing control of two calibration pulse signals, and exports to described calibration circuit by count value;
Described calibration circuit, under the control of described control circuit according to the difference of the reference value of described count value and local maintenance, export to described Parameter adjustable pierce circuit the control signal that data width is M position, described M is positive integer;
Exporting data width at described calibration circuit to described Parameter adjustable pierce circuit is in the process of the control signal of M position, described calibration circuit is L by described control circuit setup control signal adjustment figure place, described L≤M, is first set to 0 entirely by the L position of described control signal; According to L position successively more described count value and the described reference value of described control signal, if described count value is greater than described reference value, then successively the corresponding positions of the control signal of L position is adjusted to 1; If described count value is less than or equal to described reference value, then successively the corresponding positions of the control signal of described L position is adjusted to 0; Until the lowest order of described L position has adjusted, produce look-at-me to described control circuit, the control signal of M position has been exported to described Parameter adjustable pierce circuit simultaneously.
2., according to device according to claim 1, it is characterized in that,
Described testing circuit, connects described Parameter adjustable pierce circuit, for producing detection signal according to the temporal information detected, and exports to described calibration pulse generative circuit;
Described calibration pulse generative circuit, for producing multiple calibration pulse signal according to described detection signal, with the opening and closing of counter circuit described in Time-sharing control;
Described Parameter adjustable pierce circuit, for being produced described clock signal by oscillator and exporting to described testing circuit and described counter circuit respectively, calibrates the frequency of clock signal by turn according to the control signal of described M position;
The parameter of described control circuit configuration comprises the reference value of counter circuit and the figure place of control signal participation calibration.
3. according to device according to claim 2, it is characterized in that, described testing circuit is also connected with described counter circuit, wherein:
Described testing circuit utilizes synchronization signal detection to produce described detection signal after last bit of Packet Identifier, while exporting to described calibration pulse generative circuit, also exports to described counter circuit;
Described counter circuit counts described clock signal in course of normal operation under the control of two detection signals, and count value is exported to calibration circuit, determine whether clock signal is calibrated by this calibration circuit according to the difference of the parameter value of this count value and local maintenance.
4. according to device according to claim 3, it is characterized in that, described testing circuit comprises data recovery circuit and detection signal statement circuit, wherein:
Described data prediction circuit is connected with data recovery circuit, the differential signal of a pair usb data received is converted to the reverse non-return-to-zero signal of standard, and exports to data recovery circuit;
Data recovery circuit, is connected with described Parameter adjustable pierce circuit, for decoding to the reverse non-return-to-zero signal of described standard according to described clock signal, and the numeric string of generation is sent to detection signal statement circuit;
Detection signal statement circuit, produces circuit with described calibration pulse and is connected, for each generation detection signal of the digital signal that transmits according to described data recovery circuit, and exports to described calibration pulse generation circuit or described counter circuit;
Described counter circuit is opened and is counted described clock signal after receiving first calibration pulse signal or first detection signal, after receiving next calibration pulse signal or next detection signal, close the counting to described clock signal, export count value between adjacent calibration pulse signal or adjacent detection signal to described calibration circuit;
Described Parameter adjustable oscillator according to the frequency of the control signal of described M position alignment oscillator clock signal by turn, that is: f
cLOCK=k
0* f+k
1* f+ ... + k
i* f+ ... + k
m-1* f, described f are the frequency signal of oscillator reference, described k
i=0 or 1, i be positive integer, i≤M-1.
5. according to the device described in any one of Claims 1-4, it is characterized in that, also comprise the functional circuit of the clock signal used through described Parameter adjustable pierce circuit calibration, realizing corresponding application function for using the described clock signal through calibration.
6. a clock recovery method, be applied to clock recovery circuit device as claimed in claim 1, the method comprises:
Clock recovery circuitry is by internal oscillator clocking, frequency information is obtained in the digital signal of the standard received according to data prediction circuit and change, obtain control signal by the difference of the actual frequency obtained and target frequency, according to this control signal described clock signal is calibrated in the accuracy rating met the demands; Specifically also comprise:
Described clock recovery circuitry produces detection signal by testing circuit according to the temporal information detected; Multiple calibration pulse signal is produced according to described detection signal by calibration pulse generative circuit; By counter circuit in a calibration process under the Time-sharing control of two calibration pulse signals, described clock signal is counted; By the difference of calibration circuit according to the count value of counter circuit and the reference value of local maintenance, export the control signal that data width is M position, described M is positive integer; Calibrated the frequency of clock signal by turn according to the control signal of described M position by Parameter adjustable pierce circuit;
Described calibration circuit, according to the difference of the count value of counter circuit and the reference value of local maintenance, exports the control signal that data width is M position, specifically comprises:
Described calibration circuit is L by described control circuit setup control signal adjustment figure place, and described L≤M, is first set to 0 entirely by the L position of described control signal; According to L position successively more described count value and the described reference value of described control signal, if described count value is greater than described reference value, then successively the corresponding positions of the control signal of L position is adjusted to 1; If described count value is less than or equal to described reference value, then successively the corresponding positions of the control signal of described L position is adjusted to 0; Until the lowest order of described L position has adjusted, produce look-at-me to described control circuit, the control signal of M position has been exported to described Parameter adjustable pierce circuit simultaneously.
7. in accordance with the method for claim 6, it is characterized in that, also comprised before described method performs:
After clock recovery circuit device electrification reset, described clock recovery circuitry opened by described control circuit, configures corresponding parameter simultaneously.
8. in accordance with the method for claim 6, it is characterized in that, frequency information is obtained in the digital signal of the standard that described clock recovery circuitry receives according to data prediction circuit and changes, control signal is obtained by the difference of the actual frequency obtained and target frequency, clock signal is calibrated in the accuracy rating met the demands according to this control signal, specifically also comprises:
Described differential signal is converted to the reverse non-return-to-zero signal with usb data numerical coding form of standard, and exports to described clock recovery circuitry after receiving the differential signal of two-way usb data by described data prediction circuit.
9. in accordance with the method for claim 6, it is characterized in that, described testing circuit produces detection signal according to the temporal information detected, specifically comprises:
Described testing circuit utilizes synchronization signal detection to produce detection signal after last bit of Packet Identifier, exports as the mark detecting start frame packet.
10. according to the method described in claim 6 or 8, it is characterized in that, also comprise:
Counter circuit counts described clock signal in course of normal operation under the Time-sharing control of two detection signals, and count value is exported to described calibration circuit, by the difference of this calibration circuit according to the reference value of this count value and local maintenance, determine the calibration process whether entered clock signal.
11. in accordance with the method for claim 10, it is characterized in that, described counter circuit, under the Time-sharing control of two calibration pulse signals or two detection signals, counts described clock signal, specifically comprises:
The counting to described clock signal opened by described counter circuit after receiving first calibration pulse signal or first detection signal, after receiving next calibration pulse signal or next detection signal, close the counting to described clock signal, and export the count value between adjacent calibration pulse signal or adjacent detection signal.
12. in accordance with the method for claim 6, it is characterized in that, described Parameter adjustable pierce circuit calibrates the frequency of clock signal by turn according to the control signal of described M position, specifically comprises:
Described Parameter adjustable oscillator according to the frequency of the control signal of described M position alignment oscillator clock signal by turn, that is: f
cLOCK=k
0* f+k
1* f+ ... + k
i* f+ ... + k
m-1* f, described f are the frequency signal of oscillator reference, described k
i=0 or 1, i be positive integer, i≤M-1.
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| CN103336754B (en) * | 2013-05-31 | 2016-03-09 | 杭州晟元数据安全技术股份有限公司 | A kind of USB is from the system clock automated calibration system of equipment and method |
| CN105337591B (en) * | 2014-05-26 | 2017-12-22 | 无锡华润矽科微电子有限公司 | The circuit structure and method of clock recovery are realized based on USB device |
| US10890939B2 (en) * | 2017-04-24 | 2021-01-12 | Cirrus Logic, Inc. | Recovery of reference clock on a device |
| CN108614795B (en) * | 2018-04-12 | 2020-06-26 | 深圳市汇春科技股份有限公司 | Digital implementation method for USB data transmission |
| CN109687867B (en) * | 2018-11-30 | 2023-04-07 | 珠海慧联科技有限公司 | Clock calibration method and calibration circuit for crystal-oscillator-free USB (universal serial bus) equipment |
| CN112514255B (en) * | 2019-05-31 | 2024-03-19 | 京东方科技集团股份有限公司 | Signal frequency adjustment method and device, display device and storage medium |
| WO2021134783A1 (en) * | 2020-01-03 | 2021-07-08 | 深圳市汇顶科技股份有限公司 | Crystal calibration method, chip and bluetooth earphone |
| CN111665431B (en) * | 2020-04-26 | 2023-07-25 | 江西联智集成电路有限公司 | Method, device, equipment and medium for calibrating clock source in chip |
| CN113552920B (en) * | 2021-08-03 | 2023-05-09 | 中科芯集成电路有限公司 | Clock recovery system circuit |
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