CN102571080A

CN102571080A - clock recovery method and circuit supporting dynamic calibration

Info

Publication number: CN102571080A
Application number: CN2010106222500A
Authority: CN
Inventors: 高慧
Original assignee: Beijing CEC Huada Electronic Design Co Ltd
Current assignee: Beijing CEC Huada Electronic Design Co Ltd
Priority date: 2010-12-27
Filing date: 2010-12-27
Publication date: 2012-07-11

Abstract

The invention discloses a clock recovery method and circuit supporting dynamic calibration. The circuit mainly comprises a numerically controlled oscillator (DCO) and a control logic (core). The control logic is used for extracting a frequency error between a data signal of a USB (universal serial bus) and an output of the DCO, calculating the controlled quantity of the DCO by using a control algorithm, and outputs the controlled quantity to the DCO; and a DCO module adjusts the clock frequency according to controlled quantity information inputted by the core, so that an output clock frequency is close to a target frequency. A time reference used by the clock recovery circuit is completely from the data signal of the USB, after the clock recovery circuit is electrified, the DCO firstly carries out timing by using a time interval of SOF (start of frame) packets on the USB so as to complete the electrified initial calibration; after the initial calibration is completed, the DCO continues to carry out timing by using the time interval of the SOF packets in data packet transmission on the USB, and continually carries out dynamic calibration on the clock frequency of the DCO, thereby solving the problem that the constant changes of working environments including temperature and power supply voltage in the process of working affect the stability of the clock frequency. Through the structure above, a high-frequency-accuracy clock can be output and dynamic calibration is carried out continuously to keep the clock frequency under the condition of no crystal oscillator; therefore, the method and circuit disclosed by the invention can be applied to the clock recovery in the field of USB 2.0 Full Speed communication.

Description

A kind of clock recovery method and circuit of supporting dynamic calibration

Technical field:

The present invention relates to a kind of clock recovery circuitry and its implementation that is used for usb communication; It is a kind of circuit that adopts the usb data signal to carry out clock recovery; Be implemented under the condition of non-crystal oscillator; The clock of output high freuqency accuracy also keeps clock frequency, is used for the recovery of USB 2.0Full Speed communication field clock.

Background technology:

In the USB communication field, need frequency accurately clock carry out the reception and the transmission of data, usually high accuracy clock is produced by crystal oscillator.Can not external crystal oscillator or, just need to adopt clock recovery circuitry that the high accuracy clock signal is provided through removing crystal oscillator to practice thrift under the condition of cost.

Clock recovery scheme commonly used carries out primary calibration powering on; After this no longer calibrate in the course of work; The shortcoming of this type of scheme is to suppress in the course of work; Because the output clock frequency that variations such as oscillator operating voltage, working temperature cause on the sheet departs from calibration value, and the communication that causes thus makes mistakes.

The present invention proposes a kind of clock recovery method and circuit of supporting dynamic calibration; Can be from usb data recovered clock, and in communication process, utilize usb data to continue clock is calibrated, make clock output remain at the target frequency of calibration; Solved that operational environment constantly changes in the course of work; Like temperature, supply voltage etc., influence the problem of clock frequency stability, can be applied in the USB transceiver.

Summary of the invention:

The present invention proposes a kind of clock recovery circuitry structure of supporting dynamic calibration, solved under the situation of no crystal oscillator, utilize data to continue calibration, guarantee the problem of clock accuracy in the communication process.

This clock recovery circuitry mainly is made up of numerically-controlled oscillator (DCO) and control logic (core), and the entire circuit structure is as shown in Figure 1.

Use down at USB, the frequency error between control logic core module is exported reference source (usb bus data-signal) and DCO extracts, and exports to DCO through the controlled quentity controlled variable that control algolithm calculates DCO.The DCO module is according to the controlled quentity controlled variable information of core input, and the frequency of adjustment clock makes the output clock frequency near target frequency.Finally,, make the clock frequency of DCO output and the deviation of target frequency reach in the scope of permission, realized the calibration of clock frequency through repeatedly calibrating computing.The back DCO that powers at first utilizes the time interval of the SOF bag on the usb bus to carry out timing, accomplishes the first calibration that powers on; After accomplishing first calibration; The SOF bag time interval on the sustainable utilization usb bus between the data packet transmission is carried out timing; The DCO clock frequency is constantly carried out dynamic calibration, to reduce the influence of environmental changes such as outer power voltage, working temperature to CRC output clock frequency.

The regulation SOF packet time interval is that (1ms ± 500ns), promptly the precision of this time benchmark is ± 0.05% to fixed value in the usb protocol.Therefore utilize the SOF bag on the usb bus to carry out timing; In timing, the clock of inner DCO output is counted; The count results of count results and target frequency clock is compared, can judge that the frequency and the target frequency of DCO output clock is in a ratio of high or low.According to judged result the frequency of DCO is regulated, make its clock frequency remain at target frequency.The precision that DCO calibration reaches depends between the count block of satisfying required precision of calibration algorithm setting and the step-length of DCO regulating frequency.

Description of drawings:

Fig. 1 CRC system block diagram

Fig. 2 calibrating principle sketch map

Fig. 3 CRC workflow diagram

Embodiment:

For acquisition time information from usb data, whether the bag that control logic needs to transmit on the judgment data line exactly is the SOF bag, and then the adjacent SOF bag time interval is carried out timing.The SOF packet structure as shown in Figure 2, wherein SYNC part (8bit) is the part that all packets all comprise, the PID part (8bit) of SOF packet is specific coding.FrameNumber is the frame number of 11bit, and this sequence number increases progressively, and according to the difference of concrete sequence number value, may insert filler.CRC5 is the CRC5 check value (CRC5 represents CRC here) of Frame Number.

For timing is carried out at the interval between the SOF bag, must detect the SOF bag.Detection method is following, resolves SYNC and PID part, as long as SYNC partly satisfies the usb protocol requirement, PID satisfies SOF bag PID definition, then thinks the SOF bag.

In application process, can be set to electric calibration and two kinds of patterns of dynamic calibration by the CRC circuit, under the calibration mode that powers on, after the wait usb bus is accomplished and resetted; Enable the CRC module; Make electric calibration on it, reach the clock accuracy of expection after, can lock calibration result; Under the dynamic calibration pattern; The result to last electric calibration does not lock, and continues clock accuracy is judged, in case clock accuracy deflects away from the accuracy rating of setting; Then the DCO frequency is calibrated, make the DCO precision remain at the accuracy rating of expection by control logic.

The implementation method of DCO is a lot, can adopt the oscillator based on the RC vibration, and RC product decision frequency of oscillation is adjusted the electric capacity or the resistance of place in circuit by digital control position, to change frequency of oscillation; Also can adopt ring oscillator, its frequency of oscillation is relevant with current source, by digital control position the size of current source is adjusted, to change frequency of oscillation.

Through a kind of clock recovery circuitry of supporting dynamic calibration disclosed by the invention, can realize clock recovery and lasting dynamic calibration in the USB 2.0Full Speed communication system.

Should be understood that present embodiment only supplies to explain the present invention's usefulness, but not limitation of the present invention.The technical staff in relevant technologies field under the situation that does not break away from the spirit and scope of the present invention, can also make various conversion or variation, so all technical schemes that are equal to also should belong to category of the present invention and limited each claim.

Claims

1. clock recovery circuitry of supporting dynamic calibration; This clock recovery circuitry mainly is made up of numerically-controlled oscillator DCO and control logic core; It is characterized in that control logic core extracts the frequency error between usb bus data-signal and the DCO output, and export to DCO through the controlled quentity controlled variable that control algolithm calculates DCO, DCO is according to the controlled quentity controlled variable information of core input; The frequency of adjustment clock makes the output clock frequency near target frequency.

2. a kind of clock recovery circuitry of supporting dynamic calibration as claimed in claim 1; It is characterized in that numerically-controlled oscillator can adopt a kind of oscillator based on the RC vibration to realize; RC product decision frequency of oscillation; By digital control position the electric capacity or the resistance of place in circuit are adjusted, to change frequency of oscillation; Also can adopt a kind of ring oscillator, its frequency of oscillation is relevant with current source, by digital control position the size of current source is adjusted, to change frequency of oscillation.

3. a kind of clock recovery circuitry of supporting dynamic calibration as claimed in claim 1, the back DCO that it is characterized in that powering at first utilizes the time interval of the SOF bag on the usb bus to carry out timing, accomplishes the first calibration that powers on; After accomplishing first calibration, the SOF bag time interval on the sustainable utilization usb bus between the data packet transmission is carried out timing, and the DCO clock frequency is constantly carried out dynamic calibration.

4. clock recovery method of supporting dynamic calibration; Be applied in the described circuit of claim 1; It is characterized in that this method at first utilizes the time interval of the SOF packet on the usb bus to carry out timing after powering on, accomplish calibration for the first time, the SOF packet time interval between the data packet transmission is carried out timing on the sustainable utilization usb bus then; In timing, the output clock is counted; The count results of count results and calibration frequency clock is compared, judge the frequency of output clock and the height of calibration frequency, the frequency of output clock is regulated according to judged result; The output clock frequency is constantly carried out dynamic calibration, make the output clock frequency remain at calibration frequency.

5. a kind of clock recovery method of supporting dynamic standard as claimed in claim 4; Said SOF packet comprises SYNC part, PID part, Frame Number part, CRC5 part; It is characterized in that after powering on, at first utilizing the time interval of the SOF packet on the usb bus to carry out before the timing; The SOF packet is detected, and detection method is for resolving SYNC part and PID part, as long as SYNC partly satisfies the usb protocol requirement; PID satisfies SOF bag PID definition, then thinks the SOF packet.