CN212276404U

CN212276404U - Filtering unit, clock data recovery circuit and USB clock data recovery circuit

Info

Publication number: CN212276404U
Application number: CN201921338553.2U
Authority: CN
Inventors: 凌德坤; 唐振中; 郑思; 陈相政
Original assignee: Zhuhai Taixin Semiconductor Co ltd
Current assignee: Zhuhai Taixin Semiconductor Co ltd
Priority date: 2019-07-22
Filing date: 2019-08-16
Publication date: 2021-01-01
Anticipated expiration: 2029-08-16
Also published as: CN110489372B; CN110489372A

Abstract

The utility model discloses a filtering unit, a clock data recovery circuit and a USB clock data recovery circuit, wherein the filtering unit comprises a filtering circuit; the filter circuit includes eight filters, jth₁Each filter comprises a filter setting signal generating circuit, a filter reset signal generating circuit and a three-out-of-one selecting unit, j₁0, 1, 2 … 7; forming twenty-four bit data by using adjacent triple-beat eight-bit data; the filter set signal generation circuit receives DATA _ ALL _ i₁[j₁+5]To DATA _ ALL _ i₁[j₁+11]Outputting a filtering setting signal; the filter reset signal generation circuit receives DATA _ ALL _ i₁[j₁+5]To DATA _ ALL _ i₁[j₁+11]Outputting a filtering reset signal; three DATA input ends of the one-out-of-three selection unit respectively receive DATA _ i₁[j₁]1 and0, two control signal input ends respectively receiving the filtering set signal and the filtering reset signal, and a DATA output end outputting DATA _ i₁[j₁]The result of the filtering of (1).

Description

Filtering unit, clock data recovery circuit and USB clock data recovery circuit

Technical Field

The utility model relates to an integrated circuit makes technical field, especially relates to a filtering unit, clock data recovery circuit and USB clock data recovery circuit.

Background

In a general communication link, a clock data recovery circuit based on a serial data stream mainly adopts two technologies, one is a phase-locked loop, and the other is oversampling. Generally, oversampling is mainly used for low-speed communication, such as inter-computer or peripheral communication, while pll is used in the field of telecommunications, partly because pll helps to eliminate clock jitter, while oversampling not only cannot reduce jitter, but also adds self-generated jitter to the data bit stream. However, the clock data recovery circuit based on the oversampling technology is a low-cost digital technology which is easy to design and convenient for single chip integration by using a standard CMOS process, and more importantly, can satisfy the fast synchronization required by some receiving modules. In recent years, the transmission rate of computer peripherals has been greatly increased, for example, USB2.0 has reached 480Mbps, but oversampling technology has proven to be still applicable to such transmission rates.

The patent of invention with the publication number CN101202615B discloses a surge filter and a clock data recovery circuit having the same, wherein the surge filter includes: a first logic circuit for receiving the oversampled latched data and the filtered data, detecting whether data corresponding to adjacent three clock phases meet (0, 1, 0) or (1, 0, 1) combination, and if so, generating a data detection signal; the second logic circuit is used for receiving the data detection signal sent by the first logic circuit and the data jump signal fed back by the clock data recovery circuit, and judging whether surge exists in the data corresponding to the adjacent three clock phases or not based on the two signals; and the third logic circuit generates corresponding filtering data according to the judgment result of the second logic circuit and feeds the filtering data back to the first logic circuit.

Although the above patent can filter the glitch occupying one clock phase in the oversampled latched data, the following problems still exist: (1) a single glitch occupying two clock phases cannot be filtered out; (2) only a single surge can be filtered, and two continuous surges cannot be filtered; (3) when the glitches near the edges of the jumps are filtered out, the level is abnormally widened or narrowed.

SUMMERY OF THE UTILITY MODEL

The utility model discloses a first purpose aims at realizing a filtering unit, and the while filtering occupies the single sudden strain of a clock phase place and occupies the single sudden strain of two clock phase places, reduces data transmission's dislocation rate.

The utility model discloses a first purpose is realized by following technical scheme:

a filtering unit includes a filtering circuit; the filter circuit receives the eight-bit serial data, judges whether or not adjacent three-bit data in the eight-bit serial data corresponds to (1, 0, 1) or (0, 1, 0) combination, whether or not adjacent six-bit data corresponds to (1, 1, 0, 0, 1, 1) or (0, 0, 1, 0, 0) combination, outputs 1 as a filter result of the second-bit data in the (1, 0, 1) combination if the adjacent three-bit data corresponds to the (1, 0, 1) combination, outputs 0 as a filter result of the second-bit data in the (0, 1, 0) combination if the adjacent three-bit data corresponds to the (0, 1, 0, 0, 1, 1) combination, outputs 1 as a filter result of the second-bit data and the third-bit data in the (1, 1, 0, 0, 1, 1, 1) combination if the adjacent six-bit data corresponds to the (1, 1, 0, 0, 1, 1) combination, if the adjacent six bits of data match the (0, 0, 1, 1, 0, 0) combination, 0 is output as the filtering result of the second bit of data and the third bit of data in the (0, 0, 1, 1, 0, 0) combination, otherwise, the input data is output as the filtering result.

Further, the eight-bit serial DATA includes … … DATA _ N-1[ 7: 0]、DATA_N[7：0]、 DATA_N+1[7：0]……，DATA_i₁[7：0]Including DATA _ i₁[0]、DATA_i₁[1]……DATA_i₁[7]， i₁… … N-1, N, N +1 … …; the filter circuit includes eight filters, jth₁A filter for determining DATA _ i₁[j₁]Whether or not its previous bit DATA and next bit DATA match (1, 0, 1) or (0, 1, 0) combination and DATA _ i₁[j₁]Whether or not its first two-bit DATA and last three-bit DATA match (1, 1, 0, 0, 1, 1) or (0, 0, 1, 1, 0, 0) combination and DATA _ i₁[j₁]With whether its first three bits data and last two bits data match (1, 1, 0, 0, 1, 1) or (0, 0, 1, 1, 0, 0) combination,

j

₁0, 1, 2, 3, 4, 5, 6, 7 if DATA _ i₁[j₁]In (1, 0, 1) combination with its previous and next DATA bits or DATA _ i₁[j₁]In combination with its first two bits DATA and last three bits DATA (1, 1, 0, 0, 1, 1) or DATA _ i₁[j₁]Combined with its first three bits of data and last two bits of data corresponding to (1, 1, 0, 0, 1, 1), j₁The filters have 1 as DATA _ i₁[j₁]If DATA _ i is outputted₁[j₁]In (0, 1, 0) combination with its previous and next bits of DATA or DATA _ i₁[j₁]In (0, 0, 1, 1, 0, 0) combination with its first two bits DATA and last three bits DATA or DATA _ i₁[j₁]Combined with its first three bits of data and last two bits of data corresponding to (0, 0, 1, 1, 0, 0), j₁The filters take 0 as DATA _ i₁[j₁]Otherwise, j (th)₁A filter for filtering DATA _ i₁[j₁]As DATA _ i₁[j₁]And outputting the filtering result.

As a specific embodiment, the j-th₁Each filter comprises a filtering set signal generating circuit, a filtering reset signal generating circuit and a one-out-of-three selecting unit; the DATA _ i₁-1[7：0]、DATA_i₁[7：0]、 DATA_i₁+1[7：0]Constitute twenty-four bit DATA _ ALL _ i₁[23：0]，DATA_ALL_i₁[23：0]Including DATA _ ALL _ i₁[0]、DATA_ALL_i₁[1]……DATA_ALL _i₁[23](ii) a The filter set signal generation circuit receives DATA _ ALL _ i₁[j₁+5]、DATA_ALL_i₁[j₁+6] 、DATA_ALL_i₁[j₁+7]、DATA_ALL_i₁[j₁+8]、DATA_ALL_i₁[j₁+9]、DATA_ALL_i₁[j₁+10]And DATA _ ALL _ i₁[j₁+11]Determine DATA _ ALL _ i₁[j₁+7]、DATA_ALL_i₁[j₁+8]、DATA_ALL_ i₁[j₁+9]Whether or not the combination of (1, 0, 1) is satisfied, and whether or not the DATA _ ALL _ i is satisfied is judged₁[j₁+6]、DATA_ALL_i₁[j₁+7]、 DATA_ALL_i₁[j₁+8]、DATA_ALL_i₁[j₁+9]、DATA_ALL_i₁[j₁+10]、DATA_ALL_i₁[j₁+11]Whether or not the DATA _ ALL _ i matches the (1, 1, 0, 0, 1, 1) combination is determined₁[j₁+5]、DATA_ALL_i₁[j₁+6]、 DATA_ALL_i₁[j₁+7]、DATA_ALL_i₁[j₁+8]、DATA_ALL_i₁[j₁+9]、DATA_ALL_i₁[j₁+10]Whether the combination meets the (1, 1, 0, 0, 1, 1) or not, and outputting a filtering setting signal;

the filter reset signal generation circuit receives DATA _ ALL _ i₁[j₁+5]、DATA_ALL_i₁[j₁+6]、 DATA_ALL_i₁[j₁+7]、DATA_ALL_i₁[j₁+8]、DATA_ALL_i₁[j₁+9]、DATA_ALL_i₁[j₁+10]And DATA _ ALL _ i₁[j₁+11]Determine DATA _ ALL _ i₁[j₁+7]、DATA_ALL_i₁[j₁+8]、DATA_ALL_ i₁[j₁+9]Whether or not the combination of (0, 1, 0) is satisfied, and whether or not the DATA _ ALL _ i is satisfied is judged₁[j₁+6]、DATA_ALL_i₁[j₁+7]、 DATA_ALL_i₁[j₁+8]、DATA_ALL_i₁[j₁+9]、DATA_ALL_i₁[j₁+10]、DATA_ALL_i₁[j₁+11]Whether or not the DATA _ ALL _ i matches the (0, 0, 1, 1, 0, 0) combination is determined₁[j₁+5]、DATA_ALL_i₁[j₁+6]、 DATA_ALL_i₁[j₁+7]、DATA_ALL_i₁[j₁+8]、DATA_ALL_i₁[j₁+9]、DATA_ALL_i₁[j₁+10]Whether the combination of (0, 0, 1, 1, 0, 0) is met or not, and outputting a filtering reset signal;

three DATA input ends of the one-out-of-three selection unit respectively receive DATA _ i₁[j₁]1 and0, two control signal input ends respectively receiving the filtering set signal and the filtering reset signal, and a DATA output end outputting DATA _ i₁[j₁]The filtering result of (1); the one-out-of-three selection unit selects DATA _ i under the control of the filtering set signal and the filtering reset signal₁[j₁]One of, 1 and0 as DATA _ i₁[j₁]Outputting the filtering result; when the DATA _ ALL _ i₁[j₁+8]When the DATA is the second bit DATA of the combination of (1, 0, 1), or the second bit DATA or the third bit DATA of (1, 1, 0, 0, 1, 1), the filter set signal and the filter reset signal control the one-out-of-three selection unit to select 1 as DATA _ i₁[j₁]When the DATA _ ALL _ i is output₁[j₁+8]Is the second bit DATA of the (0, 1, 0) combination, or the second bit DATA or the third bit DATA of the (0, 0, 1, 1, 0, 0), the filter set signal and the filter reset signal control the one-out-of-three selection unit to select 0 as DATA _ i₁[j₁]Otherwise, the filtering set signal and the filtering reset signal control the one-out-of-three selection unit to select DATA _ i₁[j₁]As DATA _ i₁[j₁]And outputting the filtering result.

Further, when the DATA _ ALL _ i is changed₁[j₁+8]When the data is the second bit data of the combination of (1, 0, 1), or the second bit data or the third bit data of (1, 1, 0, 0, 1, 1), the filtering set signal is 1, otherwise, the filtering set signal is 0; when the DATA _ ALL _ i₁[j₁+8]When the data is the second bit data of the (0, 1, 0) combination, or the second bit data or the third bit data of the (0, 0, 1, 1, 0, 0), the filtering reset signal is 1, otherwise, the filtering reset signal is 0.

As a specific implementation manner, the filtering set signal generating circuit includes a first and gate, a second and gate, a third and gate, a first not gate, a second not gate, a third not gate, a fourth not gate, a fifth not gate, and a first or gate; two input ends of the first AND gate respectively receive DATA _ ALL _ i₁[j₁+7]、 DATA_ALL_i₁[j₁+9]The other input terminal of the first NOT gate is connected to the output terminal of the first NOT gate, and the input terminal of the first NOT gate receives DATA _ ALL _ i₁[j₁+9](ii) a Four input ends of the second AND gate respectively receive DATA _ ALL _ i₁[j₁+6]、DATA_ALL_i₁[j₁+7]、DATA_ALL_i₁[j₁+10]And DATA _ ALL _ i₁[j₁+11]The other two input terminals are respectively connected with the output terminal of the second NOT gate and the output terminal of the third NOT gate, and the input terminals of the second NOT gate and the third NOT gate respectively receive DATA _ ALL _ i₁[j₁+8]、DATA_ALL_i₁[j₁+9](ii) a Four input ends of the third AND gate respectively receive DATA _ ALL _ i₁[j₁+5]、DATA_ALL_i₁[j₁+6]、DATA_ALL_i₁[j₁+9]And DATA _ ALL _ i₁[j₁ +10]The other two input terminals are respectively connected with the output terminal of the fourth NOT gate and the output terminal of the fifth NOT gate, and the input terminal of the fourth NOT gate and the input terminal of the fifth NOT gate respectively receive DATA _ ALL _ i₁[j₁+7]、 DATA_ALL_i₁[j₁+8](ii) a The first isThe output end of the AND gate, the output end of the second AND gate and the output end of the third AND gate are respectively connected with three input ends of the first OR gate, the output end of the first OR gate is connected with the first control signal input end of the one-of-three selection unit, and a filtering setting signal is output to the first control signal input end of the one-of-three selection unit.

As a specific implementation manner, the filtering reset signal generating circuit includes a fourth and gate, a fifth and gate, a sixth not gate, a seventh not gate, an eighth not gate, a ninth not gate, a tenth not gate, an eleventh not gate, a twelfth not gate, a thirteenth not gate, a fourteenth not gate, a fifteenth not gate, and a second or gate; one input terminal of the fourth AND gate receives DATA _ ALL _ i₁[j₁+8]The other two input terminals are respectively connected with the output terminal of the sixth not gate and the output terminal of the seventh not gate, and the input terminal of the sixth not gate and the input terminal of the seventh not gate respectively receive DATA _ ALL _ i₁[j₁+7]、DATA_ALL_i₁[j₁+9](ii) a Two input ends of the fifth AND gate respectively receive DATA _ ALL _ i₁[j₁+8]、DATA_ALL_i₁[i+9]The other four input terminals are respectively connected with the output terminal of the eighth not gate, the output terminal of the ninth not gate, the output terminal of the tenth not gate and the output terminal of the eleventh not gate, and the input terminal of the eighth not gate, the input terminal of the ninth not gate, the input terminal of the tenth not gate and the input terminal of the eleventh not gate respectively receive DATA _ ALL _ i₁[j₁+6]、DATA_ALL_i₁[j₁+7]、 DATA_ALL_i₁[j₁+10]And DATA _ ALL _ i₁[j₁+11](ii) a Two input ends of the sixth AND gate receive DATA _ ALL _ i₁[j₁+7]、DATA_ALL_i₁[j₁+8]The other four input terminals are respectively connected with the output terminal of the twelfth not gate, the output terminal of the thirteenth not gate, the output terminal of the fourteenth not gate and the output terminal of the fifteenth not gate, and the input terminal of the twelfth not gate, the input terminal of the thirteenth not gate, the input terminal of the fourteenth not gate and the input terminal of the fifteenth not gate respectively receive DATA _ ALL _ i₁[j₁+5]、DATA_ALL_i₁[j₁+6]、 DATA_ALL_i₁[j₁+9]And DATA _ ALL _ i₁[i+10](ii) a The output end of the fourth AND gate, the output end of the fifth AND gate and the output end of the sixth AND gate are respectively connected with three input ends of the second OR gate, the output end of the second OR gate is connected with the second control signal input end of the one-of-three selection unit, and a filtering reset signal is output to the second control signal input end of the one-of-three selection unit.

As a specific implementation manner, the three-out-of-one selection unit includes a first one-out-of-one selector and a second one-out-of-one selector;

a control signal input terminal of the first alternative selector receives the filtering setting signal, and a DATA input terminal receives the DATA _ i₁[j₁]The other DATA input end of the first alternative selector receives 1, the output end of the first alternative selector is connected with one DATA input end of the second alternative selector, the other DATA input end of the second alternative selector receives 0, the control signal input end of the first alternative selector receives a filtering reset signal, and the output end of the first alternative selector outputs DATA _ i₁[j₁]When the filtering set signal is 1, the filtering reset signal is 0, the first alternative selector selects 1 to output, and the second alternative selector selects the output result of the first alternative selector as DATA _ i₁[j₁]When the filtering reset signal is 1, the filtering set signal is 0, and the second alternative selector selects 0 as DATA _ i₁[j₁]When the filtering set signal and the filtering reset signal are both equal to 0, the first alternative selector selects DATA _ i₁[j₁]An output, the second one-of-two selector selecting the output result of the first one-of-two selector as DATA _ i₁[j₁]The result of the filtering of (2) is output,

or, the control signal input end of the first alternative selector receives a filtering reset signal, and one DATA input end of the first alternative selector receives DATA _ i₁[j₁]The other data input end receives 0, the output end is connected with one data input end of the second alternative selector, and the second alternative selector is used for selecting one of the data input endsThe other DATA input terminal of the selector receives 1, the control signal input terminal receives the filtering setting signal, and the output terminal outputs DATA _ i₁[j₁]When the filtering reset signal is 1, the filtering set signal is 0, the first alternative selector selects 0 to output, and the second alternative selector selects the output result of the first alternative selector as DATA _ i₁[j₁]When the filtering set signal is 1, the filtering reset signal is 0, and the second alternative selector selects 1 as DATA _ i₁[j₁]When the filtering reset signal and the filtering set signal are both 0, the first alternative selector selects DATA _ i₁[j₁]An output, the second one-of-two selector selecting the output result of the first one-of-two selector as DATA _ i₁[j₁]And outputting the filtering result.

Further, the filter unit includes two of the filter circuits, and a result of filtering output from a first filter circuit is first filter DATA, which is eight-bit serial DATA including … … FILT1_ DATA _ N-1[ 7: 0), FILT1_ DATA _ N [ 7: 0), FILT1_ DATA _ N +1[ 7: 0] … …, the second filter circuit receives the first filtered DATA and outputs a filtered result as second filtered DATA, the second filtered DATA being eight-bit serial DATA including … … FILT2_ DATA _ N-1[ 7: 0), FILT2_ DATA _ N [ 7: 0].

Further, the input end of the filter circuit receives three adjacent beats of eight-bit serial data; the serial DATA of three adjacent beats and eight bits simultaneously respectively output three adjacent beats and eight DATA DATA _ i₁-1[7：0]、 DATA_i₁[7：0]、DATA_i₁+1[7：0]To the filter circuit.

Further, the filter unit includes two of the filter circuits, and a result of filtering output from a first filter circuit is first filter DATA, which is eight-bit serial DATA including … … FILT1_ DATA _ N-1[ 7: 0]、FILT1_DATA_N[7：0] 、FILT1_DATA_N+1[7：0]… …, a second filtering circuit receives adjacent three beats of the first filtered data,the output filtering result is the second filtering DATA, and the adjacent three beats of the first filtering DATA simultaneously output the adjacent three beats of the eight-bit DATA FILT1_ DATA _ i₁-1[7：0]、FILT1_DATA_i₁[7：0]、FILT1_DATA_i₁+1 [7：0]To the second filter circuit, the second filtered DATA is eight-bit serial DATA including … … FILT2_ DATA _ N-1[ 7: 0]、FILT2_DATA_N[7：0]……。

The second objective of the present invention is to realize a clock data recovery circuit using the above filtering unit, wherein the filtering occupies a single burst of a clock phase and occupies a single burst of two clock phases, and the bit error rate of data transmission is reduced.

The second purpose of the utility model is realized by the following technical scheme:

a clock data recovery circuit adopting the filter unit further comprises an oversampling unit, a synchronization unit, an edge detection unit, a data selection unit and a data storage unit; the oversampling unit receives serial input DATA and an eight-phase clock, outputs oversampled DATA corresponding to the eight-phase clock, the oversampled DATA being eight-bit serial DATA, including … … SAMPLE _ DATA _ N-1[ 7: 0), SAMPLE _ DATA _ N [ 7: 0), SAMPLE _ DATA _ N +1[ 7: 0] … …; the synchronization unit receives the over-sampling DATA output by the over-sampling unit and outputs synchronization DATA after synchronization processing, wherein the synchronization DATA are eight-bit serial DATA and comprise … … SYNC _ DATA _ N-1[ 7: 0], SYNC _ DATA _ N [ 7: 0], SYNC _ DATA _ N +1[ 7: 0] … …; the filter unit receives the synchronization DATA output from the synchronization unit, and outputs filtered DATA, which is eight-bit serial DATA and includes … … FILT _ DATA _ N-1[ 7: 0), FILT _ DATA _ N [ 7: 0), FILT _ DATA _ N +1[ 7: 0] … …, the filtered data is first filtered data when the filtering unit includes one filtering circuit, and the filtered data is second filtered data when the filtering unit includes two filtering circuits; the EDGE detection unit receives the filtering DATA output by the filtering unit, judges whether two adjacent bits of DATA in the filtering DATA are equal or not, if not, outputs 1 as the EDGE detection result of the next bit of DATA, otherwise, outputs 0 as the EDGE detection result of the next bit of DATA, the EDGE detection results of all the bits of filtering DATA form EDGE detection DATA, and the EDGE detection DATA are eight-bit serial DATA and comprise … … EDGE _ DATA _ N-1[ 7: 0), EDGE _ DATA _ N [ 7: 0), EDGE _ DATA _ N +1[ 7: 0] … …; the data selection unit receives the filtering data output by the filtering unit and the edge detection data output by the edge detection unit, samples are carried out at four phase clocks before the jump edge of the filtering data, and eight phase clocks after the last sampling point are selected for sampling when a new jump edge is not detected at twelve phase clocks after the jump edge; the data storage unit is used for outputting the valid data sampled by the data selection unit.

Furthermore, the data selection unit comprises a high-order sampling circuit, a low-order sampling circuit, a high-order sampling effective identifier generation circuit and a low-order sampling effective identifier generation circuit; the high-order sampling circuit receives the filtering data and the low-order four-digit data of the edge detection data, carries out high-order sampling on the filtering data according to the low-order four-digit data of the edge detection data and outputs high-order sampling data; the low-order sampling circuit receives filtering data and high-order four-digit data of edge detection data, performs low-order sampling on the filtering data according to the high-order four-digit data of the edge detection data, and outputs low-order sampling data; the high-order sampling effective identification generating circuit receives the edge detection data, judges whether the filtering data is high-order effective or not and outputs a high-order sampling effective identification; the low-order sampling effective identification generating circuit receives the edge detection data, judges whether the filtering data is low-order effective or not and outputs a low-order sampling effective identification;

if EDGE _ DATA _ i₁+1[j₂₁]Equal to 1, high sampling circuit selects FILT _ DATA _ i₁[j_21m+4]As FILT _ DATA _ i₁[7：0]Otherwise, the high-order sampling circuit is according to EDGE _ DATA _ i₁[j₂₂]Make a selection if EDGE _ DATA _ i₁[j₂₂]Equal to 1, the high sampling circuit selects FILT2_ DATA _ i₁[j_22m+4]As FILT2_ DATA _ i₁[7：0]And so on, j₂₁＝0，1，2，3，j_21mIs in accordance with EDGE _ DATA _ i₁+1[j₂₁]J equal to 1₂₁Maximum value of j₂₂＝0，1，2，3，j_22mIs in accordance with EDGE _ DATA _ i₁[j₂₂]J equal to 1₂₂Maximum value of (d);

if EDGE _ DATA _ i₁[j₃₁]Equal to 1, low sampling circuit selects FILT _ DATA _ i₁[j_31m-4]As FILT2_ DATA _ i₁[7：0]Otherwise, the lower sampling circuit is according to EDGE _ DATA _ i₁-1[j₃₂]Make a selection if EDGE _ DATA _ i₁-1[j₃₂]Equal to 1, low sampling circuit selects FILT _ DATA _ i₁[j_32m-4]As FILT2_ DATA _ i₁[7：0]And so on, j₃₁＝4，5，6，7，j_31mIs in accordance with EDGE _ DATA _ i₁[j₃₁]J equal to 1₃₁Maximum value of j₃₂＝4，5，6，7，j_32mIs in accordance with EDGE _ DATA _ i₁-1[j₃₂]J equal to 1₃₂Maximum value of (d);

if EDGE _ DATA _ i₁+1[j₂₁]Equal to 1, or, EDGE _ DATA _ i₁[j₄₁]Equal to 1, and EDGE _ DATA _ i₁[7：4]Are all equal to 0, and EDGE _ DATA _ i₁+1[j₄₁+4：0]Are all equal to 0, FILT _ DATA _ i₁[7：0]High bit valid, the high bit sampling valid flag output by the high bit sampling valid flag circuit is valid, otherwise, FILT _ DATA _ i₁[7：0]High-order invalid, the high-order sampling valid identification output by the high-order sampling valid identification circuit is invalid, j₄₁＝0，1，2，3；

If EDGE _ DATA _ i₁[j₃₁]Equal to 1, or, EDGE _ DATA _ i₁-1[j₄₂]Equal to 1, and EDGE _ DATA _ i₁[7：0]Are all equal to 0, and EDGE _ DATA _ i₁+1[j₄₂：0]Are all equal to 0, FILT _ DATA _ i₁[7：0]Low order valid, the low order sampling valid identification circuit outputsThe low sample valid flag is valid, otherwise FILT _ DATA _ i₁[7：0]The low order is invalid, the low order sampling valid identification output by the low order sampling valid identification circuit is invalid, j₄₂＝4，5，6，7；

The data storage unit receives high-order sampling data, low-order sampling data, high-order sampling effective identification and low-order sampling effective identification, and when high-order sampling effective identification is effective, low-order sampling effective identification is invalid, the high-order sampling data is stored low-order sampling data when low-order sampling effective identification is effective, high-order sampling effective identification is invalid, the high-order sampling data is stored earlier when high-order sampling effective identification is all valid with low-order sampling effective identification, and then the high-order sampling data is stored high-order sampling data when high-order sampling effective identification is all invalid with low-order sampling effective identification, the storage is abandoned high-order sampling data and low-order sampling data, data storage unit outputs a datum for storing eight bits.

Further, the high-order sampling circuit comprises a high-order sampling address generating circuit and a first one-out-of-eight selector; the low-order sampling circuit comprises a low-order sampling address generating circuit and a second one-of-eight selector; the high-order sampling address generation circuit receives EDGE _ DATA _ i₁+1[3：0]Outputting a high-order sampling address; the DATA input of the first one-of-eight selector receives FILT _ DATA _ i₁[7：0]The input end of the control signal receives a high-order sampling address output by the high-order sampling address generating circuit, and the first one-out-of-eight selector selects FILT _ DATA _ i under the control of the high-order sampling address₁[7：4]One bit of data in the data is output as high-order sampling data; the low-order sampling address generation circuit receives EDGE _ DATA _ i₁[7：4]Outputting a low-order sampling address; a DATA input of the second one-of-eight selector receives FILT _ DATA _ i₁[7：0]The input end of the control signal receives the lower sampling address output by the lower sampling address generating circuit, and the second one-out-of-eight selector selects FILT _ DATA _ i under the control of the lower sampling address₁[3：0]One bit of the data is output as low-order sampling data;

if EDGE _ DATA _ i₁+1[j₂₁]Equal to 1, high order sampling address generation circuit selects j_21m+4 as FILT _ DATA _ i₁[7：0]The control signal input terminal of the first one-of-eight selector receives j_21m+4, the first one-out-of-eight selector selects FILT2_ DATA _ i₁[j_21m+4]As FILT _ DATA _ i₁[7：0]Otherwise, the high-order sampling address generating circuit outputs the high-order sampling DATA according to EDGE _ DATA _ i₁[j₂₂]Select the high order sample address if EDGE _ DATA _ i₁[j₂₂]Equal to 1, high order sampling address generation circuit selects j_22m+4 as FILT _ DATA _ i₁[7：0]The control signal input terminal of the first one-of-eight selector receives j_22m+4, the first one-out-of-eight selector selects FILT _ DATA _ i₁[j_22m+4]Outputting, and so on;

if EDGE _ DATA _ i₁[j₃₁]Equal to 1, low order sampling circuit select j_31m-4 as FILT _ DATA _ i₁[7： 0]The control signal input terminal of the second one-of-eight selector receives j_31mAfter-4, the second one-of-eight selector selects FILT _ DATA _ i₁[j_31m-4]As FILT _ DATA _ i₁[7：0]Otherwise, the lower sampling address generating circuit outputs the lower sampling DATA according to EDGE _ DATA _ i₁-1[j₃₂]Select the lower sample address if EDGE _ DATA _ i₁-1[j₃₂]Equal to 1, low order sampling address generation circuit selects j_32m-4 as FILT _ DATA _ i₁[7：0]The control signal input terminal of the second one-of-eight selector receives j_32mAfter-4, the second one-of-eight selector selects FILT _ DATA _ i₁[j_32m-4]As FILT _ DATA _ i₁[7：0]And so on, and so on.

As a specific implementation manner, the high-order sampling address generating circuit includes a third one-of-two selector, a fourth one-of-two selector, a fifth one-of-two selector, a sixth one-of-two selector, and a third register;the control signal input end of the third alternative selector receives EDGE _ DATA _ i₁+1[0]One DATA input terminal receives FILT _ DATA _ i fed back by the third register₁-1[7：0]The other data input end of the high-order sampling address of (4) is received, and the output end of the high-order sampling address of (4) is connected with one data input end of the fourth alternative selector; the control signal input end of the fourth alternative selector receives EDGE _ DATA _ i₁+1[1]The other input end receives the signal 5, and the output end is connected with one data input end of the fifth alternative selector; a control signal input terminal of the fifth one-of-choices selector receives EDGE _ DATA _ i₁+1[2]The other data input end receives the signal 6, and the output end is connected with one data input end of the sixth alternative selector; a control signal input terminal of the sixth alternative selector receives EDGE _ DATA _ i₁+1[3]The other DATA input terminal receives 7, and the output terminal outputs FILT _ DATA _ i₁[7：0]Sample the address and sample the high order bits of FILT _ DATA _ i₁[7：0]Sends the high-order sampling address of the third register, and sends FILT _ DATA _ i to the third register₁[7：0]Is fed back to a DATA input terminal of the third alternative selector as a DATA input terminal for generating FILT _ DATA _ i₁+1[7：0]The input value of the upper sampling address;

as a specific implementation manner, the low-order sampling address generating circuit includes a seventh one-of-two selector, an eighth one-of-two selector, a ninth one-of-two selector, a twelfth one-of-two selector, and a fourth register; a control signal input terminal of the seventh alternative selector receives EDGE _ DATA _ i₁[4]One DATA input terminal receives FILT _ DATA _ i fed back from the fourth register₁-1[7：0]The other data input end of the low-order sampling address of (1) receives 0, and the output end of the low-order sampling address of (1) is connected with one data input end of the eighth alternative selector; a control signal input terminal of the eighth either-or selector receives EDGE _ DATA _ i₁[5]The other data input end receives 1, and the output end is connected with one data input end of the ninth alternative selector; a control signal input terminal of the ninth alternative selector receives EDGE _ DATA _ i₁[6]The other data input terminal receives 2, the output terminal and the twelfth terminalSelecting one data input end of a selector to be connected; the control signal terminal of the second-out-of-ten selector receives EDGE _ DATA _ i₁[7]The other DATA input terminal receives 3, and the output terminal outputs FILT _ DATA _ i₁[7：0]Sample the address and sample the low order of FILT _ DATA _ i₁[7：0]The lower sampling address of (1) is stored in a fourth register, and FILT _ DATA _ i is stored in the fourth register₁[7：0]Is fed back to a DATA input terminal of the seventh alternative selector as FILT _ DATA _ i₁+1[7：0]The lower order of the sampling address.

Further, when the FILT _ DATA _ i₁[7：0]When the high-order sampling is valid, the high-order sampling valid flag generation circuit selects 1 as FILT _ DATA _ i₁[7：0]The high bit of the sample valid flag output when the FILT _ DATA _ i₁[7：0]When the high-order sampling is invalid, the high-order sampling valid flag generation circuit selects 0 as FILT _ DATA _ i₁[7：0]The high-order sampling effective identification is output; when the FILT _ DATA _ i₁[7：0]The lower sampling valid flag generation circuit selects 1 as FILT _ DATA _ i when the lower sampling is valid₁[7：0]The low bit of the sample valid flag output when the FILT _ DATA _ i₁[7：0]When the lower sampling is invalid, the lower sampling valid flag generation circuit selects 0 as FILT _ DATA _ i₁[7：0]The low order samples of (a) effectively identify the output.

As a specific implementation manner, the high-order sampling flag generating circuit includes an eleventh second-to-first selector, a twelfth second-to-first selector, a thirteenth second-to-first selector, a fourteenth second-to-first selector, a fifteenth second-to-first selector, a sixteenth second-to-first selector, a seventeenth second-to-first selector, an eighteenth second-to-first selector, a fifth register, a first numerical comparator, a second numerical comparator, a third numerical comparator, a fourth numerical comparator, a first nor gate, a second nor gate, a third nor gate, a fourth nor gate, a fifth nor gate, a seventh and gate, an eighth and gate, a ninth and gate, a tenth and gate, an eleventh and gate, a third or gate, a fourth or gate, and a fifth or gate;

the first and second selectionA control signal input terminal of the selector receives EDGE _ DATA _ i₁-1[4]One DATA input terminal receives FILT _ DATA _ i fed back from the fifth register₁-2[7：0]The other data input end of the last sampling address of (1) receives 0, and the output end of the last sampling address of (1) is connected with one data input end of the twelfth alternative selector; a control signal input terminal of the twelfth alternative selector receives EDGE _ DATA _ i₁-1[5]The other data input end receives 1, and the output end is connected with one data input end of the thirteenth alternative selector; a control signal input terminal of the thirteenth alternative selector receives EDGE _ DATA _ i₁-1[6]The other data input end receives 2, and the output end is connected with one data input end of the fourteenth alternative selector; a control signal input terminal of the fourteenth either-or selector receives EDGE _ DATA _ i₁-1[7]The other data input end receives the signal 3, and the output end is connected with one data input end of the fifteenth alternative selector; a control signal input terminal of the fifteenth alternative selector receives EDGE _ DATA _ i₁[0]The other data input end receives 4, and the output end is connected with one data input end of the sixteenth alternative selector; a control signal input terminal of the sixteenth alternative selector receives EDGE _ DATA _ i₁[1]The other data input end receives the signal 5, and the output end is connected with one data input end of the nineteenth alternative selector; a control signal input terminal of the seventeenth alternative selector receives EDGE _ DATA _ i₁[2]The other data input end receives 6, and the output end is connected with one data input end of the eighteenth alternative selector; a control signal input terminal of the eighteenth alternative selector receives EDGE _ DATA _ i₁[3]The other DATA input terminal receives 7, and the output terminal outputs FILT _ DATA _ i₁-1[7：0]And will FILT _ DATA _ i₁-1[7：0]Is sent to the fifth register, and the fifth register sends FILT _ DATA _ i₁-1[7：0]Is fed back to a DATA input terminal of the eleventh alternative selector as a DATA _ i generator₁[7：0]The input value of the last sampling address of (1);

the first numerical comparator, the second numerical comparatorOne input end of each of the two numerical value comparators, the third numerical value comparator and the fourth numerical value comparator receives FILT _ DATA _ i₁-1[7：0]The other input receives 4, 5, 6 and 7, respectively; five input terminals of the first NOR gate respectively receive EDGE _ DATA _ i₁+1[0]、EDGE_DATA_i₁+1[1]、EDGE_DATA_i₁+1[2]、EDGE_DATA_i₁+1[3]、E DGE_DATA_i₁+1[4](ii) a Two input ends of the seventh AND gate are respectively connected with the output end of the first numerical comparator and the output end of the first NOR gate; six input terminals of the second NOR gate respectively receive EDGE _ DATA _ i₁+1[0]、EDGE_DATA_i₁+1[1]、EDGE_DATA_i₁+1[2]、EDGE_DATA_i₁+1 [3]、EDGE_DATA_i₁+1[4]、EDGE_DATA_i₁+1[5](ii) a Two input ends of the eighth AND gate are respectively connected with the output end of the second numerical comparator and the output end of the second NOR gate; seven input terminals of the third NOR gate respectively receive EDGE _ DATA _ i₁+1[0]、EDGE_DATA_i₁+1[1]、EDGE_DATA_ i₁+1[2]、EDGE_DATA_i₁+1[3]、EDGE_DATA_i₁+1[4]、EDGE_DATA_i₁+1[5]、 EDGE_DATA_i₁+1[6](ii) a Two input ends of the ninth AND gate are respectively connected with the output end of the third numerical comparator and the output end of the third NOR gate; eight input terminals of the fourth NOR gate respectively receive EDGE _ DATA _ i₁+1[0]、EDGE_DATA_i₁+1[1]、EDGE_DATA_i₁+1[2]、EDGE_DATA_ i₁+1[3]、EDGE_DATA_i₁+1[4]、EDGE_DATA_i₁+1[5]、EDGE_DATA_i₁+1[6]、 EDGE_DATA_i₁+1[7](ii) a Two input ends of the tenth AND gate are respectively connected with the output end of the fourth numerical comparator and the output end of the fourth NOR gate; the four input ends of the third or gate are respectively connected with the output end of the seventh and gate, the output end of the eighth and gate, the output end of the ninth and gate and the output end of the tenth and gate; the four input terminals of the fifth NOR gate NOR5 are respectively connected to EDGE _ DATA _ i₁[4]、EDGE_DATA_i₁[5]、 EDGE_DATA_i₁[6]、EDGE_DATA_i₁[7]Connecting; the eleventh andtwo input ends of the gate are respectively connected with the output end of the third OR gate and the output end of the fifth NOR gate; four input terminals of the fourth OR gate respectively receive EDGE _ DATA _ i₁+1[0]、EDGE_DATA_i₁+1[1]、EDGE_DATA_i₁+1[2]、EDGE_ DATA_i₁+1[3]Connecting; and two input ends of the fifth OR gate are respectively connected with the output end of the eleventh AND gate and the output end of the fourth OR gate, and the output end outputs a high-order sampling effective identifier.

As a specific implementation manner, the low-order sampling valid flag generating circuit includes an eleventh second-to-first selector, a twelfth second-to-first selector, a thirteenth second-to-first selector, a fourteenth second-to-first selector, a fifteenth second-to-first selector, a sixteenth second-to-first selector, a seventeenth second-to-first selector, an eighteenth second-to-first selector, a fifth register, a fifth numerical comparator, a sixth numerical comparator, a seventh numerical comparator, an eighth numerical comparator, a sixteenth nor gate, a sixth nor gate, a seventh nor gate, an eighth nor gate, a ninth nor gate, a twelfth and gate, a thirteenth and gate, a fourteenth and gate, a fifteenth and gate, a sixteenth and gate, a sixth or gate, a seventh or gate, and an eighth or gate;

a control signal input terminal of the eleventh alternative selector receives EDGE _ DATA _ i₁-1[4]One DATA input terminal receives FILT _ DATA _ i fed back from the fifth register₁-2[7：0]The other data input end of the last sampling address of (1) receives 0, and the output end of the last sampling address of (1) is connected with one data input end of the twelfth alternative selector; a control signal input terminal of the twelfth alternative selector receives EDGE _ DATA _ i₁-1[5]The other data input end receives 1, and the output end is connected with one data input end of the thirteenth alternative selector; a control signal input terminal of the thirteenth alternative selector receives EDGE _ DATA _ i₁-1[6]The other data input end receives 2, and the output end is connected with one data input end of the fourteenth alternative selector; a control signal input terminal of the fourteenth either-or selector receives EDGE _ DATA _ i₁-1[7]The other data input end receives 3, and the output end and one data of the fifteenth alternative selectorThe input ends are connected; a control signal input terminal of the fifteenth alternative selector receives EDGE _ DATA _ i₁[0]The other data input end receives 4, and the output end is connected with one data input end of the sixteenth alternative selector; a control signal input terminal of the sixteenth alternative selector receives EDGE _ DATA _ i₁[1]The other data input end receives the signal 5, and the output end is connected with one data input end of the nineteenth alternative selector; a control signal input terminal of the seventeenth alternative selector receives EDGE _ DATA _ i₁[2]The other data input end receives 6, and the output end is connected with one data input end of the eighteenth alternative selector; a control signal input terminal of the eighteenth alternative selector receives EDGE _ DATA _ i₁[3]The other DATA input terminal receives 7, and the output terminal outputs FILT _ DATA _ i₁-1[7：0]And will FILT _ DATA _ i₁-1[7：0]Is sent to the fifth register, and the fifth register sends FILT _ DATA _ i₁-1[7：0]Is fed back to a DATA input terminal of the eleventh alternative selector as a DATA _ i generator₁[7：0]The input value of the last sampling address of (1);

one input end of each of the fifth numerical comparator, the sixth numerical comparator, the seventh numerical comparator and the eighth numerical comparator receives FILT _ DATA _ i₁-1[7：0]The other input terminal receives 0, 1, 2 and 3, respectively; an input terminal of the sixteenth not-gate receives EDGE _ DATA _ i₁+1[0](ii) a Two input ends of the twelfth AND gate are respectively connected with the output end of the fifth numerical comparator and the output end of the sixteenth NOT gate; two input terminals of the sixth NOR gate respectively receive EDGE _ DATA _ i₁+1[0]、 EDGE_DATA_i₁+1[1](ii) a Two input ends of the thirteenth AND gate are respectively connected with the output end of the sixth numerical comparator and the output end of the sixth NOR gate; three input terminals of the seventh NOR gate respectively receive EDGE _ DATA _ i₁+1[0]、EDGE_DATA_i₁+1[1]、EDGE_DATA_i₁+1[2](ii) a Two input ends of the fourteenth AND gate are respectively connected with the output end of the seventh numerical comparator and the seventh numerical comparatorThe output end of the NOR gate is connected; four input terminals of the eighth NOR gate respectively receive EDGE _ DATA _ i₁+1[0]、 EDGE_DATA_i₁+1[1]、EDGE_DATA_i₁+1[2]、EDGE_DATA_i₁+1[3](ii) a Two input ends of the fifteenth AND gate are respectively connected with an output end of the eighth numerical comparator and an output end of the eighth NOR gate; the four input ends of the sixth or gate are respectively connected with the output end of the twelfth and gate, the output end of the thirteenth and gate, the output end of the fourteenth and gate and the output end of the fifteenth and gate; eight input terminals of the ninth NOR gate respectively receive EDGE _ DATA _ i₁[0]、EDGE_DATA_i₁[1]、EDGE_DATA_i₁[2]、 EDGE_DATA_i₁[3]、EDGE_DATA_i₁[4]、EDGE_DATA_i₁[5]、EDGE_DATA_i₁[6]、 EDGE_DATA_i₁[7](ii) a Two input ends of the sixteenth AND gate are respectively connected with an output end of the sixth OR gate and an output end of the ninth NOR gate; four input terminals of the seventh OR gate respectively receive EDGE _ DATA _ i₁ [4]、EDGE_DATA_i₁[5]、EDGE_DATA_i₁[6]、EDGE_DATA_i₁[7]Connecting; and two input ends of the eighth or gate are respectively connected with the output end of the sixteenth and gate and the output end of the seventh or gate, and the output end outputs a low-order sampling effective identifier.

Further, the clock data recovery circuit further comprises a shift register; the shift register receives the synchronous data output by the synchronous unit, registers the synchronous data for one beat and two beats, and then outputs the synchronous data of the previous beat and the synchronous data of the previous two beats; the filtering unit receives the synchronous data output by the synchronizing unit and the synchronous data of the previous beat and the synchronous data of the previous two beats output by the shift register and outputs filtering data; the shift register receives the filtering data output by the filtering unit, registers the filtering data for one beat, and outputs the filtering data of the previous beat; the edge detection unit receives the filtering data output by the filtering unit and the previous beat of filtering data output by the shift register and outputs edge detection data; the shift register receives the edge detection data output by the edge detection unit, registers the edge detection data for one beat and moves for two beats, and then outputs the edge detection data for the previous beat and the edge detection data for the previous two beats; the data selection unit receives the previous beat of filtering data output by the filtering unit, the edge detection data output by the edge detection unit, the previous beat of edge detection data output by the shift register and the previous two beats of edge detection data, and outputs high-order sampling data, low-order sampling data, a high-order sampling effective identifier and a low-order sampling effective identifier;

when the filtering unit comprises a filtering circuit, the filtering circuit receives synchronous data output by the synchronizing unit and synchronous data of the previous beat and synchronous data of the previous two beats output by the shift register and outputs first filtering data, wherein the first filtering data is the filtering data output by the filtering unit; when the filtering unit comprises two filtering circuits, a first filtering circuit receives synchronous data output by the synchronizing unit and previous beat synchronous data and previous two beat synchronous data output by the shift register and outputs first filtering data, the shift register receives first filtering data output by the first filtering circuit, the first filtering data is registered for one beat and two beats, the previous beat first filtering data and the previous two beat first filtering data are output, a second filtering circuit receives the first filtering data output by the first filtering circuit and the previous beat first filtering data and the previous two beat first filtering data output by the shift register and outputs second filtering data, and the second filtering data is filtering data output by the filtering unit.

The third purpose of the utility model is to realize a USB clock data recovery circuit that adopts above-mentioned clock data recovery circuit, and the single surge that the filtering occupied a clock phase place and occupied two clock phase places simultaneously reduces high-speed USB data transmission's dislocation rate.

The third purpose of the utility model is realized by the following technical scheme:

a USB clock data recovery circuit adopts the clock data recovery circuit, and serial input data received by the oversampling unit is high-speed USB data.

The utility model discloses beneficial effect: the utility model discloses the filtering unit takes the second bit data in (1, 0, 1), (0, 1, 0) combination to negate, and the filtration occupies the single surge of a clock phase place, and takes the second bit data in (1, 1, 0, 0, 1, 1), (0, 0, 1, 1, 0, 0) combination to negate with the third bit data, and the filtration occupies the single surge of two clock phases; meanwhile, the utility model discloses when the filtering unit filtering is close to the surge at jump border, will jump border translation, reduce the risk that jumps along unusual widen or narrow down, reduce data transmission's dislocation rate. Further, the utility model discloses a second filter circuit carries out the secondary filter to the filtering result of first filter circuit output, and the continuous single surge of complete filtering is failed to the first filter circuit of filtering, reduces data transmission's dislocation rate. Further, the utility model discloses a data selection unit is sampled along four preceding phase clock departments at the filtering data jump of filtering unit output, and when twelve phase clock departments do not detect new jump edge after the jump edge, selects eight phase clock departments of back of last sampling point to sample, reduces because filtering data does not sample when not jumping for a long time and leads to the probability of leaking the sample, reduces data transmission's dislocation rate.

Drawings

In order to more clearly illustrate the embodiments of the present invention, the drawings used in the embodiments will be briefly described below. The drawings in the following description are only examples of the present invention, and other drawings can be obtained by those skilled in the art without inventive efforts.

Fig. 1 is a block diagram of a clock data recovery circuit according to an embodiment of the present invention;

fig. 2 is a schematic circuit diagram of an oversampling unit according to an embodiment of the present invention;

fig. 3 is a schematic circuit diagram of a synchronization unit according to an embodiment of the present invention;

fig. 4 is a block diagram of a first filter circuit according to an embodiment of the present invention;

fig. 5 is a schematic circuit diagram of a j1 th filter of a first filter circuit according to an embodiment of the present invention;

fig. 6 is a block diagram of a second filter circuit according to an embodiment of the present invention;

fig. 7 is a schematic circuit diagram of a j1 filter of a second filter circuit according to an embodiment of the present invention;

fig. 8 is a schematic circuit diagram of an edge detecting unit according to an embodiment of the present invention;

fig. 9 is a block diagram of a data selection unit according to an embodiment of the present invention;

fig. 10 is a schematic circuit diagram of a data sampling circuit according to an embodiment of the present invention;

11-1, 11-2, and 11-3 are schematic circuit diagrams of a sampling valid flag generating circuit according to an embodiment of the present invention;

fig. 12 is a simulation result diagram of a clock data recovery circuit according to an embodiment of the present invention;

fig. 13 is a block diagram of a clock data recovery circuit according to a third embodiment of the present invention.

Detailed Description

The present invention will be described in detail with reference to the accompanying drawings. In order to make the objects, technical solutions and advantages of the present invention more clearly understood, the present invention will be further described in detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

Example one

As shown in fig. 1, a clock data recovery circuit includes an oversampling unit, a synchronization unit, a filtering unit, an edge detecting unit, a data selecting unit, a data storing unit, and a shift register; the filtering unit comprises two filtering circuits; the oversampling unit receives serial input DATA _ IN and eight-phase clocks CLK0, CLK1, CLK2, CLK3, CLK4, CLK5, CLK6, CLK7 having a frequency of 480MHZ, and outputs currently-tapped oversampling DATA SAMPLE _ DATA0 corresponding to different phase clocks; the synchronization unit receives a clock CLK0 and current beat over-sampling DATA SAMPLE _ DATA0 output by the over-sampling unit, outputs current beat synchronization DATA SYNC _ DATA0 subjected to synchronization processing to a first filter circuit and a shift register, and after the shift register registers the current beat synchronization DATA SYNC _ DATA0 for one beat (namely, lagging one beat) and two beats (namely, lagging two beats), outputs previous beat synchronization DATA SYNC _ DATA1 and previous two beat synchronization DATA SYNC _ DATA2 to the first filter circuit; the first filter circuit receives the current beat synchronization DATA SYNC _ DATA0, the previous beat synchronization DATA SYNC _ DATA1 and the previous two beats of synchronization DATA SYNC _ DATA2, outputs the current beat first filter DATA FILT1_ DATA0 subjected to the filter processing to the second filter circuit and the shift register, and outputs the previous beat first filter DATA FILT1_ DATA1 and the previous two beats of first filter DATA FILT1_ DATA2 to the second filter circuit after the shift register registers the current beat first filter DATA FILT1_ DATA0 for one beat (i.e. one beat later) and two beats (i.e. two beats later); the second filter circuit receives the current beat of the first filtered DATA FILT1_ DATA0, the previous beat of the first filtered DATA FILT1_ DATA1 and the previous two beats of the first filtered DATA FILT1_ DATA2, outputs the current beat of the second filtered DATA FILT2_ DATA0 subjected to the filtering processing to the edge detection unit and the shift register, and outputs the previous beat of the second filtered DATA FILT2_ DATA1 to the edge detection unit and the DATA selection unit after the shift register registers the current beat of the second filtered DATA FILT2_ DATA0 for one beat (i.e. lags by one beat); the EDGE detection unit receives the current beat of the second filtered DATA FILT2_ DATA0 and the previous beat of the second filtered DATA FILT2_ DATA1, outputs the current beat of the EDGE detection DATA EDGE _ DATA0 to the DATA selection unit and the shift register, and after the shift register registers the current beat of the EDGE detection DATA EDGE _ DATA0 for one beat (namely, one beat lags) and two beats (namely, two lags), outputs the previous beat of the EDGE detection DATA EDGE _ DATA1 and the previous two beats of the EDGE detection DATA EDGE _ DATA2 to the DATA selection unit; the DATA selection unit receives the current beat of EDGE detection DATA EDGE _ DATA0, the previous beat of EDGE detection DATA EDGE _ DATA1, the previous two beats of EDGE detection DATA EDGE _ DATA2, and the previous beat of second filtered DATA FILT2_ DATA1, and then outputs the high-order sample DATA _ H1 of the previous beat of second filtered DATA FILT2_ DATA1, the low-order sample DATA _ L1 of the previous beat of second filtered DATA FILT2_ DATA1, the high-order sample VALID flag VALID _ H1 of the previous beat of second filtered DATA FILT2_ DATA1, and the low-order sample VALID flag VALID _ L1 of the previous beat of second filtered DATA FILT2_ DATA1 to the DATA storage unit; the DATA storage unit outputs the sample VALID DATA _ OUT according to the high sample DATA _ H1, the low sample DATA _ L1, the high sample VALID flag VALID _ H1, and the low sample VALID flag VALID _ L1 output from the DATA selection unit.

In the present embodiment, the current beat DATA X _ DATA0, the previous beat DATA X _ DATA1, and the previous two beat DATA X _ DATA2 each include … … X _ DATA _ N-1[ 7: 0]、X_DATA_N[7：0]、X_DATA_N+1[7：0]… …, the DATA X _ DATA0, the DATA X _ DATA1 and the DATA X _ DATA2 of the previous beat and the DATA X _ DATA 3526 of the next two beats output the DATA X _ DATA _ i of the adjacent DATA of the third beat and the DATA X _ DATA _ i of the next two beats at the same time respectively, with different timings₁+1[7：0]、 X_DATA_i₁[7：0]、X_DATA_i₁-1[7：0]To the next stage circuit; x _ DATA _ i₁[7：0]Including X _ DATA _ i₁[0]、X_DATA_i₁[1]、X_DATA_i₁[2]、X_DATA_i₁[3]、X_DATA_i₁[4]、 X_DATA_i₁[5]、X_DATA_i₁[6]、X_DATA_i₁[7]；X_DATA_i₁+1[7：0]Is X _ DATA _ i₁[7：0]Eight-bit DATA of the latter beat, X _ DATA _ i₁-1[7：0]Is X _ DATA _ i₁[7：0]Eight bits of data in the previous beat, X is SYNC or FILT1 or FILT2 or EDGE, N is an integer, i₁… … N-1, N, N +1 … … (the same applies hereinafter).

In the present embodiment, adjacent three-beat eight-bit DATA Y _ DATA _ i₁-1[7：0]、Y_DATA_i₁[7：0]And Y _ DATA _ i₁+1[7：0]The component 24-bit DATA Y _ DATA _ ALL _ i₁[23：0]；Y_DATA_ALL_i₁[23：0]Including Y _ DATA _ ALL _ i₁[0](i.e., Y _ DATA _ i)₁-1[0])、Y_DATA_ALL_i₁[1](i.e., Y _ DATA _ i)₁-1 [1])、Y_DATA_ALL_i₁[2](i.e., Y _ DATA _ i)₁-1[2])、Y_DATA_ALL_i₁[3](i.e., Y _ DATA _ i)₁ -1[3])、Y_DATA_ALL_i₁[4](i.e., Y _ DATA _ i)₁-1[4])、Y_DATA_ALL_i₁[5](i.e., Y _ DATA _ i)₁-1[5])、Y_DATA_ALL_i₁[6](i.e., Y _ DATA _ i)₁-1[6])、Y_DATA_ALL_i₁[7](i.e., Y _ DATA _ i)₁-1[7])、Y_DATA_ALL_i₁[8](i.e., Y _ DATA _ i)₁[0])、Y_DATA_ALL_i₁[9](i.e., Y _ DATA _ i)₁[1])、Y_DATA_ALL_i₁[10](i.e., Y _ DATA _ i)₁[2])、Y_DATA_ALL_i₁[11](i.e., Y _ DATA _ i)₁[3])、Y_DATA_ALL_i₁[12](i.e., Y _ DATA _ i)₁[4])、Y_DATA_ALL_i₁[13](i.e., Y _ DATA _ i)₁[5])、Y_DATA_ALL_i₁[14](i.e., Y _ DATA _ i)₁[6])、Y_DATA_ALL_i₁[15](i.e., Y _ DATA _ i)₁[7])、Y_DATA_ALL_i₁[16](i.e., Y _ DATA _ i)₁+1[0])、Y_DATA_ALL_i₁[17](i.e., Y _ DATA _ i)₁+1[1])、Y_DATA_ALL_i₁[18](i.e., Y _ DATA _ i)₁+1[2])、Y_DATA_ALL_i₁[ 19](i.e., Y _ DATA _ i)₁+1[3])、Y_DATA_ALL_i₁[20](i.e., Y _ DATA _ i)₁+1[4])、Y_DATA_ALL_ i₁[21](i.e., Y _ DATA _ i)₁+1[5])、Y_DATA_ALL_i₁[22](i.e., Y _ DATA _ i)₁+1[6])、 Y_DATA_ALL_i₁[23](i.e., Y _ DATA _ i)₁+1[7]) And Y is SYNC or FILT 1.

In the present embodiment, the high-order sampled DATA DATA _ H1 includes … … DATA _ H _ N-1, DATA _ H _ N, DATA _ H _ N +1 … …, DATA _ H _ i₁Is FILT2_ DATA _ i in the second filtered DATA FILT2_ DATA1 from the previous beat₁[7：4]A sampled one bit of data; the lower sampled DATA DATA _ L1 includes … … DATA _ L _ N-1, DATA _ L _ N, DATA _ L _ N +1 … …, DATA _ L _ i₁Is FILT2_ DATA _ i in the second filtered DATA FILT2_ DATA1 from the previous beat₁[3：0]A sampled one bit of data; the high-order sample VALID flag VALID _ H1 includes … … VALID _ H _ N-1, VALID _ H _ N, VALID _ H _ N +1 … …, VALID _ H _ i₁FILT2_ DATA _ i for determining second filtered DATA FILT2_ DATA1 from the previous beat₁[7：4]Middle sampled DATA _ H _ i₁Whether it is valid; the VALID identification VALID _ L1 of the previous beat of low-order samples includes … … VALID _ L _ N-1, VALID _ L _ N, VALID _ L _ N +1 … …, VALID _ L _ i₁FILT2_ DATA _ i for determining second filtered DATA FILT2_ DATA1 from the previous beat₁[3：0]Middle sampled DATA _ L _ i₁Whether it is valid.

In this embodiment, the serial input data received by the oversampling unit is USB2.0 with a transmission rate of 480Mbps, which is high-speed transmission data, and the clock data recovery circuit is a high-speed USB clock data recovery circuit; the oversampling unit oversamples the input DATA _ IN eight times by eight-phase clocks CLK0, CLK1, CLK2, CLK3, CLK4, CLK5, CLK6, CLK 7; the synchronization unit carries out synchronization processing on the current beat over-sampled data through a sampling clock CLK 0; the first filter circuit passes the decision … … SYNC _ DATA _ N-1[ 7: 0]、SYNC_DATA_N[7：0]、SYNC_DATA_N+1[7：0]… …, if the leading three-bit SYNC DATA matches (1, 0, 1) or (0, 1, 0) combination and the adjacent six-bit DATA matches (1, 1, 0, 0, 1, 1) or (0, 0, 1, 1, 0, 0) combination, filtering … … SYNC _ DATA _ N-1[ 7: 0]、 SYNC_DATA_N[7：0]、SYNC_DATA_N+1[7：0]… …, a single glitch (1, 0, 1), (0, 1, 0) occupying one phase and a single glitch (1, 1, 0, 0, 1, 1), (0, 0, 1, 1, 0, 0) occupying two phases, 1 being output as a filtering result of the second bit sync data in the (1, 0, 1) combination if the adjacent three bit sync data matches the (1, 0, 1) combination, 0 being output as a filtering result of the second bit sync data in the (0, 1, 0) combination if the adjacent three bit data matches the (0, 1, 0) combination, 1 being output as a filtering result of the second bit sync data and the third bit sync data in the (1, 1, 0, 0, 1, 1) combination if the adjacent six bit data matches the (1, 1, 0, 0, 1, 1) combination, 1 being output as a filtering result of the second bit sync data and the third bit sync data in the (1, 1, 0, 1, 1, 1, 0, 1, 1, 0, 0) combination, then 0 is output as the filtering result of the second bit synchronization data and the third bit synchronization data in the (0, 0, 1, 1, 0, 0) combination, otherwise, the input synchronization data is output as the filtering result; the second filter circuit passes the results of the decisions … …, FILT1_ DATA _ N-1[ 7: 0]、FILT1_DATA_N[7：0]、 FILT1_DATA_N+1[7：0]… … whether or not adjacent three-bit first filtered data corresponds to (1, 0, 1) or (0, 1, 0) combination and whether or not adjacent six-bit first filtered data corresponds to (1, 1, 0, 0, 1, 1) or (0, 0)1, 1, 0, 0), filtered … …, FILT1_ DATA _ N-1[ 7: 0]、FILT1_DATA_N[7：0]、 FILT1_DATA_N+1[7：0]… …, (1, 0, 1), (0, 1, 0) and (1, 1, 0, 0, 1, 1), (0, 0, 1, 1, 0, 0) of two phases, and further filters … …, SYNC _ DATA _ N-1[ 7: 0]，SYNC_DATA_N[7：0]， SYNC_DATA_N+1[7：0]… …, a single glitch (1, 0, 1, 0, 1), (0, 1, 0, 1, 1, 0) which continuously occupies one phase, and a single glitch (1, 1, 0, 0, 1, 1, 0, 0, 1, 1), (0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 1, 0, 0) which continuously occupies two phases, 1 is output as a filtering result of the second-bit first filtered data in the (1, 0, 1) combination if the adjacent three-bit first filtered data matches the (1, 0, 1) combination, 0 is output as a filtering result of the second-bit first filtered data in the (0, 1, 0) combination if the adjacent three-bit first filtered data matches the (0, 1, 0, 0, 1, 1) combination, 1 is output as (1, 1, 0, 0, 1, 1) outputting the filtering results of the second bit first filtering data and the third bit first filtering data in the combination, if the adjacent six bits of data accord with (0, 0, 1, 1, 0, 0) combination, outputting 0 as the filtering results of the second bit first filtering data and the third bit first filtering data in (0, 0, 1, 1, 0, 0) combination, otherwise, outputting the input first filtering data as the filtering results; the edge detection unit detects the edge by determining … … FILT2_ DATA _ N-1[ 7: 0]、FILT2_DATA_N[7：0]… … if the adjacent two bits of second filtered DATA are equal, if not, outputting 1 as the EDGE detection result of the next bit of second filtered DATA, otherwise, outputting 0 as the EDGE detection result of the next bit of second filtered DATA, that is, when the EDGE _ DATA _ i is equal₁[j₁]Equal to 1, FILT2_ DATA _ i₁[j₁]When a transition occurs, when EDGE _ DATA _ i₁[j₁]Equal to 0, FILT2_ DATA _ i₁[j₁]No jump,

j

₁0, 1, 2, 3, 4, 5, 6, 7; the DATA selection unit selects the DATA by … … EDGE _ DATA _ N-1[ 7: 0]、EDGE_DATA_N[7：0]、 EDGE_DATA_N+1[7：0]……Select … … FILT2_ DATA _ N-1[ 7: 0]、 FILT2_DATA_N[7：0]、FILT2_DATA_N+1[7：0]… … sampling four phase clocks before the jump edge, and selecting the last eight phase clocks of the last sampling point to sample when no new jump edge is detected at any of twelve phase clocks after the jump edge; VALID identification VALID _ H _ i of data storage unit in high-order sampling₁Storing high DATA _ H _ i when active₁VALID flag VALID _ L _ i at low-order sample₁Storing the lower sampled DATA DATA _ L _ i when active₁VALID flag VALID _ H _ i at high-order sample₁And a low-order sample VALID flag VALID _ L _ i₁When all valid, the low-order sampling DATA DATA _ L _ i is stored first₁And then stores the high-order sample DATA DATA _ H _ i₁VALID flag VALID _ H _ i at high-order sample₁And a low-order sample VALID flag VALID _ L _ i₁All invalid, the high-order sample DATA DATA _ H _ i is not stored₁Nor does it store the low-order sample VALID flag VALID _ L _ i₁(ii) a The DATA storage unit outputs one DATA _ OUT after storing eight bits of DATA each time, and outputs a DATA VALID flag DATA _ VALID indicating whether the output DATA is VALID.

In this embodiment, when the high-order sample is VALID, the flag VALID _ H _ i₁Equal to 1, FILT2_ DATA _ i₁[7：0]High-order sampling is effective; when the high-order sample is VALID, the flag VALID _ H _ i₁Equal to 0, FILT2_ DATA _ i₁[7：0]High-order sampling is invalid; when the low-order sample is VALID, the flag VALID _ L _ i₁Equal to 1, FILT2_ DATA _ i₁[7：0]Low-order sampling is effective; when the low-order sample is VALID, the flag VALID _ L _ i₁Equal to 0, FILT2_ DATA _ i₁[7：0]The low-order sampling is invalid; when the DATA VALID flag DATA _ VALID is equal to 1, the DATA output by the DATA storage unit is VALID; when the DATA VALID flag DATA _ VALID is equal to 0, the DATA output from the DATA storage unit is invalid.

As shown IN FIG. 2, IN the embodiment, the over-sampling unit includes eight first registers RGE1, the DATA inputs of the eight first registers REG1 all receive the input DATA DATA _ IN, the reset signal inputs all receive the reset signal RST _ N, and the clock inputs respectively receive the clock signals RST _ NCLK0, CLK1, CLK2, CLK3, CLK4, CLK5, CLK6, CLK7, the output terminals of which respectively output SAMPLE _ DATA _ i₁[0]、SAMPLE_DATA_i₁[1]、 SAMPLE_DATA_i₁[2]、SAMPLE_DATA_i₁[3]、SAMPLE_DATA_i₁[4]、SAMPLE_DATA_i₁ [5]、SAMPLE_DATA_i₁[6]、SAMPLE_DATA_i₁[7]Composition SAMPLE _ DATA _ i₁[7：0]Because i is₁… … N-1, N, N +1 … …, and so on, the current beat of oversampled DATA SAMPLE _ DATA0 output by the oversampling unit includes … … SAMPLE _ DATA _ N-1[ 7: 0]、SAMPLE_DATA_N[7：0]、SAMPLE_ DATA_N+1[7：0]……。

As shown in FIG. 3, the synchronization unit includes a second register REG2, a DATA input terminal of the second register REG2 receiving SAMPLE _ DATA _ i₁[7：0]A reset signal input terminal receiving a reset signal RST _ N, a clock input terminal receiving a clock CLK0, and an output terminal outputting SYNC _ DATA _ i₁[7：0]Because i is₁… … N-1, N, N +1 … …, and so on, the synchronization unit receives the current beat oversampled DATA SAMPLE _ DATA0, and outputs current beat synchronization DATA SYNC _ DATA0 including … … SYNC _ DATA _ N-1[ 7: 0]、SYNC_DATA_N[7：0]、SYNC_DATA _N+1[7：0]… … are provided. As shown in fig. 4, the first filter circuit includes eight filters, FILT1_0, FILT1_1, FILT1_2, FILT1_3, FILT1_4, FILT1_5, FILT1_6, and FILT1_ 7; j th₁Filter FILT1_ j₁Receive SYNC _ DATA _ ALL _ i₁[j₁+5]、SYNC_DATA_ALL_i₁[j₁+6]、 SYNC_DATA_ALL_i₁[j₁+7]、SYNC_DATA_ALL_i₁[j₁+8]、SYNC_DATA_ALL_i₁[j₁+9]、 SYNC_DATA_ALL_i₁[j₁+10]、SYNC_DATA_ALL_i₁[j₁+11]Filtering out the SYNC _ DATA _ i as a surge₁[j₁]Outputs SYNC _ DATA _ i₁[j₁]Filter result FILT1_ DATA _ i of₁[j₁]， j₁By analogy with 0, 1, 2, 3, 4, 5, 6, 7, eight filters FILT1_0, FILT1_1, FILT1_2, FILT1_3, FILT1_4, FILT1_5, FILT1_6, and FILT1_7 respectively filter out SYNC _ DATA _ i that becomes a surge₁[0]、SYNC_DATA_i₁[1]、SYNC_DATA_i₁[2]、SYNC_DATA_i₁[3]、 SYNC_DATA_i₁[4]、SYNC_DATA_i₁[5]、SYNC_DATA_i₁[6]、SYNC_DATA_i₁[7]Outputs the filtering result FILT1_ DATA _ i₁[0]、FILT1_DATA_i₁[1]、FILT1_DATA_i₁[2]、 FILT1_DATA_i₁[3]、FILT1_DATA_i₁[4]、FILT1_DATA_i₁[5]、FILT1_DATA_i₁[6]、 FILT1_DATA_i₁[7]，FILT1_DATA_i₁[0]、FILT1_DATA_i₁[1]、FILT1_DATA_i₁[2]、FILT1_DATA_i₁[3]、FILT1_DATA_i₁[4]、FILT1_DATA_i₁[5]、FILT1_DATA_i₁[6]、 FILT1_DATA_i₁[7]Composition FILT1_ DATA _ i₁[7：0](ii) a Due to i₁… … N-1, N, N +1 … …, and so on, the first filter circuit receives the current beat SYNC DATA SYNC _ DATA0, the previous beat SYNC DATA SYNC _ DATA1, and the previous two beat SYNC DATA SYNC _ DATA2, and outputs the current beat first filter DATA including … … FILT1_ DATA _ N-1[ 7: 0]、FILT1_DATA_N[7：0]、FILT1_DATA_N+1[7：0]……。

As shown in FIG. 5, in the present embodiment, the j-th₁Filter FILT1_ j₁The circuit comprises a first filtering set signal generating circuit, a first filtering reset signal generating circuit and a first one-out-of-three selecting unit; the first filtering set signal generating circuit comprises a first AND gate AND101, a second AND gate AND102, a third AND gate AND103, a first NOT101, a second NOT102, a third NOT103, a fourth NOT104, a fifth NOT105 AND a first OR gate OR 101; the first filtering reset signal generation circuit comprises a fourth AND gate AND104, a fifth AND gate AND105, a sixth AND gate AND106, a sixth NOT gate NOT106, a seventh NOT gate NOT107, an eighth NOT gate NOT108, a ninth NOT gate NOT109, a tenth NOT gate NOT110, an eleventh NOT gate NOT111, a twelfth NOT gate NOT112, a thirteenth NOT gate NOT113, a fourteenth NOT gate NOT114, a fifteenth NOT gate NOT115 AND a second OR gate OR 102; the first one-of-three selection unit includes a first one-of-two selector MUX2101 and a second one-of-two selector MUX 2102.

In this embodiment, the control principle of all the alternative selectors is as follows: when the control signal input terminal sel receives 1, the output terminal out selects the data output of the data input terminal b; when the control signal input terminal sel receives 0, the output terminal selects the data output of the data input terminal a.

As shown in fig. 5, the first AND gate AND101 includes three input terminals receiving SYNC _ DATA _ ALL _ i AND one output terminal receiving SYNC _ DATA _ ALL _ i₁[j₁+7]、SYNC_DATA_ALL_i₁[j₁+9]The other input terminal of the first NOT gate is connected to the output terminal of the first NOT gate NOT101, and the input terminal of the first NOT gate NOT101 receives SYNC _ DATA _ ALL _ i₁[j₁+9](ii) a The second AND gate AND102 includes six input terminals receiving SYNC _ DATA _ ALL _ i, respectively, AND one output terminal₁[j₁+6]、SYNC_DATA_ALL_i₁[j₁+7]、 SYNC_DATA_ALL_i₁[j₁+10]And SYNC _ DATA _ ALL _ i₁[j₁+11]The other two input terminals are respectively connected to the output terminal of the second NOT gate NOT102 and the output terminal of the third NOT gate NOT103, and the input terminal of the second NOT gate NOT102 and the input terminal of the third NOT gate NOT103 respectively receive SYNC _ DATA _ ALL _ i₁[j₁+8]And SYNC _ DATA _ ALL _ i₁[j₁+9](ii) a The third AND gate AND103 includes six input terminals receiving SYNC _ DATA _ ALL _ i, AND one output terminal₁[j₁+5]、SYNC_DATA_ALL_i₁[j₁+6]、SYNC_DATA_ALL_i₁[j₁+9]And SYNC _ DATA _ ALL _ i₁[j₁+10]The other two input terminals are respectively connected to the output terminal of the fourth NOT gate NOT104 and the output terminal of the fifth NOT gate NOT105, and the input terminal of the fourth NOT gate NOT104 and the input terminal of the fifth NOT gate NOT105 respectively receive SYNC _ DATA _ ALL i₁[j₁+7]And SYNC _ DATA _ ALL _ i₁[j₁+8](ii) a The output end of the first AND gate AND101, the output end of the second AND gate AND102, AND the output end of the third AND gate AND103 are respectively connected to three input ends of the first OR gate OR101, the output end of the first OR gate OR101 is electrically connected to the control signal input end sel of the first one-out-of-two selector MUX2101, AND the first filtering setting signal FILT1_ SET _ i is output₁[j₁]To a firstA control signal input terminal sel of an one-out-of-two selector MUX2101, and a DATA input terminal a and a DATA input terminal b of the first one-out-of-two selector MUX2101 receive SYNC _ DATA _ i₁[j₁]And 1.

As shown in fig. 5, the fourth AND gate AND104 includes three input terminals AND one output terminal, AND one input terminal receives SYNC _ DATA _ ALL _ i₁[j₁+8]The other two input terminals are respectively connected to the output terminal of the sixth NOT gate NOT106 and the output terminal of the seventh NOT gate NOT107, and the input terminal of the sixth NOT gate NOT106 and the input terminal of the seventh NOT gate NOT107 respectively receive SYNC _ DATA _ ALL _ i₁[j₁+7]、SYNC_DATA_ALL_i₁[j₁+9](ii) a The fifth AND gate AND105 includes six input terminals receiving SYNC _ DATA _ ALL _ i, AND one output terminal₁[j₁+8]、SYNC_DATA_ALL_i₁[j₁+9]The other four input terminals are respectively connected to the output terminal of the eighth NOT gate NOT108, the output terminal of the ninth NOT gate NOT109, the output terminal of the tenth NOT gate NOT110, and the output terminal of the eleventh NOT gate NOT111, and the input terminals of the eighth NOT gate NOT108, the ninth NOT gate NOT109, the tenth NOT gate NOT110, and the eleventh NOT gate NOT111 respectively receive SYNC _ DATA _ ALL _ i₁[j₁+6]、SYNC_DATA_ALL_i₁[j₁+7]、SYNC_DATA_ALL _i₁[j₁+10]And SYNC _ DATA _ ALL _ i₁[j₁+11](ii) a The sixth AND gate AND106 includes six input terminals receiving SYNC _ DATA _ ALL _ i AND one output terminal₁[j₁+7]、SYNC_DATA_ALL_i₁[j₁ +8]The other four input terminals are respectively connected to the output terminal of the twelfth NOT gate NOT112, the output terminal of the thirteenth NOT gate NOT113, the output terminal of the fourteenth NOT gate NOT114, and the output terminal of the fifteenth NOT gate 115, and the input terminal of the twelfth NOT gate NOT112, the input terminal of the thirteenth NOT gate NOT113, the input terminal of the fourteenth NOT gate NOT114, and the input terminal of the fifteenth NOT gate NOT115 respectively receive SYNC _ DATA _ ALL _ i₁[j₁+5]、 SYNC_DATA_ALL_i₁[j₁+6]、SYNC_DATA_ALL_i₁[j₁+9]And SYNC _ DATA _ ALL _ i₁[j₁+10 ](ii) a An output terminal of the fourth AND gate AND104, an output terminal of the fifth AND gate AND105, AND an output terminal of the sixth AND gate AND106 are respectively connected to three input terminals of the second OR gate OR102, an output terminal of the second OR gate OR102 is electrically connected to the control signal input terminal sel of the second one-out-of-two selector MUX2102, AND outputs the first filter reset signal FILT1_ CLR _ i₁[j₁]To the control signal input terminal sel of the second alternative selector MUX2102, the DATA input terminal a of the second alternative selector MUX2102 is connected to the output terminal out of the first alternative selector MUX2101, the DATA input terminal b is connected to 0, and the output terminal outputs SYNC _ DATA _ i₁[j₁]Filter result FILT1_ DATA _ i of₁[j₁]。

As shown in FIG. 12, in the present embodiment, the j-th₁Filter FILT1_ j₁Filtering out SYNC _ DATA _ i as a glitch₁[j₁]The working principle is as follows: when SYNC _ DATA _ i₁[j₁]One of cases one, two, three, four, five, six, namely SYNC _ DATA _ i, occurs₁[j₁]The j-th surge in combination with (1, 0, 1), (0, 1, 0), (1, 1, 0, 0, 1, 1), (0, 0, 1, 1, 0, 0, 0)₁Filter FILT1_ j₁Will SYNC _ DATA _ i₁[j₁]Inverted output, i.e. filter out the SYNC _ DATA _ i that becomes a surge₁[j₁](ii) a When SYNC _ DATA _ i₁[j₁]Case seven occurs, namely SYNC _ DATA _ i₁[j₁]When not surge, j₁Filter FILT1_ j₁Directly send SYNC _ DATA _ i₁[j₁]And (6) outputting.

The first condition is as follows: SYNC _ DATA _ ALL _ i₁[j₁+7]And SYNC _ DATA _ ALL _ i₁[j₁+9]Equal to 1, SYNC _ DATA _ ALL _ i₁[j₁+8]Equal to 0, SYNC _ DATA _ i₁[j₁]The front AND rear bit data form a (1, 0, 1) surge, the first AND gate AND101 outputs 1, AND the first filtering setting signal FILT1_ SET _ i output by the first OR gate OR101₁[j₁]Equal to 1, the first one-out selector MUX2101 selects the 1 output, the fourth AND gate AND104, the fifth AND gate AND105 AND the sixth AND gate AND106 output 0, the second OR gate OR102 outputFirst filtered reset signal FILT1_ SET _ i₁[j₁]Equal to 0, the second alternative selector MUX2102 selects the 1 output by the first alternative selector MUX2101 as SYNC _ DATA _ i₁[j₁]Filter result FILT1_ DATA _ i of₁[j₁]Output, i.e. j₁Filter FILT1_ j₁Will be the original SYNC _ DATA _ i₁[j₁]Changing from 0 to 1 output.

Case two: SYNC _ DATA _ ALL _ i₁[j₁+6]、SYNC_DATA_ALL_i₁[j₁+7]、SYNC_DATA_ALL _i₁[j₁+10]、SYNC_DATA_ALL_i₁[j₁+11]Equal to 1, SYNC _ DATA _ ALL _ i₁[j₁+8]、 SYNC_DATA_ALL_i₁[j₁+9]Equal to 0, SYNC _ DATA _ i₁[j₁]With its preceding AND following bit data components (1, 1, 0, 0, 1, 1) burst, the second AND gate AND102 outputs 1, AND the first OR gate OR101 outputs the first filter SET signal FILT1_ SET _ i₁[j₁]Equal to 1, the first one-out selector MUX2101 selects the 1 output, the fourth AND gate AND104, the fifth AND gate AND105 AND the sixth AND gate AND106 output 0, the first filter reset signal FILT1_ SET _ i output by the second OR gate OR102₁[j₁]Equal to 0, the second alternative selector MUX2102 selects the 1 output by the first alternative selector MUX2101 as SYNC _ DATA _ i₁[j₁]Filter result FILT1_ DATA _ i of₁[j₁]Output, i.e. j₁Filter FILT1_ j₁Will be the original SYNC _ DATA _ i₁[j₁]Changing from 0 to 1 output.

Case three: SYNC _ DATA _ ALL _ i₁[j₁+5]、SYNC_DATA_ALL_i₁[j₁+6]、SYNC_DATA_ALL _i₁[j₁+9]、SYNC_DATA_ALL_i₁[j₁+10]Equal to 1, SYNC _ DATA _ ALL _ i₁[j₁+7]、SYNC_ DATA_ALL_i₁[j₁+8]Equal to 0, SYNC _ DATA _ i₁[j₁]With its preceding AND following bit data components (1, 1, 0, 0, 1, 1) burst, the third AND gate AND103 outputs 1, AND the first OR gate OR101 outputs the first filter SET signal FILT1_ SET _ i₁[j₁]Equal to 1, the first one-out selector MUX2101 selects the 1 output, the fourth AND gate AND104, the fifth AND gate AND105 AND the sixth AND gate AND106 output 0, the first filter reset signal FILT1_ SET _ i output by the second OR gate OR102₁[j₁]Equal to 0, the second alternative selector MUX2102 selects the 1 output by the first alternative selector MUX2101 as SYNC _ DATA _ i₁[j₁]Filter result FILT1_ DATA _ i of₁[j₁]Output, i.e. j₁Filter FILTI _ j₁Will be the original SYNC _ DATA _ i₁[j₁]Changing from 0 to 1 output.

Case four: SYNC _ DATA _ ALL _ i₁[j₁+7]And SYNC _ DATA _ ALL _ i₁[j₁+9]Equal to 0, SYNC _ DATA _ ALL _ i₁[j₁+8]Equal to 1, SYNC _ DATA _ i₁[j₁]With its preceding AND following bit data forming a (0, 1, 0) burst, the fourth AND gate AND104 outputs 1, AND the second OR gate OR102 outputs the first filter SET signal FILT1_ SET _ i₁[j₁]Equal to 1, the second alternative selector MUX2102 selects 0 as SYNC _ DATA _ i₁ [j₁]Filter result FILT1_ DATA _ i of₁[j₁]Output, i.e. j₁Filter FILT1_ j₁Will be the original SYNC _ DATA _ i₁[j₁]Changing from 1 to 0 output.

Case five: SYNC _ DATA _ ALL _ i₁[j₁+6]、SYNC_DATA_ALL_i₁[j₁+7]、SYNC_DATA_ALL _i₁[j₁+10]、SYNC_DATA_ALL_i₁[j₁+11]Equal to 0, SYNC _ DATA _ ALL _ i₁[j₁+8]、SYNC_ DATA_ALL_i₁[j₁+9]Equal to 1, SYNC _ DATA _ i₁[j₁]With its front AND rear bit data forming (0, 0, 1, 1, 0, 0) burst, the fifth AND gate AND105 outputs 1, AND the second OR gate OR102 outputs the first filter SET signal FILT1_ SET _ i₁[j₁]Equal to 1, the second alternative selector MUX2102 selects 0 as SYNC _ DATA _ i₁[j₁]Filter result FILT1_ DATA _ i of₁[j₁]Output, i.e. j₁Filter FILT1_ j₁Will be the original SYNC _ DATA _ i₁[j₁]Changing from 1 to 0 output.

Case six: SYNC _ DATA _ ALL _ i₁[j₁+5]、SYNC_DATA_ALL_i₁[j₁+6]、SYNC_DATA_ALL _i₁[j₁+9]、SYNC_DATA_ALL_i₁[j₁+10]Equal to 0, SYNC _ DATA _ ALL _ i₁[j₁+7]、SYNC_DATA _ALL_i₁[j₁+8]Equal to 1, synchronization DATA SYNC _ DATA _ i₁[j₁]With its preceding and following bit data forming a (0, 0, 1, 1, 0, 0) burst, the first filtered reset signal FILT1_ SET _ i output by the second OR gate OR102₁[j₁]Equal to 1, the second alternative selector MUX2102 selects 0 as SYNC _ DATA _ i₁[j₁]Filter result FILT1_ DATA _ i of₁[j₁]Output, i.e. j₁Filter FILT1_ j₁Will be the original SYNC _ DATA _ i₁[j₁]Changing from 1 to 0 output.

Case seven: SYNC _ DATA _ N [ j [ ]₁]Any one of the first, second, third, fourth, fifth AND sixth conditions does not occur, the outputs of the first AND gate AND101, the second AND gate AND102, the third AND gate AND103, the fourth AND gate AND104, the fifth AND gate AND105 AND the sixth AND gate AND106 are all equal to 0, AND the first filtering setting signal FILT1_ SET _ i output by the first OR gate OR101₁[j₁]The first filter reset signal FILT1_ SET _ i output from the second OR gate OR102₁[j₁]Are all equal to 0, the first alternative selector MUX2101 selects SYNC _ DATA _ i₁[j₁]Output, the second alternative selector MUX2102 selects SYNC _ DATA _ i output by the first alternative selector MUX2101₁[j₁]As SYNC _ DATA _ i₁[j₁]Filter result FILT1_ DATA _ i of₁[j₁]Output, i.e. j₁Filter FILT1_ j₁Directly send SYNC _ DATA _ i₁[j₁]And (6) outputting.

As shown in fig. 6, the second filter circuit includes eight filters, FILT2_0, FILT2_1, FILT2_2, FILT2_3, FILT2_4, FILT2_5, FILT2_6, and FILT2_ 7; j th₁Filter FILT2_ j₁Receive FILT1_ DATA _ ALL _ i₁[j₁+5]、FILT1_DATA_ALL_i₁[j₁+6]、FILT1_DATA_ALL_i₁ [j₁+7]、FILT1_DATA_ALL_i₁[j₁+8]、FILT1_DATA_ALL_i₁[j₁+9]、FILT1_DATA_ALL _i₁[j₁+10]、FILT1_DATA_ALL_i₁[j₁+11]Filter out FILT1_ DATA _ i as a surge₁[j₁]Output FILT1_ DATA _ i₁[j₁]Filter result FILT1_ DATA _ i of₁[j₁]By analogy, the eight filters FILT2_0, FILT2_1, FILT2_2, FILT2_3, FILT2_4, FILT2_5, FILT2_6, and FILT2_7 respectively filter out FILT1_ DATA _ i that becomes a surge₁[0]、FILT1_DATA_i₁[1]、FILT1_DATA_i₁[2] 、FILT1_DATA_i₁[3]、FILT1_DATA_i₁[4]、FILT1_DATA_i₁[5]、FILT1_DATA_i₁[6]、FILT1_DATA_i₁[7]Outputs the filtering result FILT2_ DATA _ i₁[0]、FILT2_DATA_i₁[1]、 FILT2_DATA_i₁[2]、FILT2_DATA_i₁[3]、FILT2_DATA_i₁[4]、FILT2_DATA_i₁[5]、 FILT2_DATA_i₁[6]、FILT2_DATA_i₁[7]，FILT2_DATA_i₁[0]、FILT2_DATA_i₁[1]、 FILT2_DATA_i₁[2]、FILT2_DATA_i₁[3]、FILT2_DATA_i₁[4]、FILT2_DATA_i₁[5]、FILT2_DATA_i₁[6]、FILT2_DATA_i₁[7]Composition FILT2_ DATA _ i₁[7：0](ii) a Due to i₁… … N-1, N, N +1 … …, and so on, the second filter circuit receives the current beat first filtered DATA FILT1_ DATA0, the previous beat first filtered DATA FILT1_ DATA1, and the previous two beats first filtered DATA FILT1_ DATA2, and outputs the current beat second filtered DATA including … … FILT2_ DATA _ N-1[ 7: 0]、 FILT2_DATA_N[7：0]、FILT2_DATA_N+1[7：0]……。

As shown in FIG. 7, in the present embodiment, the j-th₁Filter FILT2_ j₁The circuit comprises a second filtering set signal generating circuit, a second filtering reset signal generating circuit and a second one-out-of-three selecting unit; the second filtering setting signal generating circuit comprises a first AND gate AND201, a second AND gate AND202, a third AND gate AND203 AND a first AND gateAn NOT gate NOT201, a second NOT gate NOT202, a third NOT gate NOT203, a fourth NOT gate NOT204, a fifth NOT gate NOT205, and a first OR gate OR 201; the second filtering reset signal generation circuit comprises a fourth AND gate AND204, a fifth AND gate AND205, a sixth AND gate AND206, a sixth NOT gate NOT206, a seventh NOT gate NOT207, an eighth NOT gate NOT208, a ninth NOT gate NOT209, a tenth NOT gate NOT210, an eleventh NOT gate NOT211, a twelfth NOT gate NOT212, a thirteenth NOT gate NOT213, a fourteenth NOT gate NOT214, a fifteenth NOT gate NOT215 AND a second or gate 0R 202; the second one-of-three selection unit includes a first one-of-two selector MUX2201 and a second one-of-two selector MUX 2202.

As shown in fig. 7, the first AND gate AND201 includes three input terminals receiving FILT1_ DATA _ ALL _ i, AND an output terminal₁[j₁+7]、FILT1_DATA_ALL_i₁[j₁+9]The other input terminal of the first NOT gate NOT201 is connected to the output terminal of the first NOT gate NOT201, and the input terminal of the first NOT gate NOT201 receives FILT1_ DATA _ ALL _ i₁[j₁+9](ii) a The second AND gate AND202 includes six input terminals receiving FILT1_ DATA _ ALL _ i, respectively, AND one output terminal₁[j₁+6]、FILT1_DATA_ALL_i₁[j₁+7]、 FILT1_DATA_ALL_i₁[j₁+10]And FILT1_ DATA _ ALL _ i₁[j₁+11]Two other input terminals are respectively connected to the output terminal of the second NOT gate NOT202 and the output terminal of the third NOT gate NOT203, and the input terminal of the second NOT gate NOT202 and the input terminal of the third NOT gate NOT203 respectively receive FILT1_ DATA _ ALL _ i₁[j₁+8]And FILT1_ DATA _ ALL _ i₁[j₁+9](ii) a The third AND gate AND203 includes six input terminals receiving FILT1_ DATA _ ALL _ i, AND one output terminal₁[j₁+5]、FILT1_DATA_ALL_i₁[j₁+6]、 FILT1_DATA_ALL_i₁[j₁+9]And FILT1_ DATA _ ALL _ i₁[j₁+10]Two other input terminals are respectively connected to the output terminal of the fourth NOT-gate NOT204 and the output terminal of the fifth NOT-gate NOT205, and the input terminal of the fourth NOT-gate NOT204 and the input terminal of the fifth NOT-gate NOT205 respectively receive FILT1_ DATA _ ALL i₁[j₁+7]And FILT1_DATA_ALL_i₁[j₁+8](ii) a The output terminal of the first AND gate AND201, the output terminal of the second AND gate AND202, AND the output terminal of the third AND gate AND203 are respectively connected to three input terminals of the first OR gate OR201, the output terminal of the first OR gate OR201 is electrically connected to the control signal input terminal sel of the first one-of-two selector MUX2201, AND outputs the second filter SET signal FILT2_ SET _ i₁[j₁]The control signal input terminal sel of the first alternative selector MUX2201, the DATA input terminal a and the DATA input terminal b of the first alternative selector MUX2201 receive FILT1_ DATA _ i₁[j₁]And 1.

As shown in FIG. 7, the fourth AND gate AND204 includes three inputs, one for receiving FILT1_ DATA _ ALL _ i, AND one output₁[j₁+8]Two other input terminals are respectively connected to the output terminal of the sixth NOT gate NOT206 and the output terminal of the seventh NOT gate NOT207, and the input terminal of the sixth NOT gate NOT206 and the input terminal of the seventh NOT gate NOT207 respectively receive FILT1_ DATA _ ALL _ i₁[j₁+7]、 FILT1_DATA_ALL_i₁[j₁+9](ii) a The fifth AND gate AND205 includes six input terminals receiving FILT1_ DATA _ ALL _ i, AND one output terminal₁[j₁+8]、FILT1_DATA_ALL_i₁[j₁+9]The other four input terminals are respectively connected to the output terminal of the eighth NOT gate NOT208, the output terminal of the ninth NOT gate NOT209, the output terminal of the tenth NOT gate NOT210 and the output terminal of the eleventh NOT gate NOT211, and the input terminals of the eighth NOT gate NOT208, the ninth NOT gate NOT209, the tenth NOT gate NOT210 and the eleventh NOT gate NOT211 respectively receive FILT1_ DATA _ ALL _ i₁[j₁+6]、 FILT1_DATA_ALL_i₁[j₁+7]、FILT1_DATA_ALL_i₁[j₁+10]And FILT1_ DATA _ ALL _ i₁ [j₁+11](ii) a The sixth AND gate AND206 includes six input terminals receiving FILT1_ DATA _ ALL _ i AND one output terminal₁[j₁+7]、FILT1_DATA_ALL_i₁[j₁+8]The other four input terminals are respectively connected with the output terminal of the twelfth NOT212, the output terminal of the thirteenth NOT213 and the output terminal of the fourteenth NOT214And an output of the fifteenth NOT gate NOT215, an input of the twelfth NOT gate NOT212, an input of the thirteenth NOT gate NOT213, an input of the fourteenth NOT gate NOT214, and an input of the fifteenth NOT gate NOT215 respectively receiving FILT1_ DATA _ ALL _ i₁[j₁+5]、FILT1_DATA_ALL_i₁[j₁+6]、 FILT1_DATA_ALL_i₁[j₁+9]And FILT1_ DATA _ ALL _ i₁[j₁+10](ii) a An output terminal of the fourth AND gate AND204, an output terminal of the fifth AND gate AND205, AND an output terminal of the sixth AND gate AND206 are respectively connected to three input terminals of the second OR gate OR202, an output terminal of the second OR gate OR202 is electrically connected to a control signal input terminal sel of the second one-of-two selector MUX2202, AND outputs a second filter reset signal FILT1_ CLR _ i₁[j₁]To the control signal input terminal sel of the second alternative selector MUX2202, the DATA input terminal a of the second alternative selector MUX2202 is connected to the output terminal out of the first alternative selector MUX2201, the DATA input terminal b is connected to 0, and the output terminal outputs FILT1_ DATA _ i₁[j₁]Filter result FILT2_ DATA _ i of₁[j₁]。

As shown in FIG. 12, in the present embodiment, the j-th₁Filter FILT2_ j₁FILT1_ DATA _ i that filters out spikes₁[j₁]The working principle is as follows: when FILT1_ DATA _ i₁[j₁]One of the cases one, two, three, four, five, six occurs, FILT1_ DATA _ i₁[j₁]A surge meeting the combination of (1, 0, 1), (0, 1, 0), (1, 1, 0, 0, 1, 1), (0, 0, 1, 1, 0, 0), SYNC _ DATA _ i₁[j₁]When it is a continuous burst, j₁Filter FILT1_ j₁FILT1_ DATA _ i₁[j₁]Inverted output, i.e. FILT1_ DATA _ i filtered out as glitches₁[j₁](ii) a When FILT1_ DATA _ i₁[j₁]Case seven occurs, FILT1_ DATA _ i₁[j₁]Not in surge, SYNC _ DATA _ i₁[j₁]When it is a single burst, the j-th₁Filter FILT2_ j₁Direct FILT1_ DATA _ i₁[j₁]And (6) outputting.

The first condition is as follows: FILT1_DATA_ALL_i₁[j₁+7]And FILT1_ DATA _ ALL _ i₁[j₁+9]Equal to 1, FILT1_ DATA _ ALL _ i₁[j₁+8]Equal to 0, FILT1_ DATA _ i₁[j₁]The front AND rear bit data form a (1, 0, 1) surge, the first AND gate AND201 outputs 1, AND the first OR gate OR201 outputs the second filtering setting signal FILT2_ SET _ i₁[j₁]Equal to 1, the first one-out selector MUX2201 selects the 1 output, the fourth AND gate AND204, the fifth AND gate AND205 AND the sixth AND gate AND206 output 0, AND the second filter reset signal FILT2_ SET _ i output by the second OR gate OR202₁[j₁]Equal to 0, the second alternative selector MUX2202 selects the 1 output by the first alternative selector MUX2201 as FILT1_ DATA _ i₁[j₁]Filter result FILT2_ DATA _ i of₁[j₁]Output, i.e. j₁Filter FILT2_ j₁The original FILT1_ DATA _ i₁[j₁]Changing from 0 to 1 output.

Case two: FILT1_ DATA _ ALL _ i₁[j₁+6]、FILT1_DATA_ALL_i₁[j₁+7]、 FILT1_DATA_ALL_i₁[j₁+10]、FILT1_DATA_ALL_i₁[j₁+11]Equal to 1, FILT1_ DATA _ ALL _ i₁[j₁+8]、FILT1_DATA_ALL_i₁[j₁+9]Equal to 0, FILT1_ DATA _ i₁[j₁]With its preceding AND following bit data components (1, 1, 0, 0, 1, 1) burst, the second AND gate AND202 outputs 1, AND the first OR gate OR201 outputs the first filter SET signal FILT1_ SET _ i₁[j₁]Equal to 1, the first one-out selector MUX2201 selects the 1 output, the fourth AND gate AND204, the fifth AND gate AND205 AND the sixth AND gate AND206 output 0, AND the first filter reset signal FILT2_ SET _ i output by the second OR gate OR202₁[j₁]Equal to 0, the second alternative selector MUX2202 selects the 1 output by the first alternative selector MUX2201 as FILT1_ DATA _ i₁[j₁]Filter result FILT2_ DATA _ i of₁[j₁]Output, i.e. j₁Filter FILT2_ j₁The original FILT1_ DATA _ i₁[j₁]Changing from 0 to 1 output.

Case three: FILT1_ DATA _ ALL _ i₁[j₁+5]、FILT1_DATA_ALL_i₁[j₁+6]、FILT1_DATA _ALL_i₁[j₁+9]、FILT1_DATA_ALL_i₁[j₁+10]Equal to 1, FILT1_ DATA _ ALL _ i₁[j₁+7] 、FILT1_DATA_ALL_i₁[j₁+8]Equal to 0, FILT1_ DATA _ i₁[j₁]With its front AND rear bit data forming (1, 1, 0, 0, 1, 1) glitch, the third AND gate AND203 outputs 1, the first OR gate OR201 outputs the second filter SET signal FILT2_ SET _ i₁[j₁]Equal to 1, the first one-out selector MUX2201 selects the 1 output, the fourth AND gate AND204, the fifth AND gate AND205 AND the sixth AND gate AND206 output 0, AND the second filter reset signal FILT2_ SET _ i output by the second OR gate OR202₁[j₁]Equal to 0, the second alternative selector MUX2202 selects the 1 output by the first alternative selector MUX2201 as FILT1_ DATA _ i₁[j₁]Filter result FILT2_ DATA _ i of₁[j₁]Output, i.e. j₁Filter FILT2_ j₁The original FILT1_ DATA _ i₁[j₁]Changing from 0 to 1 output.

Case four: FILT1_ DATA _ ALL _ i₁[j₁+7]And FILT1_ DATA _ ALL _ i₁[j₁+9]Equal to 0, FILT1_ DATA _ ALL _ i₁[j₁+8]Equal to 1, FILT1_ DATA _ i₁[j₁]The front AND rear bit data form a (0, 1, 0) burst, the fourth AND gate AND204 outputs 1, AND the second OR gate 0R202 outputs the second filtering setting signal FILT2_ SET _ i₁[j₁]Equal to 1, the second alternative selector MUX2202 selects 0 as FILT1_ DATA _ i₁[j₁]Filter result FILT2_ DATA _ i of₁[j₁]Output, i.e. j₁Filter FILT2_ j₁The original FILT1_ DATA _ i₁[j₁]Changing from 1 to 0 output.

Case five: FILT1_ DATA _ ALL _ i₁[j₁+6]、FILT1_DATA_ALL_i₁[j₁+7]、 FILT1_DATA_ALL_i₁[j₁+10]、FILT1_DATA_ALL_i₁[j₁+11]Equal to 0, FILT1_ DATA _ ALL _ i₁[j₁+8]、FILT1_DATA_ALL_i₁[j₁+9]Equal to 1, FILT1_ DATA _ i₁[j₁]With its front AND rear bit data forming (0, 0, 1, 1, 0, 0) glitch, the fifth AND gate AND205 outputs 1, the second or gate 0R202 outputs the second filter SET signal FILT2_ SET _ i₁[j₁]Equal to 1, the second alternative selector MUX2202 selects 0 as FILT1_ DATA _ i₁[j₁]Filter result FILT2_ DATA _ i of₁[j₁]Output, i.e. j₁Filter FILT2_ j₁The original FILT1_ DATA _ i₁[j₁]Changing from 1 to 0 output.

Case six: FILT1_ DATA _ ALL _ i₁[j₁+5]、FILT1_DATA_ALL_i₁[j₁+6]、 FILT1_DATA_ALL_i₁[j₁+9]、FILT1_DATA_ALL_i₁[j₁+10]Equal to 0, FILT1_ DATA _ ALL _ i₁[j₁+7]、FILT1_DATA_ALL_i₁[j₁+8]Equal to 1, FILT1_ DATA _ i₁[j₁]With its preceding and following bit data forming a (0, 0, 1, 1, 0, 0) burst, the second or gate 0R202 outputs the second filtered reset signal FILT2_ SET _ i₁[j₁]Equal to 1, the second alternative selector MUX2202 selects 0 as FILT1_ DATA _ i₁[j₁]Filter result FILT2_ DATA _ i of₁[j₁]Output, i.e. j₁Filter FILT2_ j₁The original FILT1_ DATA _ i₁[j₁]Changing from 1 to 0 output.

Case seven: FILT1_ DATA _ N [ j₁]Any one of the first, second, third, fourth, fifth AND sixth conditions does not occur, the outputs of the first AND gate AND201, the second AND gate AND202, the third AND gate AND203, the fourth AND gate AND204, the fifth AND gate AND205 AND the sixth AND gate AND206 are all equal to 0, AND the second filtering SET signal FILT2_ SET _ i output by the first OR gate OR201₁[j₁]And a second filtered reset signal FILT2_ SET _ i output from the second OR gate 0R202₁[j₁]Are all equal to 0, the first alternative selector MUX2201 selects FILT1_ DATA _ i₁[j₁]Output, the second alternative selector MUX2202 selects F output by the first alternative selector MUX2201ILT1_DATA_i₁[j₁]As FILT1_ DATA _ i₁[j₁]Filter result FILT2_ DATA _ i of₁[j₁]Output, i.e. j₁Filter FILT2_ j₁Direct FILT1_ DATA _ i₁[j₁]And (6) outputting.

As shown in fig. 8, the edge detection unit includes a first exclusive or gate XOR1, a second exclusive or gate XOR2, a third exclusive or gate XOR3, a fourth exclusive or gate XOR4, a fifth exclusive or gate XOR5, a sixth exclusive or gate XOR6, a seventh exclusive or gate XOR7, and an eighth exclusive or gate XOR 8; two input terminals of the first exclusive or gate XOR1 receive FILT2_ DATA _ i, respectively₁-1[7]、FILT2_DATA_i₁[0]And an output terminal outputting EDGE _ DATA _ i₁[0](ii) a Two input terminals of the second exclusive or gate XOR2 respectively receive FILT2_ DATA _ i₁[0]、FILT2_DATA_i₁[1]And an output terminal outputting EDGE _ DATA _ i₁[1](ii) a Two input terminals of the third exclusive or gate XOR3 respectively receive FILT2_ DATA _ i₁[1]、FILT2_DATA_i₁[2]And an output terminal outputting EDGE _ DATA _ i₁[2](ii) a Two input terminals of the fourth exclusive or gate XOR4 respectively receive FILT2_ DATA _ i₁[2]、FILT2_DATA_i₁[3]And an output terminal outputting EDGE _ DATA _ i₁[3](ii) a Two input terminals of the fifth exclusive or gate XOR5 receive FILT2_ DATA _ i, respectively₁[3]、FILT2_DATA_i₁[4]And an output terminal outputting EDGE _ DATA _ i₁[4](ii) a Two input terminals of the sixth exclusive or gate XOR6 receive FILT2_ DATA _ i, respectively₁[4]、FILT2_DATA_i₁[5]And an output terminal outputting EDGE _ DATA _ i₁[5](ii) a Two input terminals of the seventh exclusive or gate XOR7 receive FILT2_ DATA _ i, respectively₁[5]、FILT2_DATA_i₁[6]And an output terminal outputting EDGE _ DATA _ i₁[6](ii) a Two input terminals of the eighth XOR gate XOR8 receive FILT2_ DATA _ i, respectively₁[6]、FILT2_DATA_i₁[7]And an output terminal outputting EDGE _ DATA _ i₁[7]；EDGE_DATA_i₁[0]、EDGE_DATA_i₁[1]、EDGE_DATA_i₁[2] 、EDGE_DATA_i₁[3]、EDGE_DATA_i₁[4]、EDGE_DATA_i₁[5]、EDGE_DATA_i₁[6]、EDGE_DATA_i₁[7]Composing eight-bit EDGE detection DATA EDGE _ DATA _ i₁[7：0]Due to i₁… … N-1, N, N +1 … …, and so on, the EDGE detection unit receives the current beat of first filtered DATA FILT1_ DATA0, the previous beat of first filtered DATA FILT1_ DATA1, and outputs current beat of EDGE detection DATA EDGE _ DATA0 including … … EDGE _ DATA _ N-1[ 7: 0]、EDGE_DATA_N[7：0]、EDGE_DATA_N+1[7：0]……。

As shown in fig. 9, in the present embodiment, the data selection unit includes a data sampling circuit and an effective flag generation circuit; the data sampling circuit comprises a high-order sampling circuit and a low-order sampling circuit; the effective mark generating circuit comprises a high-order sampling effective mark generating circuit and a low-order sampling effective mark generating circuit; the high order sampling circuit receives FILT2_ DATA _ i₁[7：0]And EDGE _ DATA _ i₁+1[3：0]According to EDGE _ DATA _ i₁+1[3：0]For FILT2_ DATA _ i₁[7：0]High bit sampling, output FILT2_ DATA _ i₁[7：0]Is sampled to the high order DATA _ H _ i₁(ii) a The lower sampling circuit receives FILT2_ DATA _ i₁[7：0]And EDGE _ DATA _ i₁[7：4]According to EDGE _ DATA _ i₁[7：4]For FILT2_ DATA _ i₁[7：0]Sampling the low order bits and outputting FILT2_ DATA _ i₁[7：0]Low order sample DATA _ L _ i₁(ii) a High-order sampling valid flag generation circuit receives EDGE _ DATA _ i₁+1[7：0]、EDGE_DATA_i₁[7：0]And EDGE _ DATA _ i₁-1[7： 4]Judgment FILT2_ DATA _ i₁[7：0]If the high bit sample is valid, output FILT2_ DATA _ i₁[7：0]High order sample VALID flag VALID _ H _ i₁(ii) a The low-order sampling valid flag generation circuit receives EDGE _ DATA _ i₁+1[3：0]、EDGE_DATA_i₁[7：0]And EDGE _ DATA _ i₁-1[7：4]Judgment FILT2_ DATA _ i₁[7：0]If the lower sample is valid, output FILT2_ DATA _ i₁[7：0]VALID flag VALID _ H _ i of the lower sample₁(ii) a Due to i₁… … N-1, N, N +1 … …, and so on, the high order sampled DATA output by the high order sampling circuit includes … … DATA _ H _ N-1, DATA _ H _ N [ 7: 0]、DATA_H_N+1[7：0]… …, the lower sampled DATA output by the lower sampling circuit includes … … DATA _ L _ N-1, DATA _ L _ N [ 7: 0] 、DATA_L_N+1[7：0]… …, the high sample VALID flag output by the high sample VALID flag generation circuit includes … … VALID _ H _ N-1, VALID _ H _ N [ 7: 0]、VALID_H_N+1[7：0]… …, the low-order sampling VALID flag output by the low-order sampling VALID flag generation circuit includes … … VALID _ L _ N-1, VALID _ L _ N [ 7: 0]、VALID_L_N+1[7：0]……。

As shown in fig. 9, in the present embodiment, the high-order sampling circuit includes a high-order sampling address generating circuit and a first one-of-eight selector MUX81, and the low-order sampling circuit includes a low-order sampling address generating circuit and a second one-of-eight selector MUX 82; the high-order sampling address generation circuit receives EDGE _ DATA _ i₁+1[3：0]According to EDGE _ DATA _ i₁+1[3：0]Select FILT2_ DATA _ i₁[7：0]Is sampled to the high order sampling address ADR _ H _ i₁(ii) a The DATA input of the first one-of-eight selector MUX81 receives FILT2_ DATA _ i₁[7：0]The input end of the control signal receives a high-order sampling address ADR _ H _ i output by the high-order sampling address generating circuit₁At the upper sampling address ADR _ H _ i₁Selects FILT2_ DATA _ i under control of₁[7：4]As FILT2_ DATA _ i₁ [7：0]Is sampled to the high order DATA _ H _ i₁Outputting; the DATA input terminal of the low-order sampling address generation circuit receives EDGE _ DATA _ i₁[7：4]According to EDGE _ DATA _ i₁[7：4]Select FILT2_ DATA _ i₁[7：0]Low order sampling address ADR _ L _ i of₁(ii) a The DATA input of the second one-of-eight selector MUX82 receives FILT2_ DATA _ i₁[7：0]The input end of the control signal receives a low-order sampling address ADR _ L _ i output by the low-order sampling address generating circuit₁At the lower sample address ADR _ L _ i₁Selects FILT2_ DATA _ i under control of₁[3： 0]As FILT2_ DATA _ i₁[7：0]Low order sample DATA _ L _ i₁And (6) outputting.

In the present embodiment, the current beat EDGE detection DATA EDGE _ DATA0 is synchronized with the current beat second filtered DATA FILT2_ DATA0, and the previous beat EDGE detection DATA EDGE _ DATA1 is synchronized with the previous beat second filtered DATA FILT2_ DATA 1; the operation principle of the DATA selection unit sampling four phase clocks before the transition edge of the previous beat of the second filtered DATA FILT2_ DATA1 and selecting the last eight phase clocks of the last sampling point when no new transition edge is detected at any of twelve phase clocks after the transition edge is as follows:

if EDGE _ DATA _ i₁+1[j₂₁](

j

₂₁0, 1, 2, 3) equals 1, i.e., FILT2_ DATA _ i₁+1[j₂₁]Transition occurs, i.e. FILT2_ DATA _ i₁[7：4]The last four phase clocks have jump, the high-order sampling address generating circuit selects j_21m+4(j_21mIs in accordance with EDGE _ DATA _ i₁-1[j₂₁]J equal to 1₂₁Maximum value of) as the upper sampling address ADR _ H _ i₁The control signal input of the first one-of-eight selector MUX81 receives j_21mAfter +4, FILT2_ DATA _ i is selected₁[j_21m+4]As FILT _ DATA _ i₁[7：0]Is sampled to the high order DATA _ H _ i₁Output, i.e., high-order sampling address generation circuit selection FILT2_ DATA _ i₁-1[j₂₁]Four phase clocks before the last transition edge as FILT _ DATA _ i₁[7：0]High order sample point of (FILT 2_ DATA _ i)₁[j_21m+4]Belong to FILT _ DATA _ i₁[7：0]High bit DATA (i.e., FILT _ DATA _ i)₁[7：4]DATA in (c), otherwise, the high-order sampling address generation circuit generates the DATA according to EDGE _ DATA _ i₁[j₂₂](j₂₂0, 1, 2, 3), if EDGE _ DATA _ i₁[j₂₂]Equal to 1, high order sampling address generation circuit selects j_22m+4(j_22mIs in accordance with EDGE _ DATA _ i₁[j₂₂]J equal to 1₂₂Maximum value of) as the upper sampling address ADR _ H _ i₁The control signal input of the first one-of-eight selector MUX81 receives j_22mAfter +4, FILT2_ DATA _ i is selected₁[j_22m+4]As FILT2_ DATA _ i₁[7：0]Is sampled to the high order DATA _ H _ i₁Output, and so on, i.e. high order sampling address generation circuit at FILT2_ DATA _ i₁[7：4]When the last four phase clocks do not jump, the last eight phase clocks of the last sampling point are selected as the next sampling point, namely twelve phase clocks after the jump edge are not detectedWhen a new jump edge is detected, the high-order sampling circuit selects the last eight phase clocks of the last sampling point for sampling;

if (1) EDGE _ DATA _ i₁+1[j₂₁]Equal to 1, FILT2_ DATA _ i₁+1[3：0]In which a transition occurs, i.e., FILT2_ DATA _ i₁[7：0]At FILT2_ DATA _ i₁[7：4]Or, (2) EDGE _ DATA _ i₁[j₄₁]Is equal to 1 (j)₄₁0, 1, 2, 3, i.e. FILT2_ DATA _ i₁[3：0]In which a transition occurs, i.e., FILT2_ DATA _ i₁-1[7：0]At FILT2_ DATA _ i₁-1[7：4]) And EDGE _ DATA _ i₁[7：4]Are all equal to 0 (i.e., FILT2_ DATA _ i)₁[7：4]No transition occurs), and EDGE _ DATA _ i₁+1[j₄₁+4：0]Are all equal to 0, i.e., FILT2_ DATA _ i₁[3：0]No transition occurs within twelve phase clocks after the last transition, and the high-order sample effectively identifies FILT2_ DATA _ i output by the circuit₁[7：0]High order sample VALID flag VALID _ DATA _ i₁Are all valid, i.e., FILT2_ DATA _ i₁+1[3：0]A transition occurs, or, FILT _ DATA _ i₁[3：0]Twelve phase clocks with no new transition after the transition, FILT2_ DATA _ i₁[7：0]All high sampling is effective, combined with high sampling address generation circuit at FILT2_ DATA _ i₁+1[3：0]When the jump occurs, j at the first four clock phases of the jump edge is selected_21m+4 as FILT2_ DATA _ i₁[7：0]Is sampled to the high order sampling address ADR _ H _ i₁And, the high-order sampling address generating circuit is in FILT2_ DATA _ i₁+1[3：0]When no jump occurs, the next sampling point is selected from the eight last phase clocks of the previous sampling point, and the DATA storage unit is found to be FILT2_ DATA _ i₁+1[3：0]When a transition occurs, DATA FILT2_ DATA _ i at the first four clock phases of the output transition edge₁[j_21m+4]As FILT2_ DATA _ i₁[7：0]At FILT _ DATA _ i₁[3：0]When twelve phase clocks do not have new transitions after the transition, DATA FILT2_ DATA _ i at eight phase clocks after the output of the last sample point₁[j_22m+4]As FILT2_ DATA _ i₁[7：0]The high order sample data of (1);

if EDGE _ DATA _ i₁[j₃₁]Is equal to 1 (j)₃₁4, 5, 6, 7), i.e., FILT2_ DATA _ i₁[j₃₁]Transition occurs, i.e. FILT2_ DATA _ i₁[7：0]At FILT2_ DATA _ i₁[3：0]Selection j of low-order sampling address generation circuit_31m-4(j_31mIs in accordance with EDGE _ DATA _ i₁-1[j₃₁]J equal to 1₃₁Maximum value of) as FILT2_ DATA _ i₁[7：0]Low order sampling address ADR _ L _ i of₁The control signal input of the second one-of-eight selector MUX82 receives j_31mAfter-4, select FILT _ DATA _ i₁[j_31m-4]As FILT2_ DATA _ i₁[7：0]I.e., the lower sampling address generation circuit selects FILT2_ DATA _ i₁[7：4]Four phase clocks before the last transition edge as FILT _ DATA _ i₁[7：0]The lower sample point of (FILT 2_ DATA _ i)₁[j_31m-4]Belong to FILT _ DATA _ i₁[7：0]Low bit DATA (i.e., FILT _ DATA _ i)₁[3：0]DATA in) otherwise, the lower sampling circuit is according to EDGE _ DATA _ i₁-1[j₃₂]Make a selection if EDGE _ DATA _ i₁-1[j₃₂]Is equal to 1 (j)₃₂4, 5, 6, 7), the lower sampling circuit selects j_32m-4(j_32mIs in accordance with EDGE _ DATA _ i₁-1[j₃₂]J equal to 1₃₂Maximum value of) as FILT2_ DATA _ i₁[7：0]Low order sampling address ADR _ L _ i of₁The control signal input of the second one-of-eight selector MUX82 receives j_32mAfter-4, select FILT _ DATA _ i₁[j_32m-4]As FILT2_ DATA _ i₁[7：0]And so on, i.e. the lower sampled address generating circuit is in FILT2_ DATA _ i₁[7：4]When jumping does not occur, the next eight phase clocks of the last sampling point are selected as the next sampling point, namely when a new jumping edge is not detected at any of the twelve phase clocks after the jumping edge, the next eight phase clocks of the last sampling point are selected by the low-order sampling circuit for sampling;

if (1)EDGE_DATA_i₁[j₃₁]Equal to 1, FILT2_ DATA _ i₁[7：4]Transition occurs, i.e. FILT2_ DATA _ i₁[7：0]At FILT2_ DATA _ i₁[3：0]Or, (2) EDGE _ DATA _ i₁-1 [j₄₂]Is equal to 1 (j)₄₂4, 5, 6, 7, i.e. FILT2_ DATA _ i₁-1[7：4]Transition occurred, FILT2_ DATA i₁-1[7：0]At FILT2_ DATA _ i₁-1[3：0]) And EDGE _ DATA _ i₁[7：0]Are all equal to 0 (i.e., EDGE _ DATA _ i)₁[7：0]No transition occurs), and EDGE _ DATA _ i₁+1[j₄₂：0]Are all equal to, i.e., FILT _ DATA _ i₁-1[7：4]No jump occurs in twelve phase clocks after the last jump, and the low-bit sampling VALID identifier output by the low-bit sampling VALID identifier circuit is VALID _ DATA _ i₁Are all valid, i.e., if FILT2_ DATA _ i₁[7：4]A transition occurs, or, FILT _ DATA _ i₁-1[7：4]Twelve phase clocks with no new transition after the transition, FILT2_ DATA _ i₁[7：0]All low-order sampling is effective, combined with low-order sampling address generation circuit at FILT2_ DATA _ i₁[7：4]When the jump occurs, j at the first four clock phases of the jump edge is selected_31m+4 as the lower sample address ADR _ L _ i₁And, the lower sampling address generating circuit is in FILT2_ DATA _ i₁[7：4]When no jump occurs, the next sampling point is selected from the eight last phase clocks of the previous sampling point, and the DATA storage unit is found to be FILT2_ DATA _ i₁[7：4]The DATA FILT2_ DATA _ i at the first four clock phases of the transition edge is output when the latter four phase clocks transition₁[j_31m-4]As FILT2_ DATA _ i₁[7：0]At FILT _ DATA _ i₁-1[7：4]When twelve phase clocks do not have new transitions after the transition, DATA FILT2_ DATA _ i at eight phase clocks after the output of the last sample point₁[j_32m-4]As FILT2_ DATA _ i₁[7：0]The lower sampled data.

As shown in FIG. 10, in the present embodiment, the high-order sampling address generating circuit includes a third alternative selector MUX203, a fourth alternative selector MUX204,A fifth either selector MUX205, a sixth either selector MUX206, and a third register REG 3; the control signal input sel of the third alternative selector MUX203 receives EDGE _ DATA _ i₁+1[0]The DATA input terminal a receives the previous beat DATA FILT2_ DATA _ i fed back from the third register REG3₁-1[7：0]Is sampled to the high order sampling address ADR _ H _ i₁1, the data input b receives 4, and the output is connected to the data input a of the fourth alternative selector MUX 204; the control signal input of the fourth alternative selector MUX204 receives EDGE _ DATA _ i₁+1[1]The data input end b receives 5, and the output end is connected with the data input end a of the fifth alternative selector MUX 205; the control signal input of the fifth alternative selector MUX205 receives EDGE _ DATA _ i₁+1[2]The data input end b receives 6, and the output end is connected with the data input end a of the sixth alternative selector MUX 206; the control signal input of the sixth alternative selector MUX206 receives EDGE _ DATA _ i₁+1[3]DATA input terminal b receives 7, and output terminal outputs FILT2_ DATA _ i₁[7：0]Is sampled to the high order sampling address ADR _ H _ i₁And FILT2_ DATA _ i₁[7：0]Is sampled to the high order sampling address ADR _ H _ i₁To the third register REG3, since i₁… … N-1, N, N +1 … …, and so on, it can be seen that the high-order sampling address generation circuit receives … … EDGE _ DATA _ N-1[ 3: 0]、 EDGE_DATA_N+1[3：0]、EDGE_DATA_N+1[3：0]… …, the ADR _ H with high-order sampling address outputted to the third register REG3 includes … … ADR _ H _ N-1, ADR _ H _ N, ADR _ H _ N +1 … …, the third register REG3 outputs the high-order sampling address of … … ADR _ H _ N-1, ADR _ H _ N, ADR _ H _ N +1 … … to the third alternative selector MUX203 after registering one beat (i.e. lagging one beat), the third register REG3 outputs the high-order sampling address ADR _ H _ i₁Is fed back to the DATA input a of the third alternative selector MUX203 as the second filtered DATA FILT2_ DATA _ i of the next beat of the generated second filtered DATA₁+1[7：0]Is sampled to the high order sampling address ADR _ H _ i₁An input value of + 1.

As shown in FIG. 10, the low-order sampling address generating circuit includes a seventh alternative selector MUX207, an eighth alternative selector MUX208, a ninth alternative selector MUX209, and a twelfth alternative selector MUX210 and a fourth register REG 4; the control signal input sel of the seventh alternative selector MUX207 receives EDGE _ DATA _ i₁[4]The DATA input terminal a receives the previous beat DATA FILT2_ DATA _ i fed back from the fourth register REG4₁-1[7：0]Low order sampling address ADR _ L _ i of₁1, the data input b receives 0, and the output is connected to the data input a of the eighth either selector MUX 208; the control signal input of the eighth either-or selector MUX208 receives EDGE _ DATA _ i₁[5]The data input end b receives 1, and the output end is connected with the data input end a of the ninth alternative selector MUX 209; the control signal input of the ninth alternative selector MUX209 receives EDGE _ DATA _ i₁[6]The data input end b receives 2, and the output end is connected with the data input end a of the twelfth one-of-choice selector MUX 210; the control signal input of the twelfth one-of-choice selector MUX210 receives EDGE _ DATA _ i₁[7]DATA input terminal b receives 3, and output terminal outputs FILT2_ DATA _ i₁[7：0]Low order sampling address ADR _ L _ i of₁And FILT2_ DATA _ i₁[7：0]Low order sampling address ADR _ L _ i of₁To the fourth register REG4, since i₁… … N-1, N, N +1 … …, and so on, it can be seen that the lower sampling address generation circuit receives … … EDGE _ DATA _ N-1[ 7: 4]、EDGE_DATA_N+1[7：4]、EDGE_ DATA_N+1[7：4]… …, the ADR _ L of the low-order sampling address outputted to the fourth register REG4 includes … … ADR _ L _ N-1, ADR _ L _ N, ADR _ L _ N +1 … …, the fourth register REG4 outputs the low-order sampling address of the previous beat to the seventh alternative selector MUX207 after registering … … ADR _ L _ N-1, ADR _ L _ N, ADR _ L _ N +1 … … for one beat (i.e. lagging by one beat), the fourth register REG4 feeds back the low-order sampling address to the DATA input terminal a of the seventh alternative selector MUX207 as the generated DATA of the next beat, FILT2_ DATA _ i₁+1[7：0]Low order sampling address ADR _ i of₁_i₁An input value of + 1.

In this embodiment, since the first filter circuit and the second filter circuit filter out … … SYNC _ DATA _ N-1[ 7: 0]、SYNC_DATA_N[7：0]、SYNC_DATA_N+1[7：0]… …, … … FILT2_ DATA _ N-1[ 7: 0]、FILT2_DATA_N[7：0]、FILT2_DATA_ N+1[7：0]… … at most one transition occurs for four consecutive clock phases, EDGE _ DATA _ i₁+1[0]、 EDGE_DATA_i₁+1[1]、EDGE_DATA_i₁+1[2]、EDGE_DATA_i₁+1[3]Of which at most one has a value of 1, i.e. j_21mEqual to EDGE _ DATA _ i compliance₁+1[j₂₁]J1 ═ 1₂₁；EDGE_DATA_i₁[4]、 EDGE_DATA_i₁[5]、EDGE_DATA_i₁[6]、EDGE_DATA_i₁[7]Of which at most one has a value of 1, i.e. j_31mEqual to EDGE _ DATA _ i compliance₁[j₃₁]J1 ═ 1₃₁，EDGE_DATA_i₁[0]、EDGE_DATA_i₁[1]、 EDGE_DATA_i₁[2]、EDGE_DATA_i₁[3]At most one value of 1, EDGE _ DATA _ i₁-1[4]、 EDGE_DATA_i₁-1[5]、EDGE_DATA_i₁-1[6]、EDGE_DATA_i₁-1[7]Of which at most one has a value of 1.

In this embodiment, the operation principle of the high-order sampling address generation circuit is as follows: when EDGE _ DATA _ i₁+1[0]Equal to 1, EDGE _ DATA _ i₁+1[1]、EDGE_DATA_i₁+1[2]、 EDGE_DATA_i₁+1[3]Are all equal to 0, i.e., FILT2_ DATA _ i₁+1[0]Transition occurs, FILT2_ DATA _ i₁+1[1]、FILT2_DATA_i₁+1[2]、FILT2_DATA_i₁+1[3]When no transition occurs, the fifth either-or selector MUX205 selects the 4 output, the fourth either-or selector MUX204 selects the 4 output of the fifth either-or selector MUX205, and so on, the fifth either-or selector MUX205 selects the 4 output of the fourth either-or selector MUX204, and the sixth either-or selector MUX206 selects the 4 output of the fifth either-or selector MUX205 as the second filtered DATA FILT2_ DATA _ i₁[7：0]Is sampled to the high order sampling address ADR _ H _ i₁Outputting; the control signal input sel of the first one-of-eight selector MUX81 receives 4, selects FILT2_ DATA _ i₁[4]As FILT2_ DATA _ i₁[7：0]Is sampled to the high order DATA _ H _ i₁Output, FILT2_ DATA _ i₁[4]Is located in FILT2_ DATA _ i₁+1[0]The first four phases; and so on, when EDGE _ DATA _ i₁+1[1]Equal to 1, EDGE _ DATA _ i₁+1[0]、EDGE_DATA_i₁+1[2]、 EDGE_DATA_i₁+1[3]All equal to 0, the sixth alternative selector MUX206 selects 5 as the second filtered DATA FILT2_ DATA _ i₁[7：0]Is sampled to the high order sampling address ADR _ H _ i₁Outputting; the control signal input sel of the first one-of-eight selector MUX81 receives 5 and selects FILT2_ DATA _ i₁[5]As FILT2_ DATA _ i₁[7：0]Is sampled to the high order DATA _ H _ i₁Output, FILT2_ DATA _ i₁[5]Is located in FILT2_ DATA _ i₁+1[1]The first four phases; and so on, when EDGE _ DATA _ i₁+1[2]Equal to 1, EDGE _ DATA _ i₁+1[0]、EDGE_DATA_i₁+1[1]、EDGE_DATA_i₁+1[3]All equal to 0, the sixth alternative selector MUX206 selects 6 as the second filtered DATA FILT2_ DATA _ i₁[7：0]Is sampled to the high order sampling address ADR _ H _ i₁Outputting; the control signal input sel of the first one-of-eight selector MUX81 receives 6 and selects FILT2_ DATA _ i₁[6]As FILT2_ DATA _ i₁[7：0]Is sampled to the high order DATA _ H _ i₁Output, FILT2_ DATA _ i₁[6]Is located in FILT2_ DATA _ i₁+1[2]The first four phases; and so on, when EDGE _ DATA _ i₁+1[3]Equal to 1, EDGE _ DATA _ i₁+1[0]、EDGE_DATA_i₁+1[1]、EDGE_DATA i₁+1[2]All equal to 0, the sixth alternative selector MUX206 selects 7 as the second filtered DATA FILT2_ DATA _ i₁[7：0]Is sampled to the high order sampling address ADR _ H _ i₁Outputting; the control signal input sel of the first one-of-eight selector MUX81 receives 7 and selects FILT2_ DATA _ i₁[7]As FILT2_ DATA _ i₁[7：0]Is sampled to the high order DATA _ H _ i₁Output, FILT2_ DATA _ i₁[7]Is located in FILT2_ DATA _ i₁+1 [3]The first four phases; when EDGE _ DATA _ i₁[4]、EDGE_DATA_i₁[5]、EDGE_DATA_i₁[6]、 EDGE_DATA_i₁[7]All equal to 0, the sixth alternative selector MUX206 selects FILT2_ DATA _ i₁-1[7：0]Is sampled to the high order sampling address ADR _ H _ i₁-1 as FILT2_ DATA _ i₁[7：0]Is sampled to the high order sampling address ADR _ H _ i₁And (6) outputting.

In the present embodiment, the lower orderThe working principle of the sampling address generating circuit is as follows: when EDGE _ DATA _ i₁[4]Equal to 1, EDGE _ DATA _ i₁[5]、EDGE_DATA_i₁[6]、EDGE_DATA_i₁[7]Are all equal to 0, i.e., FILT2_ DATA _ i₁[4]Transition occurs, FILT2_ DATA _ i₁[5]、FILT2_DATA_i₁[6]、FILT2_DATA_i₁[7]When no transition occurs, the seventh either-or selector MUX207 selects the 0 output, the eighth either-or selector MUX208 selects the 0 output of the seventh either-or selector MUX207 output, and so on, the ninth either-or selector MUX209 selects the 0 output of the eighth either-or selector MUX208 output, and the twelfth either-or selector MUX210 selects the 0 output of the ninth either-or selector MUX209 as the second filtered DATA FILT2_ DATA _ i₁[7：0]Low order sampling address ADR _ L _ i of₁Outputting; after the control signal input sel of the second one-out-of-eight selector MUX82 receives 0, it selects FILT2_ DATA _ i₁[0]As FILT2_ DATA _ i₁[7：0]Low order sample DATA _ L _ i₁Output, FILT2_ DATA _ i₁[0]Is located in FILT2_ DATA _ i₁[4]The first four phases; and so on, when EDGE _ DATA _ i₁[5]Equal to 1, EDGE _ DATA _ i₁[4]、EDGE_DATA_i₁[6]、 EDGE_DATA_i₁[7]All equal to 0, the twelfth one-of-one selector MUX210 selects 1 as the second filtered DATA FILT2_ DATA _ i₁[7：0]Low order sampling address ADR _ L _ i of₁Outputting; after the control signal input sel of the second one-out-of-eight selector MUX82 receives 1, the FILT2_ DATA _ i is selected₁[1]As FILT2_ DATA _ i₁ [7：0]Low order sample DATA _ L _ i₁Output, FILT2_ DATA _ i₁[1]Is located in FILT2_ DATA _ i₁[5]The first four phases; when EDGE _ DATA _ i₁[6]Equal to 1, EDGE _ DATA _ i₁[4]、EDGE_DATA_i₁[5]、 EDGE_DATA_i₁[7]All equal to 0, the twelfth one-of-one selector MUX210 selects 2 as the second filtered DATA FILT2_ DATA _ i₁[7：0]Low order sampling address ADR _ L _ i of₁Outputting; after the control signal input sel of the second one-of-eight selector MUX82 receives 2, the FILT2_ DATA _ i is selected₁[2]As FILT2_ DATA _ i₁ [7：0]Low order sampled data ofDATA_L_i₁Output, FILT2_ DATA _ i₁[2]Is located in FILT2_ DATA _ i₁[6]The first four phases; when EDGE _ DATA _ i₁[7]Equal to 1, EDGE _ DATA _ i₁[4]、EDGE_DATA_i₁[5]、 EDGE_DATA_i₁[6]Are all equal to 0, the twelfth one-of-one selector MUX210 selects 3 as the second filtered DATA FILT2_ DATA _ i₁[7：0]Low order sampling address ADR _ L _ i of₁Outputting; the control signal input sel of the second one-of-eight selector MUX82 receives 3 and selects FILT2_ DATA _ i₁[3]As FILT2_ DATA _ i₁ [7：0]Low order sample DATA _ L _ i₁Output, FILT2_ DATA _ i₁[3]Is located in FILT2_ DATA _ i₁[7]The first four phases; when EDGE _ DATA _ i₁[4]、EDGE_DATA_i₁[5]、EDGE_DATA_i₁[6]、EDGE_ DATA_i₁[7]All equal to 0, the sixth alternative selector MUX206 selects FILT2_ DATA _ i₁-1[7：0]Low order sampling address ADR _ H _ i of (a)₁-1 as FILT2_ DATA _ i₁[7：0]Low order sampling address ADR _ H _ i of (a)₁And (6) outputting.

11-1, 11-2, AND 11-3, the valid flag generating circuit includes an eleventh one-out selector MUX211, a twelfth one-out selector MUX212, a thirteenth one-out selector MUX213, a fourteenth one-out selector MUX214, a fifteenth one-out selector MUX215, a sixteenth one-out selector MUX216, a seventeenth one-out selector MUX217, an eighteenth one-out selector MUX218, a fifth register REG5, a first numerical comparator NC1, a second numerical comparator NC2, a third numerical comparator NC3, a fourth numerical comparator NC4, a first NOR gate NOR1, a second NOR gate NOR2, a third NOR gate NOR3, a fourth NOR gate 4, a fifth NOR gate 5, a seventh AND gate 07, an eighth AND08, a ninth AND gate 09, a tenth AND gate 10, an eleventh AND gate 10, a third NOR gate 11, a fifth NOR gate 3, a fifth NOR gate 638, a fifth NOR gate NC 638, a fifth numerical comparator NC 638, a sixteenth OR 638, a fifth numerical comparator NC 638, a sixth OR, A sixth numerical comparator NC6, a seventh numerical comparator NC7, an eighth numerical comparator NC8, a sixteenth NOR gate NOT16, a sixth NOR gate NOR6, a seventh NOR gate NOR7, an eighth NOR gate NOR8, a ninth NOR gate NOR9, a twelfth AND gate 12, a thirteenth AND gate 13, a fourteenth AND gate 14, a fifteenth AND gate 15, a sixteenth AND gate 16, a sixth OR gate OR6, a seventh OR gate OR7, AND an eighth OR gate OR 8; an eleventh two-way selector MUX211, a twelfth two-way selector MUX212, a thirteenth two-way selector MUX213, a fourteenth two-way selector MUX214, a fifteenth two-way selector MUX215, a sixteenth two-way selector MUX216, a seventeenth two-way selector MUX217, an eighteenth two-way selector MUX218, a fifth register REG5, a first numerical comparator NC1, a second numerical comparator NC2, a third numerical comparator NC3, a fourth numerical comparator NC4, a first NOR gate NOR1, a second NOR gate NOR2, a third NOR gate NOR3, a fourth NOR gate NOR4, a fifth NOR gate NOR5, a seventh AND gate 07, an eighth AND gate 08, a ninth AND gate 09, a tenth AND gate 10, an eleventh AND gate 11, a third OR gate R3, a fourth OR gate OR4, AND a fifth OR gate OR5 to form a bit-up sampling circuit; an eleventh two-way selector MUX211, a twelfth two-way selector MUX212, a thirteenth two-way selector MUX213, a fourteenth two-way selector MUX214, a fifteenth two-way selector MUX215, a sixteenth two-way selector MUX216, a seventeenth two-way selector MUX217, an eighteenth two-way selector MUX218, a fifth register REG5, a fifth numerical comparator NC5, a sixth numerical comparator NC6, a seventh numerical comparator NC7, an eighth numerical comparator NC8, a sixteenth NOT gate NOT16, a sixth NOR gate NOR6, a seventh NOR gate NOR7, an eighth NOR gate NOR8, a ninth NOR gate NOR9, a twelfth AND gate 12, a thirteenth AND gate 13, a fourteenth AND gate 14, a fifteenth AND gate 15, a sixteenth AND gate 16, a sixth OR gate OR6, a seventh OR gate OR7, AND an eighth OR gate OR8 form a low bit sampling circuit.

In this embodiment, all the numerical comparators are one-bit numerical comparators, and when the two input values are equal, the numerical comparator outputs 1, otherwise, the numerical comparator outputs 0; NC is an abbreviation for numerical comparator, representing a numerical comparator.

As shown in FIG. 11-1, the control signal input sel of the eleventh alternative selector MUX211 receives EDGE _ DATA _ i₁-1[4]The data input terminal a receives the feedback of the fifth register REG5The previous beat DATA FILT2_ DATA _ i₁-2[7：0]ADR _ ALL _ i as the last sampling address₁2, the data input b receives 0, and the output is connected to the data input a of the twelfth alternative selector MUX 212; the control signal input of the twelfth alternative selector MUX212 receives EDGE _ DATA _ i₁-1[5]The data input end b receives 1, and the output end is connected with the data input end a of the thirteenth alternative selector MUX 213; the control signal input of the thirteenth alternative selector MUX213 receives EDGE _ DATA _ i₁-1[6]The data input end b receives 2, and the output end is connected with the data input end a of the fourteenth alternative selector MUX 214; the control signal input of the fourteenth either-or selector MUX214 receives EDGE _ DATA _ i₁-1[7]The data input end b receives 3, and the output end is connected with the data input end a of the fifteenth alternative selector MUX 215; the control signal input of the fifteenth alternative selector MUX215 receives EDGE _ DATA _ i₁[0]The data input end b receives 4, and the output end is connected with the data input end a of the sixteenth alternative selector MUX 216; the control signal input of the sixteenth either selector MUX216 receives EDGE _ DATA _ i₁[1]The data input b receives 5, and the output is connected to the data input a of the nineteenth alternative selector MUX 218; the control signal input of the seventeenth alternative selector MUX217 receives EDGE _ DATA _ i₁[2]The data input b receives 6, and the output is connected to the input a of the eighteenth alternative selector MUX 218; the control signal input of the eighteenth either-or selector MUX218 receives EDGE _ DATA _ i₁[3]A DATA input terminal b receiving 7, and an output terminal outputting second filtered DATA FILT2_ DATA _ i₁-1[7：0]ADR _ ALL _ i as the last sampling address₁-1 and second filtered DATA FILT2_ DATA _ i₁+1[7：0]ADR _ ALL _ i as the last sampling address₁+1 is sent to the fifth register REG5, since i₁… … N-1, N, N +1 … …, and so on, it can be seen that the last sampling address outputted from the valid flag generating circuit to the fifth register REG5 includes … … ADR _ ALL _ N-1, ADR _ ALL _ N, ADR _ ALL _ N +1 … …, and the fifth register REG5 outputs … … ADR _ ALL _ N-1, ADR _ ALL _ N, ADR _ ALL _ N +1 … … after registering one beat (i.e. lagging one beat), and outputting the last beatSampling the address to the fifth register REG 5; the fifth register REG5 registers FILT2_ DATA _ i₁-1[7：0]ADR _ ALL _ i as the last sampling address₁-1 is fed back to the DATA input a of the eleventh alternative selector MUX211 as the generation FILT2_ DATA _ i₁[7：0]ADR _ ALL _ i as the last sampling address₁The input value of (1).

As shown in FIG. 11-2, an input terminal of the first numerical comparator NC1, an input terminal of the second numerical comparator NC2, an input terminal of the third numerical comparator NC3, and an input terminal of the fourth numerical comparator NC4 all receive FILT2_ DATA _ i₁-1[7：0]ADR _ ALL _ i as the last sampling address₁-1, the other input of the first numerical comparator NC1, the other input of the second numerical comparator NC2, the other input of the third numerical comparator NC3 and the other input of the fourth numerical comparator NC4 receiving 4, 5, 6 and 7, respectively; five input terminals of the first NOR gate NOR1 receive EDGE _ DATA _ i, respectively₁+1 [0]、EDGE_DATA_i₁+1[1]、EDGE_DATA_i₁+1[2]、EDGE_DATA_i₁+1[3]、EDGE_DATA i₁+1[4](ii) a Two input ends of the seventh AND gate AND07 are respectively connected with the output end of the first numerical comparator NC1 AND the output end of the first NOR gate NOR 1; six input terminals of the second NOR gate NOR2 receive EDGE _ DATA _ i, respectively₁+1[0]、EDGE_DATA_i₁+1[1]、EDGE_DATA_i₁+1[2]、EDGE_DATA_ i₁+1[3]、EDGE_DATA_i₁+1[4]、EDGE_DATA_i₁+1[5](ii) a Two input ends of the eighth AND gate AND08 are respectively connected with the output end of the second numerical comparator NC2 AND the output end of the second NOR gate NOR 2; seven inputs of the third NOR gate NOR3 receive EDGE _ DATA _ i, respectively₁+1[0]、EDGE_DATA_ i₁+1[1]、EDGE_DATA_i₁+1[2]、EDGE_DATA_i₁+1[3]、EDGE_DATA_i₁+1[4]、 EDGE_DATA_i₁+1[5]、EDGE_DATA_i₁+1[6](ii) a Two input ends of the ninth AND-gate AND09 are respectively connected with the output end of the third numerical comparator NC3 AND the output end of the third NOR-gate NOR 3; eight input terminals of the fourth NOR gate NOR4 receive EDGE detection DATA EDGE _ DATA _ i, respectively₁+1[0]、EDGE_DATA_ i₁+1[1]、EDGE_DATA_i₁+1[2]、EDGE_DATA_i₁+1[3]、EDGE_DATA_i₁+1[4]、 EDGE_DATA_i₁+1[5]、EDGE_DATA_i₁+1[6]、EDGE_DATA_i₁+1[7](ii) a Two input ends of the fourth AND gate AND204 are respectively connected with the output end of the fourth numerical comparator NC4 AND the output end of the fourth NOR gate NOR 4; four input terminals of the fifth nor gate OR5 are connected to the output terminal of the seventh AND gate AND07, the output terminal of the eighth AND gate AND08, the output terminal of the ninth AND gate AND09, AND the output terminal of the tenth AND gate AND204, respectively; four input terminals of the fifth NOR gate NOR5 receive EDGE _ DATA _ i, respectively₁[4]、 EDGE_DATA_i₁[5]、EDGE_DATA_i₁[6]、EDGE_DATA_i₁[7](ii) a Two input terminals of the eleventh AND gate AND11 are respectively connected with the output terminal of the third OR gate OR3 AND the output terminal of the fifth NOR gate NOR 5; the four inputs of the fourth OR gate OR4 receive EDGE _ DATA _ i, respectively₁+1[0]、EDGE_DATA_i₁+1[1]、 EDGE_DATA_i₁+1[2]、EDGE_DATA_i₁+1[3](ii) a Two input terminals of the fifth OR gate OR5 are connected to an output terminal of the eleventh AND gate AND11 AND an output terminal of the fourth OR gate OR4, respectively, AND the output terminal outputs FILT2_ DATA _ i₁[7：0]High order sample VALID flag VALID _ H _ i₁。

As shown in FIGS. 11-3, an input of the fifth numerical comparator NC5, an input of the sixth numerical comparator NC6, an input of the seventh numerical comparator NC7, and an input of the eighth numerical comparator NC8 all receive FILT2_ DATA _ i₁-1[7：0]ADR _ ALL _ i as the last sampling address₁-1, the other input of the fifth numerical comparator NC5, the other input of the sixth numerical comparator NC6, the other input of the seventh numerical comparator NC7 and the other input of the eighth numerical comparator NC8 receiving 0, 1, 2 and 3, respectively; the input of the sixteenth NOT16 receives EDGE _ DATA _ i₁+1[0](ii) a Two input ends of the twelfth AND gate AND12 are respectively connected with an output end of the fifth numerical comparator NC5 AND an output end of the sixteenth NOT 16; two input terminals of the sixth NOR gate NOR6 receive EDGE _ DATA _ i, respectively₁+1[0]、EDGE_DATA_i₁+1[1](ii) a First, theTwo input ends of the thirteen AND gate AND13 are respectively connected with an output end of the sixth numerical comparator NC6 AND an output end of the sixth NOR gate NOR 6; three input terminals of the seventh NOR gate NOR7 receive EDGE _ DATA _ i, respectively₁+1[0]、EDGE_DATA_i₁+1[1]、EDGE_DATA_ i₁+1[2](ii) a Two input ends of the fourteenth AND gate AND14 are respectively connected with the output end of the seventh numerical comparator NC7 AND the output end of the seventh NOR gate NOR 7; the four input terminals of the eighth NOR gate NOR8 receive EDGE _ DATA _ i, respectively₁+1[0]、EDGE_DATA_i₁+1[1]、EDGE_DATA_i₁+1[2]、EDGE_DATA_ i₁+1[3](ii) a Two input ends of the fifteenth AND gate AND15 are respectively connected with the output end of the eighth numerical comparator NC8 AND the output end of the eighth NOR gate NOR 8; four input terminals of the sixth OR gate OR6 are connected to the output terminal of the twelfth AND gate AND12, the output terminal of the thirteenth AND gate AND13, the output terminal of the fourteenth AND gate AND14, AND the output terminal of the fifteenth AND gate AND15, respectively; eight input terminals of the ninth NOR gate NOR9 receive EDGE _ DATA _ i, respectively₁[0]、EDGE_DATA_i₁[1]、EDGE_DATA_i₁[2]、EDGE_DATA_i₁[3]、 EDGE_DATA_i₁[4]、EDGE_DATA_i₁[5]、EDGE_DATA_i₁[6]、EDGE_DATA_i₁[7](ii) a Two input terminals of the sixteenth AND gate AND16 are respectively connected to the output terminal of the sixth OR gate OR6 AND the output terminal of the ninth NOR gate NOR 9; the four input terminals of the seventh OR gate OR7 receive EDGE _ DATA _ i, respectively₁[4]、 EDGE_DATA_i₁[5]、EDGE_DATA_i₁[6]、EDGE_DATA_i₁[7]Connecting; two input terminals of the eighth OR gate OR8 are connected to an output terminal of the sixteenth AND gate AND16 AND an output terminal of the seventh OR gate OR7, respectively, AND the output terminal outputs FILT2_ DATA _ i₁[7：0]VALID flag VALID _ L _ i of the lower sample₁。

As shown in fig. 12, in the present embodiment, the operation principle of the high-order sampling valid flag generating circuit is as follows:

as shown in FIG. 11-1, when EDGE _ DATA _ i₁[0]Equal to 1, EDGE _ DATA _ i₁[1]、EDGE_DATA_ i₁[2]、EDGE_DATA_i₁[3]Are all equal to 0, i.e., FILT2_ DATA _ i₁[0]Jump occurs， FILT2_DATA_i₁[1]、FILT2_DATA_i₁[2]、FILT2_DATA_i₁[3]When no transition occurs, the eighteenth alternative selector MUX218 selects 4 as FILT2_ DATA _ i₁-1[7：0]ADR _ ALL _ i as the last sampling address₁-1, and so on, when EDGE _ DATA _ i₁[1]Equal to 1, EDGE _ DATA _ i₁[0]、 EDGE_DATA_i₁[2]、EDGE_DATA_i₁[3]All equal 0, the eighteenth alternative selector MUX218 selects 5 as FILT2_ DATA _ i₁-1[7：0]ADR _ ALL _ i as the last sampling address₁-1; when EDGE _ DATA _ i₁[2]Equal to 1, EDGE _ DATA _ i₁[0]、EDGE_DATA_i₁[1]EDGE_DATA_i₁[3]All equal 0, the eighteenth alternative selector MUX218 selects 6 as FILT2_ DATA _ i₁-1[7：0]ADR _ ALL _ i as the last sampling address₁-1; when EDGE _ DATA _ i₁[3]Equal to 1, EDGE _ DATA _ i₁[0]、EDGE_DATA_i₁[1] EDGE_DATA_i₁[2]All equal 0, the eighteenth alternative selector MUX218 selects 7 as FILT2_ DATA _ i₁-1[7：0]ADR _ ALL _ i as the last sampling address₁-1；

When EDGE _ DATA _ i₁+1[3：0]The fourth OR gate OR4 outputs 1 when one bit of data in the data is equal to 1, and the high-order sample output from the fifth OR gate OR5 effectively identifies VALID _ H _ i₁Is 1, FILT2_ DATA _ i₁+1[3：0]FILT2_ DATA _ i when a transition occurs₁[7：0]High-order sampling is effective; when FILT2_ DATA _ i₁-1[7：0]ADR _ ALL _ i as the last sampling address₁-1 equals 4 and EDGE _ DATA _ i₁+1[4：0]Are all equal to 0, EDGE _ DATA _ i₁[7：4]All equal to 0, the first numerical comparator NC1 outputs 1, the first NOR gate NOR1 outputs 1, the seventh AND gate AND07 outputs 1, the third OR gate OR3 outputs 1, the fifth NOR gate NOR5 outputs 1, the eleventh AND gate AND11 outputs 1, AND the fifth OR gate OR5 outputs the high-order sample VALID flag VALID _ H _ i₁Is 1, FILT2_ DATA _ i₁[0]Twelve clocks after transition, including FILT2_ DATA _ i₁[1]、 FILT2_DATA_i₁[2]……FILT2_DATA_i₁[7]And FILT2_ DATA _ i₁+1[0]、FILT2_DATA _i₁+1[1]、FILT2_DATA_i₁+1[2]……FILT2_DATA_i₁+1[4]) FILT2_ DATA _ i when no more transitions occur₁[7：0]High-order sampling is effective;

and so on when FILT2_ DATA _ i₁-1[7：0]ADR _ ALL _ N-1 is equal to 5 and EDGE _ DATA _ i₁+1[5：0]Are all equal to 0, EDGE _ DATA _ i₁[7：4]All equal to 0, the second digital comparator NC2 outputs 1, the second NOR gate NOR2 outputs 1, the eighth AND gate AND08 outputs 1, the third OR gate OR3 outputs 1, the fifth NOR gate NOR5 outputs 1, the eleventh AND gate AND11 outputs 1, AND the fifth OR gate OR5 outputs the high-order sample VALID flag VALID _ H _ i₁Is 1, FILT2_ DATA _ i₁[1]Twelve clocks after transition, including FILT2_ DATA _ i₁[2]、FILT2_DATA_i₁[3]……FILT2_DATA_i₁[7]And FILT2_ DATA _ i₁+1[0]、FILT2_DATA_i₁+1[1]、FILT2_DATA_i₁+1[2]……FILT2_ DATA_i₁+1[5]) FILT2_ DATA _ i when no more transitions occur₁[7：0]High-order sampling is effective; when FILT2_ DATA _ i₁-1[7：0]ADR _ ALL _ i as the last sampling address₁-1 equals 6 and EDGE _ DATA _ i₁+1[6：0]Are all equal to 0, EDGE _ DATA _ i₁[7：4]All equal to 0, the high-order sample VALID flag VALID _ H _ i output by the third numerical comparator NC3, the third NOR gate NOR3, the ninth AND gate AND09, the third OR gate OR3, the fifth NOR gate NOR5, the eleventh AND gate AND11, AND the fifth OR gate OR5₁Is 1, FILT2_ DATA _ i₁[2]Twelve clocks after transition, including FILT2_ DATA _ i₁[3]、FILT2_DATA_i₁[3]……FILT2_DATA_i₁[7]And FILT2_ DATA _ i₁+1[0]、FILT2_DATA_i₁+1[1]、FILT2_DATA_i₁+1[2]……FILT2_DATA_i₁+1[6]) FILT2_ DATA _ i when no more transitions occur₁[7：0]High-order sampling is effective; when FILT2_ DATA _ i₁-1[7：0]ADR _ ALL _ i as the last sampling address₁-1 equals 7 and EDGE _ DATA _ i₁+1[7：0]Are all equal to 0, EDGE _ DATA _ i₁[7：4]All equal to 0, the fourth numerical comparator NC4 outputs 1, the fourth NOR gate NOR4 outputs 1, the tenth AND gate AND10 outputs1, third OR gate OR3 output 1, fifth NOR gate NOR5 output 1, eleventh AND gate AND11 output 1, AND the high-order sample VALID flag VALID _ H _ i output by fifth OR gate OR5₁Is 1, FILT2_ DATA _ i₁[3]Twelve clocks after transition, including FILT2_ DATA _ i₁[4]、 FILT2_DATA_i₁[3]……FILT2_DATA_i₁[7]And FILT2_ DATA _ i₁+1[0]、FILT2_DATA_ i₁+1[1]、FILT2_DATA_i₁+1[2]……FILT2_DATA_i₁+1[7]) FILT2_ DATA _ i when no more transitions occur₁[7：0]The high order sampling is valid.

As shown in fig. 12, in the present embodiment, the operation principle of the low-order sampling valid flag generating circuit is as follows:

as shown in FIG. 11-1, when EDGE _ DATA _ i₁-1[4]Equal to 1, EDGE _ DATA _ i₁-1[5]、 EDGE_DATA_i₁-1[6]、EDGE_DATA_i₁-1[7]And EDGE _ DATA _ i₁[3：0]Are all equal to 0, i.e., FILT2_ DATA _ i₁-1[4]Transition occurs, FILT2_ DATA _ i₁-1[5]、FILT2_DATA_i₁-1[6]、 FILT2_DATA_i₁-1[7]And FILT2_ DATA _ i₁[3：0]When no transition occurs, the eighteenth alternative selector MUX218 selects 0 as FILT2_ DATA _ i₁-1[7：0]ADR _ ALL _ i as the last sampling address₁-1; and so on, when EDGE _ DATA _ i₁-1[5]Equal to 1, EDGE _ DATA _ i₁-1[4]、EDGE_DATA_ i₁-1[6]、EDGE_DATA_i₁-1[7]And EDGE _ DATA _ i₁[3：0]Are all equal to 0, i.e., FILT2_ DATA _ i₁-1[5]Transition occurs, FILT2_ DATA _ i₁-1[4]、FILT2_DATA_i₁-1[6]、FILT2_DATA_ i₁-1[7]And FILT2_ DATA _ i₁[3：0]When no transition occurs, the eighteenth alternative selector MUX218 selects 1 as FILT2_ DATA _ i₁-1[7：0]ADR _ ALL _ i as the last sampling address₁-1; when EDGE _ DATA _ i₁-1[6]Equal to 1, EDGE _ DATA _ i₁-1[4]、EDGE_DATA_i₁-1[5]、EDGE_DATA_i₁-1[7]And EDGE _ DATA _ i₁[3：0]Are all equal to 0, i.e., FILT2_ DATA _ i₁-1[6]Transition occurs, FILT2_ DATA _ i₁-1[4]、FILT2_DATA_i₁-1[5]、FILT2_DATA_i₁-1[7]And FILT2_ DATA _ i₁[3：0]When no transition occurs, the eighteenth alternative selector MUX218 selects 2 as FILT2_ DATA _ i₁-1[7：0]ADR _ ALL _ i as the last sampling address₁-1; when EDGE _ DATA _ i₁-1[7]Equal to 1, EDGE _ DATA _ i₁-1[4]、EDGE_DATA_i₁-1[5]、EDGE_DATA_i₁-1[6]And EDGE _ DATA _ i₁[3：0]Are all equal to 0, i.e., FILT2_ DATA _ i₁-1[7]Transition occurs, FILT2_ DATA _ i₁-1[4]、FILT2_DATA_i₁-1[5]、FILT2_DATA_i₁-1[6]And FILT2 DATA _ i₁[3：0]When no transition occurs, the eighteenth alternative selector MUX218 selects 3 as FILT2_ DATA _ i₁1[7：0]ADR _ ALL _ i as the last sampling address₁-1；

When EDGE _ DATA _ i₁[7：4]The seventh OR gate OR7 outputs 1 when the one-bit data in the data is equal to 1, and the low-order sample output from the eighth OR gate OR8 effectively identifies VALID _ L _ i₁Is 1, FILT2_ DATA _ i₁[7：4]FILT2_ DATA _ i when a transition occurs₁[7：0]Low-order sampling is effective; when FILT2_ DATA _ i₁-1[7：0]ADR _ ALL _ i as the last sampling address₁-1 equals 0 and EDGE _ DATA _ i₁+1[0]Equal to 0, EDGE _ DATA _ i₁[7：0]All equal to 0, the fifth numerical comparator NC5 outputs 1, the sixteenth NOT gate NOT16 outputs 1, the twelfth AND gate AND12 outputs 1, the sixth OR gate OR6 outputs 1, the ninth NOR gate NOR9 outputs 1, the sixteenth AND gate AND16 outputs 1, AND the eighth OR gate OR8 outputs the low-bit sample VALID flag VALID _ L _ i₁Is 1, FILT2_ DATA _ i₁-1[4]Twelve clocks after transition, including FILT2_ DATA _ i₁-1[5]、 FILT2_DATA_i₁-1[6]、FILT2_DATA_i₁-1[7]、FILT2_DATA_i₁[0]、FILT2_DATA_i₁ [1]……FILT2_DATA_i₁[7]And FILT2_ DATA _ i₁+1[0]) FILT2_ DATA _ i when no more transitions occur₁[7：0]Low-order sampling is effective; and so on when FILT2_ DATA _ i₁-1[7：0]ADR _ ALL _ i as the last sampling address₁-1 equals 1 and EDGE _ DATA _ i₁+1[1：0]Are all equal to 0, EDGE _ DATA _ i₁ [7：0]EqualizationAt 0, the sixth numerical comparator NC6 outputs 1, the sixth NOR gate NOR6 outputs 1, the thirteenth AND gate AND13 outputs 1, the sixth OR gate 0R6 outputs 1, the ninth NOR gate NOR9 outputs 1, the sixteenth AND gate AND16 outputs 1, AND the eighth OR gate OR8 outputs the low-bit sampling VALID flag VALID _ L _ i₁Is 1, FILT2_ DATA _ i₁-1[5]Twelve clocks after transition, including FILT2_ DATA _ i₁-1[6]、 FILT2_DATA_i₁-1[7]、FILT2_DATA_i₁[0]、FILT2_DATA_i₁[1]……FILT2_DATA i₁[7]And FILT2_ DATA _ i₁+1[0]、FILT2_DATA_i₁+1[1]FILT2_ DATA _ i when no more transitions occur₁[7：0]The low bit is sampled valid when FILT2_ DATA _ i₁-1[7：0]ADR _ ALL _ i as the last sampling address₁-1 equals 2 and EDGE _ DATA _ i₁+1[2：0]Are all equal to 0, EDGE _ DATA _ i₁[7：0]All equal to 0, the low-order sampling VALID flag VALID _ L _ i output from the seventh numerical comparator NC7, the seventh NOR gate NOR7, the fourteenth AND gate AND14, the sixth OR gate OR6, the ninth NOR gate NOR9, the sixteenth AND gate AND16, AND the eighth OR gate OR8₁Is 1, FILT2_ DATA _ i₁+1[7]Twelve clocks after transition, including FILT2_ DATA _ i₁[0]、FILT2_DATA_ i₁[1]……FILT2_DATA_i₁[7]And FILT2_ DATA _ i₁+1[0]、FILT2_DATA_i₁+1[1] ……FILT2_DATA_i₁+1[3]FILT2_ DATA _ i when no more transitions occur₁[7：0]The low bit is sampled valid when FILT2_ DATA _ i₁-1[7：0]ADR _ ALL _ i as the last sampling address₁-1 equals 3 and EDGE _ DATA _ i₁+1[3：0]Are all equal to 0, EDGE _ DATA _ i₁[7：0]All equal to 0, the eighth numerical comparator NC8 outputs 1, the eighth NOR gate NOR8 outputs 1, the fifteenth AND gate AND15 outputs 1, the sixth OR gate OR6 outputs 1, the ninth NOR gate NOR9 outputs 1, the sixteenth AND gate AND16 outputs 1, AND the eighth OR gate OR8 outputs the low-bit sample VALID flag VALID _ L _ i₁Is 1, FILT2_ DATA _ i₁-1[7]Twelve clocks after transition, including FILT2_ DATA _ i₁[0]、FILT2_DATA_i₁[1]……FILT2_DATA_i₁[7]And FILT2_ DATA _ i₁+1[0]、FILT2_DATA_i₁+1[1]……FILT2_DATA_i₁+1[3]FILT2_ DATA _ i when no more transitions occur₁[7：0]The low order sampling is valid.

Example two

The difference between this embodiment and the first embodiment is: the control signal input terminal sel of the first alternative selector MUX2101 is connected to the output terminal of the second OR gate OR102 and receives the first filter reset signal FILT1_ CLR _ i output from the second OR gate OR102₁[j₁]The DATA input terminal a receives SYNC _ DATA _ i₁[j₁]Data input b receives 0; a control signal input terminal sel of the second alternative selector MUX2101 is connected to an output terminal of the first OR gate OR101, and receives the first filtered SET signal FILT1_ SET _ i output from the first OR gate OR101₁[j₁]The DATA input end a is connected with the output end of the first alternative selector MUX2101, the DATA input end b receives 1, and the output end outputs SYNC _ DATA _ i₁[j₁]Filter result FILT1_ DATA _ i of₁[j₁](ii) a The control signal input terminal sel of the first alternative selector MUX2201 is connected to the output terminal of the second OR gate OR202, and receives the second filtered reset signal FILT2_ CLR _ i output from the second OR gate OR202₁[j₁]The DATA input terminal a receives FILT1_ DATA _ i₁[j₁]Data input b receives 0; the control signal input terminal sel of the second alternative selector MUX2201 is connected to the output terminal of the first OR gate OR201, and receives the second filtered SET signal FILT2_ SET _ i output from the first OR gate OR201₁[j₁]The DATA input terminal a is connected to the output terminal of the first alternative selector MUX2201, the DATA input terminal b receives 1, and the output terminal outputs FILT1_ DATA _ i₁[j₁]Filter result FILT2_ DATA _ i of₁[j₁]。

EXAMPLE III

As shown in fig. 12, the present embodiment is different from the first embodiment in that: the filtering unit comprises only one filtering circuit, and the filtered DATA output by the filtering unit is the current beat first filtered DATA FILT1_ DATA 0; the edge detection unit receives the current beat of the first filtered DATA output by the first filter circuit and the previous beat of the first filtered DATA FILT1_ DATA1 output by the shift register, and performs edge detection on the current beat of the first filtered DATA FILT1_ DATA 0; the DATA selection unit receives the current beat EDGE detection DATA EDGE _ DATA0 output by the EDGE detection circuit and the previous beat first filtered DATA FILT1_ DATA1, the previous beat first EDGE detection DATA EDGE _ DATA1 and the previous two beats EDGE detection DATA EDGE _ DATA2 output by the shift register, samples the previous beat first filtered DATA FILT1_ DATA1, and outputs the high-bit sample DATA _ H, the low-bit sample DATA _ L, the high-bit sample VALID flag VALID _ H and the low-bit sample VALID flag VALID _ L of the previous beat first filtered DATA FILT1_ DATA 1.

The filtering unit in this embodiment can filter a single glitch occupying one phase and a single glitch occupying two phases, the data selecting unit can sample at four phase clocks before a first filtering data transition edge, and select the last eight phase clocks of the last sampling point to sample when a new transition edge is not detected at any of twelve phase clocks after the transition edge, the working principle of the data sampling unit is consistent with that in the first embodiment, only the input data is different, and different input data is sampled.

It is only above the preferred embodiment of the utility model, the utility model discloses a scope of protection does not only confine above-mentioned embodiment, the all belongings to the utility model discloses a technical scheme under the thinking all belongs to the utility model discloses a scope of protection. It should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.

Claims

1. A filtering unit includes a filtering circuit; the method is characterized in that: the filter circuit includes eight filters, jth₁Each filter comprises a filter setting signal generating circuit, a filter reset signal generating circuit and a three-out-of-one selecting unit, j₁0, 1, 2 … 7; adjacent three-beat eight-bit DATA DATA _ i₁-1[7：0]、DATA_i₁[7：0]、DATA_i₁+1[7：0]Constitute twenty-four bit DATA _ ALLi₁[23：0](ii) a The filter set signal generation circuit receives DATA _ ALL _ i₁[j₁+5]To DATA _ ALL _ i₁[j₁+11]Outputting a filtering setting signal; the filter reset signal generation circuit receives DATA _ ALL _ i₁[j₁+5]To DATA _ ALL _ i₁[j₁+11]Outputting a filtering reset signal; three DATA input ends of the one-out-of-three selection unit respectively receive DATA _ i₁[j₁]1 and0, two control signal input ends respectively receiving the filtering set signal and the filtering reset signal, and a DATA output end outputting DATA _ i₁[j₁]The result of the filtering of (1).

2. The filter unit of claim 1, wherein: the filtering set signal generating circuit comprises a first AND gate, a second AND gate, a third AND gate, a first NOT gate, a second NOT gate, a third NOT gate, a fourth NOT gate, a fifth NOT gate and a first OR gate; two input ends of the first AND gate respectively receive DATA _ ALL _ i₁[j₁+7]、DATA_ALL_i₁[j₁+9]The other input terminal of the first NOT gate is connected to the output terminal of the first NOT gate, and the input terminal of the first NOT gate receives DATA _ ALL _ i₁[j₁+9](ii) a Four input ends of the second AND gate respectively receive DATA _ ALL _ i₁[j₁+6]、DATA_ALL_i₁[j₁+7]、DATA_ALL_i₁[j₁+10]And DATA _ ALL _ i₁[j₁+11]The other two input terminals are respectively connected with the output terminal of the second NOT gate and the output terminal of the third NOT gate, and the input terminals of the second NOT gate and the third NOT gate respectively receive DATA _ ALL _ i₁[j₁+8]、DATA_ALL_i₁[j₁+9](ii) a Four input ends of the third AND gate respectively receive DATA _ ALL _ i₁[j₁+5]、DATA_ALL_i₁[j₁+6]、DATA_ALL_i₁[j₁+9]And DATA _ ALL _ i₁[j₁+10]The other two input terminals are respectively connected with the output terminal of the fourth NOT gate and the output terminal of the fifth NOT gate, and the input terminal of the fourth NOT gate and the input terminal of the fifth NOT gate respectively receive DATA _ ALL _ i₁[j₁+7]、DATA_ALL_i₁[j₁+8](ii) a The output end of the first AND gate, the output end of the second AND gate and the output end of the third AND gate are respectively connected with three input ends of the first OR gate, the output end of the first OR gate is connected with the first control signal input end of the one-of-three selection unit, and a filtering setting signal is output to the first control signal input end of the one-of-three selection unit.

3. The filter unit of claim 1, wherein: the filtering reset signal generating circuit comprises a fourth AND gate, a fifth AND gate, a sixth NOT gate, a seventh NOT gate, an eighth NOT gate, a ninth NOT gate, a tenth NOT gate, an eleventh NOT gate, a twelfth NOT gate, a thirteenth NOT gate, a fourteenth NOT gate, a fifteenth NOT gate and a second OR gate; one input terminal of the fourth AND gate receives DATA _ ALL _ i₁[j₁+8]The other two input terminals are respectively connected with the output terminal of the sixth not gate and the output terminal of the seventh not gate, and the input terminal of the sixth not gate and the input terminal of the seventh not gate respectively receive DATA _ ALL _ i₁[j₁+7]、DATA_ALL_i₁[j₁+9](ii) a Two input ends of the fifth AND gate respectively receive DATA _ ALL _ i₁[j₁+8]、DATA_ALL_i₁[i+9]The other four input terminals are respectively connected with the output terminal of the eighth not gate, the output terminal of the ninth not gate, the output terminal of the tenth not gate and the output terminal of the eleventh not gate, and the input terminal of the eighth not gate, the input terminal of the ninth not gate, the input terminal of the tenth not gate and the input terminal of the eleventh not gate respectively receive DATA _ ALL _ i₁[j₁+6]、DATA_ALL_i₁[j₁+7]、DATA_ALL_i₁[j₁+10]And DATA _ ALL _ i₁[j₁+11](ii) a Two input ends of the sixth AND gate receive DATA _ ALL _ i₁[j₁+7]、DATA_ALL_i₁[j₁+8]The other four input ends are respectively connected with the output end of the twelfth NOT gate, the output end of the thirteenth NOT gate, the output end of the fourteenth NOT gate and the output end of the fifteenth NOT gate, and the input end of the twelfth NOT gate, the input end of the thirteenth NOT gate and the input end of the fourteenth NOT gateThe input terminal of the input terminal and the input terminal of the fifteenth NOT gate receive DATA _ ALL _ i₁[j₁+5]、DATA_ALL_i₁[j₁+6]、DATA_ALL_i₁[j₁+9]And DATA _ ALL _ i₁[i+10](ii) a The output end of the fourth AND gate, the output end of the fifth AND gate and the output end of the sixth AND gate are respectively connected with three input ends of the second OR gate, the output end of the second OR gate is connected with the second control signal input end of the one-of-three selection unit, and a filtering reset signal is output to the second control signal input end of the one-of-three selection unit.

4. The filter unit of claim 1, wherein: the three-to-one selection unit comprises a first two-to-one selector and a second two-to-one selector;

a control signal input terminal of the first alternative selector receives the filtering setting signal, and a DATA input terminal receives the DATA _ i₁[j₁]The other DATA input end of the first alternative selector receives 1, the output end of the first alternative selector is connected with one DATA input end of the second alternative selector, the other DATA input end of the second alternative selector receives 0, the control signal input end of the first alternative selector receives a filtering reset signal, and the output end of the first alternative selector outputs DATA _ i₁[j₁]As a result of the filtering of (a),

or, the control signal input end of the first alternative selector receives a filtering reset signal, and one DATA input end of the first alternative selector receives DATA _ i₁[j₁]The other DATA input end of the first alternative selector receives 0, the output end of the first alternative selector is connected with one DATA input end of the second alternative selector, the other DATA input end of the second alternative selector receives 1, the control signal input end of the first alternative selector receives a filtering setting signal, and the output end of the first alternative selector outputs DATA _ i₁[j₁]The result of the filtering of (1).

5. The filtering unit according to any one of claims 1 to 4, characterized in that: the filtering unit comprises two filtering circuits, wherein the filtering result output by the first filtering circuit is first filtering data which is eight-bit serial data, the second filtering circuit receives the first filtering data, and the output filtering result is second filtering data which is eight-bit serial data.

6. The filtering unit according to any one of claims 1 to 4, characterized in that: the input end of the filter circuit receives adjacent three-beat eight-bit serial data; the serial DATA of three adjacent beats and eight bits simultaneously respectively output three adjacent beats and eight DATA DATA _ i₁-1[7：0]、DATA_i₁[7：0]、DATA_i₁+1[7：0]To the filter circuit.

7. The filtering unit according to claim 6, characterized in that: the filtering unit comprises two filtering circuits, wherein the first filtering circuit outputs first filtering DATA which is eight-bit serial DATA, the second filtering circuit receives the first filtering DATA of three adjacent beats and outputs second filtering DATA which is eight-bit serial DATA, and the first filtering DATA of three adjacent beats simultaneously respectively outputs three adjacent beats of eight-bit DATA FILT1_ DATA _ i₁-1[7：0]、FILT1_DATA_i₁[7：0]、FILT1_DATA_i₁+1[7：0]To the second filter circuit, the second filtered data is eight-bit serial data.

8. A clock data recovery circuit using the filter unit of any one of claims 1 to 7, characterized in that: the device also comprises an oversampling unit, a synchronization unit, an edge detection unit, a data selection unit and a data storage unit; the oversampling unit receives serial input data and an eight-phase clock, and outputs oversampling data corresponding to the eight-phase clock, the oversampling data being eight-bit serial data; the synchronization unit receives the over-sampling data output by the over-sampling unit and outputs synchronized data after synchronization processing, wherein the synchronized data are eight-bit serial data; the filtering unit receives the synchronous data output by the synchronous unit and outputs filtering data, wherein the filtering data is eight-bit serial data, when the filtering unit comprises one filtering circuit, the filtering data is first filtering data, and when the filtering unit comprises two filtering circuits, the filtering data is second filtering data; the edge detection unit receives the filtering data output by the filtering unit and outputs edge detection data, wherein the edge detection data are eight-bit serial data; the data selection unit receives the filtering data output by the filtering unit and the edge detection data output by the edge detection unit, samples are carried out at four phase clocks before the jump edge of the filtering data, and eight phase clocks after the last sampling point are selected for sampling when a new jump edge is not detected at twelve phase clocks after the jump edge; the data storage unit is used for outputting the valid data sampled by the data selection unit.

9. The clock data recovery circuit of claim 8, wherein: the data selection unit comprises a high-order sampling circuit, a low-order sampling circuit, a high-order sampling effective identifier generation circuit and a low-order sampling effective identifier generation circuit; the high-order sampling circuit receives the filtering data and the low-order four-digit data of the edge detection data, carries out high-order sampling on the filtering data according to the low-order four-digit data of the edge detection data and outputs high-order sampling data; the low-order sampling circuit receives filtering data and high-order four-digit data of edge detection data, performs low-order sampling on the filtering data according to the high-order four-digit data of the edge detection data, and outputs low-order sampling data; the high-order sampling effective identification generating circuit receives the edge detection data and outputs a high-order sampling effective identification; the low-order sampling effective identification generating circuit receives the edge detection data and outputs a low-order sampling effective identification;

10. The clock data recovery circuit of claim 9, wherein: the high-order sampling circuit comprises a high-order sampling address generating circuit and a first one-of-eight selector; the low-order sampling circuit comprises a low-order sampling address generating circuit and a second one-of-eight selector; the high-order sampling address generation circuit receives EDGE _ DATA _ i₁+1[3：0]Outputting a high-order sampling address; the DATA input of the first one-of-eight selector receives FILT _ DATA _ i₁[7：0]The input end of the control signal receives a high-order sampling address output by the high-order sampling address generating circuit, and the first one-out-of-eight selector selects FILT _ DATA _ i under the control of the high-order sampling address₁[7：4]One bit of data in the data is output as high-order sampling data; the low-order sampling address generation circuit receives EDGE _ DATA _ i₁[7：4]Outputting a low-order sampling address; a DATA input of the second one-of-eight selector receives FILT _ DATA _ i₁[7：0]The input end of the control signal receives the lower sampling address output by the lower sampling address generating circuit, and the second one-out-of-eight selector selects FILT _ DATA _ i under the control of the lower sampling address₁[3：0]One bit of data in (b) is output as lower sampled data.

11. The clock data recovery circuit of claim 10, wherein: the high-order sampling address generating circuit comprises a third alternative selector, a fourth alternative selector, a fifth alternative selector, a sixth alternative selector and a third register; the control signal input end of the third alternative selector receives EDGE _ DATA _ i₁+1[0]One DATA input terminal receives FILT _ DATA _ i fed back by the third register₁-1[7：0]The other data input end of the high-order sampling address of (4) is received, and the output end of the high-order sampling address of (4) is connected with one data input end of the fourth alternative selector; the control signal input end of the fourth alternative selector receives EDGE _ DATA _ i₁+1[1]The other input end receives the signal 5, and the output end is connected with one data input end of the fifth alternative selector; a control signal input terminal of the fifth one-of-choices selector receives EDGE _ DATA _ i₁+1[2]The other data input end receives the signal 6, and the output end is connected with one data input end of the sixth alternative selector; a control signal input terminal of the sixth alternative selector receives EDGE _ DATA _ i₁+1[3]The other DATA input terminal receives 7, and the output terminal outputs FILT _ DATA _ i₁[7：0]Sample the address and sample the high order bits of FILT _ DATA _ i₁[7：0]Sends the high-order sampling address of the third register, and sends FILT _ DATA _ i to the third register₁[7：0]Is fed back to a DATA input terminal of the third alternative selector as a DATA input terminal for generating FILT _ DATA _ i₁+1[7：0]The upper bits of (b) sample the input value of the address.

12. The clock data recovery circuit of claim 11, wherein: the low-order sampling address generating circuit comprises a seventh alternative selector, an eighth alternative selector, a ninth alternative selector, a twelfth alternative selector and a fourth register; a control signal input terminal of the seventh alternative selector receives EDGE _ DATA _ i₁[4]One DATA input terminal receives FILT _ DATA _ i fed back from the fourth register₁-1[7：0]The other data input end of the low-order sampling address of (1) receives 0, and the output end of the low-order sampling address of (1) is connected with one data input end of the eighth alternative selector; a control signal input terminal of the eighth either-or selector receives EDGE _ DATA _ i₁[5]The other data input end receives 1, and the output end is connected with one data input end of the ninth alternative selector; a control signal input terminal of the ninth alternative selector receives EDGE _ DATA _ i₁[6]The other data input end receives 2, and the output end is connected with one data input end of the twelfth one-of-choice selector; of the twelfth alternative selectorThe control signal end receives EDGE _ DATA _ i₁[7]The other DATA input terminal receives 3, and the output terminal outputs FILT _ DATA _ i₁[7：0]Sample the address and sample the low order of FILT _ DATA _ i₁[7：0]The lower sampling address of (1) is stored in a fourth register, and FILT _ DATA _ i is stored in the fourth register₁[7：0]Is fed back to a DATA input terminal of the seventh alternative selector as FILT _ DATA _ i₁+1[7：0]The lower order of the sampling address.

13. The clock data recovery circuit of claim 9, wherein: when the FILT _ DATA _ i₁[7：0]When the high-order sampling is valid, the high-order sampling valid flag generation circuit selects 1 as FILT _ DATA _ i₁[7：0]The high bit of the sample valid flag output when the FILT _ DATA _ i₁[7：0]When the high-order sampling is invalid, the high-order sampling valid flag generation circuit selects 0 as FILT _ DATA _ i₁[7：0]The high-order sampling effective identification is output; when the FILT _ DATA _ i₁[7：0]The lower sampling valid flag generation circuit selects 1 as FILT _ DATA _ i when the lower sampling is valid₁[7：0]The low bit of the sample valid flag output when the FILT _ DATA _ i₁[7：0]When the lower sampling is invalid, the lower sampling valid flag generation circuit selects 0 as FILT _ DATA _ i₁[7：0]The low order samples of (a) effectively identify the output.

14. The clock data recovery circuit of claim 13, wherein: the high-order sampling identification generating circuit comprises an eleventh second-to-first selector, a twelfth second-to-first selector, a thirteenth second-to-first selector, a fourteenth second-to-first selector, a fifteenth second-to-first selector, a sixteenth second-to-first selector, a seventeenth second-to-first selector, an eighteenth second-to-first selector, a fifth register, a first numerical comparator, a second numerical comparator, a third numerical comparator, a fourth numerical comparator, a first NOR gate, a second NOR gate, a third NOR gate, a fourth NOR gate, a fifth NOR gate, a seventh AND gate, an eighth AND gate, a ninth AND gate, a tenth AND gate, an eleventh AND gate, a third OR gate, a fourth OR gate and a fifth OR gate;

a control signal input terminal of the eleventh alternative selector receives EDGE _ DATA _ i₁-1[4]One DATA input terminal receives FILT _ DATA _ i fed back from the fifth register₁-2[7：0]The other data input end of the last sampling address of (1) receives 0, and the output end of the last sampling address of (1) is connected with one data input end of the twelfth alternative selector; a control signal input terminal of the twelfth alternative selector receives EDGE _ DATA _ i₁-1[5]The other data input end receives 1, and the output end is connected with one data input end of the thirteenth alternative selector; a control signal input terminal of the thirteenth alternative selector receives EDGE _ DATA _ i₁-1[6]The other data input end receives 2, and the output end is connected with one data input end of the fourteenth alternative selector; a control signal input terminal of the fourteenth either-or selector receives EDGE _ DATA _ i₁-1[7]The other data input end receives the signal 3, and the output end is connected with one data input end of the fifteenth alternative selector; a control signal input terminal of the fifteenth alternative selector receives EDGE _ DATA _ i₁[0]The other data input end receives 4, and the output end is connected with one data input end of the sixteenth alternative selector; a control signal input terminal of the sixteenth alternative selector receives EDGE _ DATA _ i₁[1]The other data input end receives the signal 5, and the output end is connected with one data input end of the nineteenth alternative selector; a control signal input terminal of the seventeenth alternative selector receives EDGE _ DATA _ i₁[2]The other data input end receives 6, and the output end is connected with one data input end of the eighteenth alternative selector; a control signal input terminal of the eighteenth alternative selector receives EDGE _ DATA _ i₁[3]The other DATA input terminal receives 7, and the output terminal outputs FILT _ DATA _ i₁-1[7：0]And will FILT _ DATA _ i₁-1[7：0]Is sent to the fifth register, and the fifth register sends FILT _ DATA _ i₁-1[7：0]Is fed back to a DATA input terminal of the eleventh alternative selector as a DATA _ i generator₁[7：0]The input value of the last sampling address of (1);

one input end of each of the first numerical comparator, the second numerical comparator, the third numerical comparator and the fourth numerical comparator receives FILT _ DATA _ i₁-1[7：0]The other input receives 4, 5, 6 and 7, respectively; five input terminals of the first NOR gate respectively receive EDGE _ DATA _ i₁+1[0]、EDGE_DATA_i₁+1[1]、EDGE_DATA_i₁+1[2]、EDGE_DATA_i₁+1[3]、EDGE_DATA_i₁+1[4](ii) a Two input ends of the seventh AND gate are respectively connected with the output end of the first numerical comparator and the output end of the first NOR gate; six input terminals of the second NOR gate respectively receive EDGE _ DATA _ i₁+1[0]、EDGE_DATA_i₁+1[1]、EDGE_DATA_i₁+1[2]、EDGE_DATA_i₁+1[3]、EDGE_DATA_i₁+1[4]、EDGE_DATA_i₁+1[5](ii) a Two input ends of the eighth AND gate are respectively connected with the output end of the second numerical comparator and the output end of the second NOR gate; seven input terminals of the third NOR gate respectively receive EDGE _ DATA _ i₁+1[0]、EDGE_DATA_i₁+1[1]、EDGE_DATA_i₁+1[2]、EDGE_DATA_i₁+1[3]、EDGE_DATA_i₁+1[4]、EDGE_DATA_i₁+1[5]、EDGE_DATA_i₁+1[6](ii) a Two input ends of the ninth AND gate are respectively connected with the output end of the third numerical comparator and the output end of the third NOR gate; eight input terminals of the fourth NOR gate respectively receive EDGE _ DATA _ i₁+1[0]、EDGE_DATA_i₁+1[1]、EDGE_DATA_i₁+1[2]、EDGE_DATA_i₁+1[3]、EDGE_DATA_i₁+1[4]、EDGE_DATA_i₁+1[5]、EDGE_DATA_i₁+1[6]、EDGE_DATA_i₁+1[7](ii) a Two input ends of the tenth AND gate are respectively connected with the output end of the fourth numerical comparator and the output end of the fourth NOR gate; the four input ends of the third or gate are respectively connected with the output end of the seventh and gate, the output end of the eighth and gate, the output end of the ninth and gate and the output end of the tenth and gate; the four input terminals of the fifth NOR gate NORS are respectively connected with EDGE _ DATA _ i₁[4]、EDGE_DATA_i₁[5]、EDGE_DATA_i₁[6]、EDGE_DATA_i₁[7]Connecting; two input ends of the eleventh AND gate are respectively connected with the output end of the third OR gate and the output end of the fifth NOR gate; four input terminals of the fourth OR gate respectively receive EDGE _ DATA _ i₁+1[0]、EDGE_DATA_i₁+1[1]、EDGE_DATA_i₁+1[2]、EDGE_ DATA_i₁+1[3]Connecting; and two input ends of the fifth OR gate are respectively connected with the output end of the eleventh AND gate and the output end of the fourth OR gate, and the output end outputs a high-order sampling effective identifier.

15. The clock data recovery circuit of claim 13, wherein: the low-order sampling effective identification generating circuit comprises an eleventh second-to-first selector, a twelfth second-to-first selector, a thirteenth second-to-first selector, a fourteenth second-to-first selector, a fifteenth second-to-first selector, a sixteenth second-to-first selector, a seventeenth second-to-first selector, an eighteenth second-to-first selector, a fifth register, a fifth numerical comparator, a sixth numerical comparator, a seventh numerical comparator, an eighth numerical comparator, a sixteenth not gate, a sixth not gate, a seventh not gate, an eighth not gate, a ninth not gate, a twelfth and gate, a thirteenth and gate, a fourteenth and gate, a fifteenth and gate, a sixteenth and gate, a sixth or gate, a seventh or gate and an eighth or gate;

a control signal input terminal of the eleventh alternative selector receives EDGE _ DATA _ i₁-1[4]One DATA input terminal receives FILT _ DATA _ i fed back from the fifth register₁-2[7：0]The other data input end of the last sampling address of (1) receives 0, and the output end of the last sampling address of (1) is connected with one data input end of the twelfth alternative selector; a control signal input terminal of the twelfth alternative selector receives EDGE _ DATA _ i₁-1[5]The other data input end receives 1, and the output end is connected with one data input end of the thirteenth alternative selector; a control signal input terminal of the thirteenth alternative selector receives EDGE _ DATA _ i₁-1[6]The other data input end receives 2, and the output end is connected with one of the fourteenth alternative selectorThe data input ends are connected; a control signal input terminal of the fourteenth either-or selector receives EDGE _ DATA _ i₁-1[7]The other data input end receives the signal 3, and the output end is connected with one data input end of the fifteenth alternative selector; a control signal input terminal of the fifteenth alternative selector receives EDGE _ DATA _ i₁[0]The other data input end receives 4, and the output end is connected with one data input end of the sixteenth alternative selector; a control signal input terminal of the sixteenth alternative selector receives EDGE _ DATA _ i₁[1]The other data input end receives the signal 5, and the output end is connected with one data input end of the nineteenth alternative selector; a control signal input terminal of the seventeenth alternative selector receives EDGE _ DATA _ i₁[2]The other data input end receives 6, and the output end is connected with one data input end of the eighteenth alternative selector; a control signal input terminal of the eighteenth alternative selector receives EDGE _ DATA _ i₁[3]The other DATA input terminal receives 7, and the output terminal outputs FILT _ DATA _ i₁-1[7：0]And will FILT _ DATA _ i₁-1[7：0]Is sent to the fifth register, and the fifth register sends FILT _ DATA _ i₁-1[7：0]Is fed back to a DATA input terminal of the eleventh alternative selector as a DATA _ i generator₁[7：0]The input value of the last sampling address of (1);

one input end of each of the fifth numerical comparator, the sixth numerical comparator, the seventh numerical comparator and the eighth numerical comparator receives FILT _ DATA _ i₁-1[7：0]The other input terminal receives 0, 1, 2 and 3, respectively; an input terminal of the sixteenth not-gate receives EDGE _ DATA _ i₁+1[0](ii) a Two input ends of the twelfth AND gate are respectively connected with the output end of the fifth numerical comparator and the output end of the sixteenth NOT gate; two input terminals of the sixth NOR gate respectively receive EDGE _ DATA _ i₁+1[0]、EDGE_DATA_i₁+1[1](ii) a Two input ends of the thirteenth AND gate are respectively connected with the output end of the sixth numerical comparator and the output end of the sixth NOR gate; three inputs of the seventh NOR gateThe terminals receive EDGE _ DATA _ i respectively₁+1[0]、EDGE_DATA_i₁+1[1]、EDGE_DATA_i₁+1[2](ii) a Two input ends of the fourteenth AND gate are respectively connected with an output end of the seventh numerical comparator and an output end of the seventh NOR gate; four input terminals of the eighth NOR gate respectively receive EDGE _ DATA _ i₁+1[0]、EDGE_DATA_i₁+1[1]、EDGE_DATA_i₁+1[2]、EDGE_DATA_i₁+1[3](ii) a Two input ends of the fifteenth AND gate are respectively connected with an output end of the eighth numerical comparator and an output end of the eighth NOR gate; the four input ends of the sixth or gate are respectively connected with the output end of the twelfth and gate, the output end of the thirteenth and gate, the output end of the fourteenth and gate and the output end of the fifteenth and gate; eight input terminals of the ninth NOR gate respectively receive EDGE _ DATA _ i₁[0]、EDGE_DATA_i₁[1]、EDGE_DATA_i₁[2]、EDGE_DATA_i₁[3]、EDGE_DATA_i₁[4]、EDGE_DATA_i₁[5]、EDGE_DATA_i₁[6]、EDGE_DATA_i₁[7](ii) a Two input ends of the sixteenth AND gate are respectively connected with an output end of the sixth OR gate and an output end of the ninth NOR gate; four input terminals of the seventh OR gate respectively receive EDGE _ DATA _ i₁[4]、EDGE_DATA_i₁[5]、EDGE_DATA_i₁[6]、EDGE_DATA_i₁[7]Connecting; and two input ends of the eighth or gate are respectively connected with the output end of the sixteenth and gate and the output end of the seventh or gate, and the output end outputs a low-order sampling effective identifier.

16. The clock data recovery circuit of any one of claims 8-15, wherein: the device also comprises a shift register; the shift register receives the synchronous data output by the synchronous unit, registers the synchronous data for one beat and two beats, and then outputs the synchronous data of the previous beat and the synchronous data of the previous two beats; the filtering unit receives the synchronous data output by the synchronizing unit and the synchronous data of the previous beat and the synchronous data of the previous two beats output by the shift register and outputs filtering data; the shift register receives the filtering data output by the filtering unit, registers the filtering data for one beat, and outputs the filtering data of the previous beat; the edge detection unit receives the filtering data output by the filtering unit and the previous beat of filtering data output by the shift register and outputs edge detection data; the shift register receives the edge detection data output by the edge detection unit, registers the edge detection data for one beat and moves for two beats, and then outputs the edge detection data for the previous beat and the edge detection data for the previous two beats; the data selection unit receives the previous beat of filtering data output by the filtering unit, the edge detection data output by the edge detection unit, the previous beat of edge detection data output by the shift register and the previous two beats of edge detection data, and outputs high-order sampling data, low-order sampling data, a high-order sampling effective identifier and a low-order sampling effective identifier;

17. A USB clock data recovery circuit, comprising: the clock data recovery circuit of any of claims 8-16, wherein the serial input data received by the oversampling unit is high speed USB data.