CN102510328A - High-speed parallel interface circuit - Google Patents
High-speed parallel interface circuit Download PDFInfo
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Abstract
The invention is suitable for the digital communication field, and provides a high-speed parallel interface circuit. The high-speed parallel interface circuit comprises a low voltage differential signaling (LVDS) receiving module, a data sampling module, a data restoring module and a word synchronization module, wherein the LVDS receiving module receives and shapes data; the data sampling module is connected with the LVDS receiving module and samples the data output by the LVDS receiving module under a plurality of phase clocks; the data restoring module is connected with the data sampling module, selects optimal sampling data from oversampling data output from the data sampling module and restores original data by non return to zero inverse (NRZI) decoding; and the word synchronization module is connected with the data restoring module and carries out shift adjustment to the data output by the data restoring module. In the high-speed parallel interface circuit, oversampling and word synchronization are combined to carry out accurate sampling restoration and synchronization to source-synchronous parallel data; and data in the center of an effective window can be dynamically and accurately sampled and restored in real time by dynamically synchronizing, filtering, discriminating phase, selecting the oversampling data and the like.
Description
Technical field
The invention belongs to digital communicating field, relate in particular to a kind of high speed parallel interface circuit.
Background technology
Along with the flourish communication system that causes of digital communication service has proposed unprecedented challenge to the communication interface transmission bandwidth, wherein high speed parallel interface and HSSI High-Speed Serial Interface solution have a wide range of applications in fields such as optical fiber communication, exchanges data.High-speed parallel is transmitted; The have efficient recovery and the passage of data are transmission bottleneck synchronously; Two problems of main existence: the one, when the single line transmission rate was more and more faster, corresponding bits per inch was more and more littler according to shared time window, and the valid window that causes clock to be difficult in data is accurately sampled; The 2nd, because each data paths of parallel transmission postpones difference, cause receiving terminal to be difficult to efficient synchronization and receive data.
In the prior art, data receiver mainly is to adopt dual mode to realize the data recovery, a kind of digital circuit that is based on training sequence, and another kind is that the simulated clock simulation clock data are recovered.When carrying out the recovery of high-speed data, earlier training sequence is sampled, obtain the phase place of clock,, make it possible to sampling in data window central authorities then through phase-locked loop is carried out the adjustment of clock phase according to sampled value based on the training sequence circuit.Each passage is sampled by the way and again each channel sample data is carried out Synchronous Processing after adjustment is accomplished.Can be fast data be recovered and synchronously through above-mentioned circuit, but shortcoming be can not dynamic real-time sampling phase is adjusted, when shake that big phase place occurs and drift, can cause sample error.For the simulated clock simulation clock data recovery circuit, at first obtain sampling clock through clock recovery circuitry, transmit data thereby then data are sampled correctly to sample.These circuit requirement input data are non-return-to-zero coding (NRZI), and circuit at first detects the saltus step on data edge through marginal detector, extract phase information then, at last through clock adjustment circuit output clock.But the design of simulated clock simulation clock data recovery circuit is comparatively complicated; Data-signal for burst can not satisfy requirement synchronously fast; The shake of big phase place causes the phase-locked loop losing lock easily; Phase lock loop lock on time is longer, and the recovery and the sampling of serial clock data only are provided, and parallel transfer of data solution is not provided.
Summary of the invention
The objective of the invention is to: a kind of high speed parallel interface circuit is provided, is intended to solve the problem that exists in the above-mentioned background technology.
The objective of the invention is to realize like this:
A kind of high speed parallel interface circuit comprises:
Receive the LVDS receiver module of data and shaping;
Be connected with the LVDS receiver module, the data of under a plurality of phase clocks, the LVDS receiver module being exported are carried out the data sampling module of over-sampling;
Be connected with data sampling module, in the over-sampling data of data sampling module output, select the optimum sampling data and recover the data recovery module of initial data through the NRZI decoding; And
Be connected the word synchronization module that the data that data recovery module is exported are shifted and adjust with data recovery module.
Said data sampling module comprises:
Produce the DLL phase-locked loop of the sampling clock of n phase place, said n is the integer greater than 1;
Be connected with the DLL phase-locked loop, the data of under a said n sampling clock, said LVDS receiver module being exported are carried out the over-sampling unit of over-sampling;
Be connected with the over-sampling unit, with the sample-synchronous unit in data sync to a clock zone of over-sampling unit output; And
Be connected the digital filter that the data of sample-synchronous unit output are carried out filtering with the sample-synchronous unit.
Said DLL phase-locked loop produces the sampling clock of n phase place based on the source synchronous clock signal.
Said sample-synchronous unit is also gone here and there the data of over-sampling unit output and is changed.
Said data recovery module comprises:
Detect the data edge detecting unit of the hopping edge of over-sampling data;
Be connected with the data edge detecting unit, draw the phase demodulation coding unit of the optimum sampling point of data according to the detected hopping edge of data edge detecting unit information;
Be connected with the phase demodulation coding unit with data sampling module, from the over-sampling data of data sampling module output, select the MUX of optimum sampling data according to the optimum sampling point of phase demodulation coding unit output; And
Be connected with MUX, the data of MUX output are carried out the NRZI decoding unit that NRZI decodes.
Said data edge detecting unit is carried out XOR through the data vector that the over-sampling data are formed and is obtained the detection of intermediate vector realization to over-sampling data hopping edge.
Store the look-up table of calculation Design in advance in the said phase demodulation coding unit, search output optimum sampling phase place expectation vector according to the intermediate vector of data edge detecting unit output; Said MUX is selected according to the optimum sampling phase place expectation vector of phase demodulation coding unit output, output optimum sampling data.
Said word synchronization module comprises displacement computing unit and asynchronous FIFO unit; Said displacement computing unit is used in the training stage based on preset synchronization character the asynchronous digital data that the receives adjustment that is shifted; Calculate and the storage carry digit; And data are shifted according to depositing carry digit in the normal data transfer stage, and the adjusted data that will be shifted write the asynchronous FIFO unit.
Said displacement computing unit also is used for after accomplishing displacement and calculating carry digit, producing the WrdRdy signal; Read signal to said asynchronous FIFO unit has all produced the WrdRdy signal at the displacement computing unit of each passage, and all WrdRdy signals are all effective effectively the time.
Said WrdRdy signal to each passage carries out logical AND to be handled and to obtain the AllRdy signal, when AllRdy effectively and synchronization character data are deposited in the said asynchronous FIFO unit when arriving; Read signal for said asynchronous FIFO unit is effective after effective at least one clock cycle at AllRdy.
Outstanding advantage of the present invention is: the present invention uses over-sampling and word locking phase to combine; The synchronous parallel data in source is accurately sampled recovery with synchronously; Through to the over-sampling data in real time dynamically synchronously, processing such as filtering, phase demodulation, selection, can realize real-time dynamicly, correctly sample and recover the data of valid window central authorities.
Description of drawings
Fig. 1 is the structure chart of the high speed parallel interface circuit that provides of the embodiment of the invention;
Fig. 2 is the structure chart of data sampling module in the high speed parallel interface circuit that provides of the embodiment of the invention;
Fig. 3 is the structure chart of data recovery module in the high speed parallel interface circuit that provides of the embodiment of the invention;
Fig. 4 is the structure chart of word synchronization module in the high speed parallel interface circuit that provides of the embodiment of the invention.
Embodiment
In order to make the object of the invention, technical scheme and advantage clearer,, the present invention is further elaborated below in conjunction with accompanying drawing and embodiment.Should be appreciated that specific embodiment described herein only in order to explanation the present invention, and be not used in qualification the present invention.
The transmission of high-speed parallel data is made up of a plurality of passages, and in embodiments of the present invention, the high speed parallel interface circuit structure of each passage is as shown in Figure 1.Each single channel (one digit number in the parallel data is according to the path) comprises that data sampling recovers (fine setting) and synchronous (coarse adjustment) two parts of word.
The data sampling recovered part comprises low-voltage differential signal (LVDS) receiver module 1, data sampling module 2 and the data recovery module 3 that electrically connects successively.LVDS receiver module 1 receives the data in each passage and carries out exporting after the shaping; Data sampling module 2 is carried out over-sampling to data under a plurality of phase clocks, data recovery module 3 is selected the optimum sampling data and recovered initial data through the NRZI decoding in the over-sampling data.Word synchronization module 4 makes the word alignment of each channel data through adjustment that the data that receive are shifted.
Under the initial condition; The word that at first each transmission channel is carried out coarse adjustment through training sequence is synchronous; To surpass the delay in one or half sampling clock cycle between the synchronizing channel; In the normal data transfer process after the system initialization training is accomplished, through the optimum sampling phase place of fine setting real-time and dynamic adjustment data.
Fig. 2 shows the structure of the above-mentioned data sampling module 2 that the embodiment of the invention provides, and comprises DLL phase-locked loop 21, over-sampling unit 22, sample-synchronous unit 23 and digital filter 24.
In embodiments of the present invention, DLL phase-locked loop 21 produces the sampling clock of the individual phase place of n (n is for greater than 1 integer, and for example n is 8,16 etc.) based on the source synchronous clock of LVDS receiver module 1 output (promptly send data terminal send with the road clock) signal.Over-sampling unit 22 carries out over-sampling to the high-speed serial data of LVDS receiver module 1 output under a said n sampling clock.Sample-synchronous unit 23 is handling in over-sampling data sync to a clock zone, after digital filter 24 is removed the burr that occurs in sudden change and the sampling of data in transmission.
The embodiment of the invention adopts bilateral along sampling; Each phase clock 4 bit data (divide 2 clock cycle accomplish) of sampling; In the sampled data synchronizing process; One (for example 0 phase clock) in n the phase clock that the said DLL phase-locked loop 21 of chosen in advance produces all is synchronized to all sampled datas under this phase clock.The string and the conversion of data also will be accomplished in said sample-synchronous unit 23 in carrying out the Synchronous Processing process of sampled data; The 4 Bits Serial data conversion that are about to each clock down-sampling gained are 4 channel parallel datas; Thereby both can reduce the clock frequency of data recovery process thereafter; Also be convenient to the word Synchronous Processing of training sequence thereafter, final sample-synchronous unit 23 is exported the 4*n bit data altogether.Should be appreciated that to those skilled in the art above-mentioned over-sampling also can adopt monolateral along the sampling realization.
The embodiment of the invention is utilized source synchronous clock to get into DLL phase-locked loop 21 and is produced each phase clock that over-sampling needs; Can avoid because transmitting terminal and receiving terminal clock frequency inequality and when data are recovered, carry out the insertion and the deletion of data; Utilize digital filter then can the burr signal that occur in sudden change that occur in the transmission path or the over-sampling be carried out filtering; For example can " 010 ", " 101 " etc. be filtered into " 000 ", " 111 ", thereby can reduce the complexity of data recovery module greatly.
Fig. 3 shows the structure of the above-mentioned data recovery module 3 that the embodiment of the invention provides, and comprises MUX 31, data edge detecting unit 32, phase demodulation coding unit 33 and NRZI decoding unit 34.
Over-sampling data behind digital filtering input to MUX 31 and data edge detecting unit 32.Data edge detecting unit 32 detects the hopping edge of over-sampling data; Phase demodulation coding unit 33 draws the optimum sampling point of data according to data edge detecting unit 32 detected hopping edge information; 31 of MUXs are selected the optimum sampling data according to this optimum sampling point and are exported from the over-sampling data of input, carry out the NRZI decoding by 34 pairs of these optimum sampling data of NRZI decoding unit and recover initial data.Said optimum sampling point in embodiments of the present invention, is the optimum sampling clock in the said n phase sample clock, and the clock that is in the centre of the corresponding sampling clock of the data of two adjacent generation hopping edges usually can be thought optimum sampling point.
As one embodiment of the present of invention, data vector E [e1, the e2 of data edge detecting unit 32 through the over-sampling data are formed;, en] carry out XOR and obtain intermediate vector X [x1, x2;, xn-1] and realize detection to over-sampling data hopping edge, wherein; En (n=1 ..., n) represent 4 bit data of n sampling clock down-sampling gained.Store the look-up table of calculation Design in advance in the phase demodulation coding unit 33, according to the intermediate vector X of data edge detecting unit 32 output search output optimum sampling phase place expect vectorial F [f1, f2 ..., fn].The optimum sampling phase place expectation vector that MUX 31 is exported according to phase demodulation coding unit 33 is shifted and selects, and finally exports 4 optimum sampling data.To those skilled in the art, can be as required flexibly to phase demodulation coding unit 33 modification of encoding, thereby the maximum likelihood value of finding out the optimum sampling phase place is to satisfy the demand of circuit.
Each channel data provides the DatRdy signal after recovering to accomplish, and control word synchronization module 4 can carry out Synchronous Processing to data.The structure of said word synchronization module 4 is as shown in Figure 4, comprises displacement computing unit 41 and the asynchronous FIFO unit of handling based on stream 42.
Under initial condition, transmitting terminal will send the training sequence data of predetermined certain series, for example, be one group with " 0000_0000_0011_1111_1111 " and will repeatedly send.Displacement computing unit 41, calculates and also store the figure place of being moved, and the adjusted data that will be shifted writes asynchronous FIFO unit 42 the asynchronous digital data that the receives adjustment that is shifted based on preset synchronization character.For example, preset synchronization character is " 0011 ", is " 0001 " when receiving parallel data, and the computing unit 41 that then is shifted moves to left one with data.Displacement computing unit 41 will produce the WrdRdy signal after accomplishing displacement and calculating carry digit; When the displacement computing unit 41 of each passage has all produced the WrdRdy signal; And all WrdRdy signals are all effectively the time, the control unit that triggers receiving terminal are read the data in the asynchronous FIFO unit 42 of each passage.As a preferred embodiment of the present invention; To carry out the logical AND processing to the WrdRdy signal that each passage produces and obtain the AllRdy signal; When AllRdy effectively and synchronization character data are deposited in the asynchronous FIFO unit 42 when arriving, for the read signal of asynchronous FIFO unit 42 then be preferably in AllRdy effectively after at least one clock cycle effectively.After training was accomplished, during normal data transfer, displacement computing unit 41 calculates gained in the time of will be according to training carry digit was to the data that the receive adjustment that is shifted.Above-mentioned training sequence data, synchronization character and shifting function can design arbitrarily, do not receive above-mentioned the limit.
The high speed parallel interface circuit that the embodiment of the invention provides uses over-sampling and word locking phase to combine, and the synchronous parallel data in source is accurately sampled recover with synchronously.Through to the over-sampling data in real time dynamically synchronously, processing such as filtering, phase demodulation, selection, can realize real-time dynamicly, correctly sample and recover the data of valid window central authorities, and can not receive the influence of ambient temperature, humidity, interference etc.Compared with prior art, adopt the source clock synchronized to carry out over-sampling, can avoid in the over-sampling process, need carry out the insertion and the deletion of data owing to clock jitter; Adopt the over-sampling data sampling to recover and the synchronous method of synchronization of word has higher bandwidth for transmission ability, lower stand-by period, to postponing the stronger advantage of tolerance between shake and transmission channel; Behind over-sampling, use digital filter, can remove the burst saltus step and sampling burr of sampled data, make system's adaptive capacity higher.
The above is merely preferred embodiment of the present invention, not in order to restriction the present invention, all any modifications of within spirit of the present invention and principle, being done, is equal to and replaces and improvement etc., all should be included within protection scope of the present invention.
Claims (10)
1. a high speed parallel interface circuit is characterized in that, comprising:
Receive the LVDS receiver module of data and shaping;
Be connected with the LVDS receiver module, the data of under a plurality of phase clocks, the LVDS receiver module being exported are carried out the data sampling module of over-sampling;
Be connected with data sampling module, in the over-sampling data of data sampling module output, select the optimum sampling data and recover the data recovery module of initial data through the NRZI decoding; And
Be connected the word synchronization module that the data that data recovery module is exported are shifted and adjust with data recovery module.
2. high speed parallel interface circuit as claimed in claim 1 is characterized in that, said data sampling module comprises:
Produce the DLL phase-locked loop of the sampling clock of n phase place, said n is the integer greater than 1;
Be connected with the DLL phase-locked loop, the data of under a said n sampling clock, said LVDS receiver module being exported are carried out the over-sampling unit of over-sampling;
Be connected with the over-sampling unit, with the sample-synchronous unit in data sync to a clock zone of over-sampling unit output; And
Be connected the digital filter that the data of sample-synchronous unit output are carried out filtering with the sample-synchronous unit.
3. high speed parallel interface circuit as claimed in claim 2 is characterized in that, said DLL phase-locked loop produces the sampling clock of n phase place based on the source synchronous clock signal.
4. high speed parallel interface circuit as claimed in claim 2 is characterized in that, said sample-synchronous unit is also gone here and there the data of over-sampling unit output and changed.
5. high speed parallel interface circuit as claimed in claim 1 is characterized in that, said data recovery module comprises:
Detect the data edge detecting unit of the hopping edge of over-sampling data;
Be connected with the data edge detecting unit, draw the phase demodulation coding unit of the optimum sampling point of data according to the detected hopping edge of data edge detecting unit information;
Be connected with the phase demodulation coding unit with data sampling module, from the over-sampling data of data sampling module output, select the MUX of optimum sampling data according to the optimum sampling point of phase demodulation coding unit output; And
Be connected with MUX, the data of MUX output are carried out the NRZI decoding unit that NRZI decodes.
6. high speed parallel interface circuit as claimed in claim 5 is characterized in that, said data edge detecting unit is carried out XOR through the data vector that the over-sampling data are formed and obtained the detection of intermediate vector realization to over-sampling data hopping edge.
7. high speed parallel interface circuit as claimed in claim 6 is characterized in that, stores the look-up table of calculation Design in advance in the said phase demodulation coding unit, searches output optimum sampling phase place expectation vector according to the intermediate vector of data edge detecting unit output; Said MUX is selected according to the optimum sampling phase place expectation vector of phase demodulation coding unit output, output optimum sampling data.
8. high speed parallel interface circuit as claimed in claim 1; It is characterized in that; Said word synchronization module comprises displacement computing unit and asynchronous FIFO unit, and said displacement computing unit is used in the training stage based on preset synchronization character the asynchronous digital data that the receives adjustment that is shifted, and carry digit is also stored in calculating; And data are shifted according to depositing carry digit in the normal data transfer stage, and the adjusted data that will be shifted write the asynchronous FIFO unit.
9. high speed parallel interface circuit as claimed in claim 8 is characterized in that, said displacement computing unit also is used for after accomplishing displacement and calculating carry digit, producing the WrdRdy signal; Read signal to said asynchronous FIFO unit has all produced the WrdRdy signal at the displacement computing unit of each passage, and all WrdRdy signals are all effective effectively the time.
10. high speed parallel interface circuit as claimed in claim 9 is characterized in that, said WrdRdy signal to each passage carries out logical AND to be handled and to obtain the AllRdy signal, when AllRdy effectively and synchronization character data are deposited in the said asynchronous FIFO unit when arriving; Read signal for said asynchronous FIFO unit is effective after effective at least one clock cycle at AllRdy.
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