CN101692218A - High-speed data transmission method - Google Patents

Abstract

The invention provides a high-speed data transmission method. The method comprises: performing splitting, coding and parallel-serial transformation on high-speed data at a sending end and then transmitting the high-speed data to a plurality of serial channels; and performing serial-parallel transformation, decoding, buffering/synchronization and data combination on the data of the serial channels at a receiving end and then restoring the data to the sent high-speed data. The transmission rate of data is raised through parallel-serial and serial-parallel transformation. By adopting dual-clock FIFO when data is buffered/synchronized, the problem that the serial channels are possible to be inconsistent in line length is solved so as to realize synchronous data transmission. The method is of great importance to raise data transmission rate and solve the problems of multi-processor information transmission in high-speed transmission and synchronization.

Description

A method for high-speed data transmission

technical field

The invention relates to a high-speed data transmission method in the communication field.

Background technique

In the field of communication, with the development of high-speed processors, multimedia and other technologies, and the continuous improvement of communication requirements, the requirements for signal bandwidth are increasing, and the requirements for real-time data are also increasing. Therefore, the requirements for data transmission rates are also increasing. Gradually improve. At the same time, as the processor develops to a multi-core structure, the high-speed transmission and communication outside the multi-core processor has also become a problem that needs to be solved for the further development of the processor.

Many current studies focus on the interface research between multiprocessors, such as the use of PCI front side bus, LVDS interface standard, VME bus and so on. These methods increase the communication speed in terms of improving the communication speed, but all require special hardware support. The existing technology that does not use a special bus is generally single-channel transmission, which cannot meet the problem of a large increase in signal bandwidth and the number of signal channels and the transmission of large amounts of data. In order to improve the data communication rate, the present invention can achieve Multi-channel high-speed data transmission does not limit the physical wiring length of each channel, and does not require special hardware support, and can be dynamically adjusted and expanded according to the bandwidth.

Contents of the invention

The purpose of the present invention is to provide a high-speed data transmission method to increase the data transmission rate.

Technical scheme of the present invention is realized like this:

A high-speed data transmission method, the implementation steps are:

(1) The high-speed data is split, encoded, parallel-to-serial converted at the sending end and then transmitted to multiple serial channels;

(2) Perform serial-to-parallel conversion, decoding, buffering/synchronization, and data merging on the data of multiple serial channels at the receiving end, and then restore the sent high-speed data.

The split processing flow in step (1) is split at a constant speed, and the length of the sent high-speed data must be an integer multiple of the serial channel. The encoding processing flow is 8B/10B encoding.

The decoding processing flow in step (2) is 8B/10B decoding. The buffer/synchronization process uses a dual-clock FIFO with the same number of serial channels as a buffer/synchronization device; the data at the writing end of the dual-clock FIFO comes from the decoded data of each serial channel, and the clock at the writing end is serial-to-parallel conversion from the serial channel The recovered clock WR_Clk has the same frequency; the reading end of the dual-clock FIFO uses the same read clock RD_Clk, and its frequency is consistent with the frequency of the write clock; the read enable RD_Ena signal is the NOR gate output of all dual-clock FIFO empty states ,, when all FIFOs are non-empty, the read enable is valid, and data is read from the dual clock FIFO. When the FIFO is empty, the read enable is invalid, and the FIFO read operation is stopped, so that the read data is the sender’s Data; the FIFO depth must be greater than the transmission information delay difference of each channel to ensure the synchronization of data transmission and the interval between two data transmissions must be greater than the transmission information delay difference of each channel. The data read from each dual clock can be combined to restore the sent data.

Description of drawings

Figure 1 is a flow chart of data processing at the sending end;

Fig. 2 is a flow chart of data processing at the receiving end;

FIG. 3 is a diagram of a data buffer synchronization process in the data processing flow of the receiving end in FIG. 2 .

Detailed ways

A preferred embodiment of the present invention is described as follows in conjunction with accompanying drawing:

This embodiment realizes the high-speed multi-channel data transmission between the data sending end and the receiving end.

Figure 1 is a flow chart of data processing at the sending end. It can be seen from Figure 1 that the sending end needs to perform a series of processing on the high-speed data, followed by splitting, encoding, parallel-to-serial conversion, and then transmit the processed data to multiple serial channels. Among them, the splitting processing flow is equal-speed splitting, which divides the data into several transmission channels with the same transmission rate, and the length of the high-speed data to be sent must be an integer multiple of the transmission channel. The encoding process is 8B/10B encoding to realize differential signal clock extraction and data transmission error correction.

Figure 2 is a flow chart of data processing at the receiving end. It can be seen from Figure 2 that a series of processing is performed on the data of multiple serial channels at the receiving end, followed by serial-to-parallel conversion, decoding, buffering/synchronization, and data merging, and then restores the sent high-speed data. The decoding processing flow is 8B/10B decoding.

FIG. 3 is a diagram of a data buffer synchronization process in the data processing flow of the receiving end in FIG. 2 . The buffer/synchronization process uses a dual-clock FIFO with the same number of serial channels as a buffer/synchronization device; the data at the writing end of the dual-clock FIFO comes from the decoded data of each serial channel, and the clock at the writing end is serial-to-parallel conversion from the serial channel The recovered clocks WR_Clk1, WR_Clk2...WR_ClkN have the same frequency of each write clock. The readout end of the dual-clock FIFO uses the same read clock RD_Clk, whose frequency is consistent with the write clock frequency. The signals Emp1, Emp2, . . . , EmpN for judging whether each FIFO is empty can be directly obtained from the FIFO, as shown in FIG. 3 , and the read enable RD_Ena signal is obtained after these signals pass through the NOR gate. When all FIFOs are non-empty, the read enable is valid, and data is read from the dual-clock FIFO; when any FIFO is empty, the read enable is invalid, and the FIFO read operation is stopped. In actual transmission, there are situations where the transmission distances of multiple serial transmission channels are different. Even in this case, the above method can achieve transmission synchronization, but the FIFO depth must be greater than the transmission information delay difference of each channel, and the interval between two data transmissions is also It needs to be greater than the transmission information delay difference of each channel. The data processed through the above process can be restored at the receiving end to the data at the sending end through data merging.

The above description is a preferred embodiment of the present invention, and is not intended to limit this embodiment. Any modifications, equivalent replacements and improvements made within the spirit and principles of the present invention are included in the protection scope of the present invention. Inside.

Claims (6)

1. A method for high-speed data transmission, characterized in that the steps for realizing are: 1) The high-speed data is split, encoded, parallel-to-serial converted at the sending end and then transmitted to multiple serial channels; 2) Perform serial-to-parallel conversion, decoding, buffering/synchronization, and data merging on the data of multiple serial channels at the receiving end, and then restore the sent high-speed data. 2. The data high-speed transmission method according to claim 1, characterized in that the split processing flow in the step (1): carry out constant speed split, and the length of sending high-speed data needs to be an integer multiple of the serial channel . 3. The high-speed data transmission method according to claim 1, characterized in that the encoding process performed in the step (1) is: 8B/10B encoding. 4. The high-speed data transmission method according to claim 1, characterized in that the decoding processing flow in the step (2) is: 8B/10B decoding. 5. the data high-speed transmission method according to claim 1 is characterized in that in the described step (2), the buffering/synchronization processing flow: adopt the double clock FIFO identical with serial channel number as buffering/synchronization equipment; Double clock FIFO The data at the writing end comes from the decoded data of each serial channel, and the clock at the writing end is the clock WR_Clk recovered from the serial channel by serial-to-parallel conversion, and its frequency is the same; The frequency is consistent with the write clock frequency; the read enable RD_Ena signal is the NOR gate output of all dual-clock FIFO empty states. When all FIFOs are non-empty, the read enable is valid, and data is read from the dual-clock FIFO. When FIFO When it is empty, the read enable is invalid, and the FIFO read operation is stopped, so that the read data is the data of the sending end; the FIFO depth must be greater than the transmission information delay difference of each channel to ensure the synchronization of data transmission. 6. The buffering/synchronization processing flow according to claim 5, characterized in that the interval between two data transmissions needs to be greater than the delay difference of transmission information of each channel.

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