CN103888693A - Image transmission device - Google Patents
Image transmission device Download PDFInfo
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- CN103888693A CN103888693A CN201410129037.4A CN201410129037A CN103888693A CN 103888693 A CN103888693 A CN 103888693A CN 201410129037 A CN201410129037 A CN 201410129037A CN 103888693 A CN103888693 A CN 103888693A
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Abstract
The invention discloses an image transmission device. A path of image signals are transmitted simultaneously by means of multiple paths of high-speed serial transceivers, due to the fact that bandwidth requirements of the high-speed serial transceivers are not high, the high-speed serial transceivers with low band widths can be used for transmission, and compared with a video encoding and decoding chip transmission mode, the image transmission device saves cost. When bandwidths of input image data such as high-definition signals and 3D signals are high, transmission can be completed through increase of the number of the high-speed serial transceivers. According to the image transmission device, phase synchronization encoding is carried out on image signals at the transmitting end, phase synchronization among the multiple paths of transceivers is guaranteed at the receiving end by means of corresponding measures, and the blurred screen phenomenon caused by dislocation of the image data is avoided.
Description
Technical field
The present invention relates to technical field of image processing, particularly relate to a kind of image transmission.
Background technology
In image processing field, usually need picture signal to be transferred to another processing unit from a processing unit.The method that present stage adopts is generally to pass through video coding chip, the video decoding chip of another processing unit will be sent after image signal encoding, video decoding chip will be processed for local signal after signal decoding, this method needs the extra coding and decoding video chip that increases conventionally, increased the cost of product, the size of transmitting image is subject to the restriction of coding and decoding video chip bandwidth simultaneously.
Summary of the invention
Based on above-mentioned situation, the present invention proposes a kind of image transmission, to reduce the cost of image transmitting, ensure transmission quality simultaneously.For this reason, the scheme of employing is as follows.
A kind of image transmission, comprises transmitting terminal and receiving terminal,
Described transmitting terminal comprises that signal selector, polarity unifies module, clock zone modular converter, Phase synchronization coding module, and multiple high speed serialization transmitter;
Described receiving terminal comprises multiple high-speed serial receivers, Phase synchronization module and local signal processing unit;
The number of described high-speed serial receiver and described high-speed serial receiver and the resolution of picture signal to be transmitted and frame per second adapt;
Described signal selector is sent to described polarity by selecteed picture signal and unifies module, it is positive polarity or negative polarity by the polarity unification of the field sync signal of picture signal and line synchronizing signal that described polarity is unified module, polarity picture signal is after reunification transformed into high speed serialization transmitter parallel data input clock territory by described clock zone modular converter, described Phase synchronization coding module inserts Synchronization Control code the starting position alternate image data of the field synchronization head of each, multiple described high speed serialization transmitters transfer to multiple described high-speed serial receivers by transmission link jointly by the picture signal after Phase synchronization coding,
The multiway images data that receive are sent to described Phase synchronization module by multiple described high-speed serial receivers, described Phase synchronization module judges whether to read the Synchronization Control code of multiway images data simultaneously, if multiway images data are mail to described local signal processing unit, multiway images data are carried out to Phase synchronization processing if not, then mail to described local signal processing unit.
Image transmission of the present invention, adopt multipath high-speed serial transceiver transmission of one line picture signal simultaneously, due to not high to the bandwidth requirement of high speed serialization transceiver, can use the high speed serialization transceiver of low bandwidth to transmit, compare the mode that adopts the transmission of coding and decoding video chip, reduced cost.When input image data bandwidth is higher, as ultra high-definition resolution signal, 3D signal etc., can complete transmission by the quantity that increases high speed serialization transceiver.This device also carries out Phase synchronization coding at transmitting terminal to picture signal, adopts corresponding measure to ensure Phase synchronization between multichannel transceiver at receiving terminal, the flower screen phenomenon of avoiding view data dislocation to cause.
Brief description of the drawings
Fig. 1 is the structural representation of image transmission of the present invention;
Fig. 2 is the structural representation of clock zone modular converter in image transmission of the present invention;
Fig. 3 is the structural representation of two FIFO memories of Phase synchronization module in image transmission of the present invention;
Fig. 4 is that Phase synchronization module is carried out phase locked schematic flow sheet.
Embodiment
In order to make object of the present invention, technical scheme and advantage clearer, below in conjunction with drawings and Examples, the present invention is described in further detail.Should be appreciated that embodiment described herein, only in order to explain the present invention, does not limit protection scope of the present invention.
The structure of image transmission of the present invention as shown in Figure 1, the multiway images signal of transmitting terminal selects a road to send by signal selector, selecteed picture signal is input to polarity and unifies module, due to different input signal sources, the field sync signal of picture signal and the polarity of line synchronizing signal may be different, for convenience of back end signal processing, field sync signal and line synchronizing signal unification need be converted to positive polarity or negative polarity.
Picture signal after polarity conversion is input to clock zone modular converter, because the picture signal of input can be the signal of various resolution, the picture signal pixel clock of different resolution is different, and high speed serialization transceiver is in the situation that bandwidth is certain, the input clock of parallel data is determined, the picture signal of input must be transformed into high speed serialization transceiver parallel data input clock territory for completing transmission.
The structure of clock zone modular converter as shown in Figure 2, comprise that one is write control module, two FIFO and a read control module, write control module and be written to FIFO_a according to the odd-numbered line of the line synchronizing signal control view data of input image data, even number line is written to FIFO_b, read control module is according to alternately reads image data from FIFO_a and FIFO_b of the line synchronizing signal of input image data, in the time writing control module and write FIFO_a, read control module reads FIFO_b, in the time writing control module and write FIFO_b, read control module reads FIFO_a.For ensureing that picture signal (comprises field sync signal, line synchronizing signal, data useful signal and viewdata signal) all carry out clock zone conversion, the width of two FIFO is all necessary for field sync signal, line synchronizing signal, the width sum of data useful signal and viewdata signal, the degree of depth must be greater than the total pixel of row of ultimate resolution image in received image signal, the pixel clock of writing control module received image signal carries out write operation, read control module is carried out read operation with high speed serialization transceiver parallel data input clock, thereby complete the conversion of image clock signal territory.
Picture signal through oversampling clock conversion need be carried out Phase synchronization coding, and the data phase that the Synchronization Control code adding receives multipath high-speed serial received device for receiving terminal carries out synchronously.Control code is in the starting position of the field synchronization head of each alternate image data, and every road high speed serialization transmitter sends identical control code simultaneously.
Picture signal after Phase synchronization coding is transferred to the high speed serialization transceiver receiving terminal of another signal processing unit by transmission link by multipath high-speed serial transmitter.Need how many roads high speed serialization transceiver to be determined by the bandwidth of picture signal, the bandwidth sum of high speed serialization transceiver must be greater than the bandwidth of picture signal.Because the parameters such as cable and impedance that on pcb board, wiring can not ensure two-way link and length are consistent, may cause two paths of data asynchronous in the time that receiving terminal receives for high-speed data, thereby cause image signal data to misplace.
The high-speed serial receiver of receiving terminal is input to Phase synchronization module after receiving picture signal, and Phase synchronization module is by judging whether control code out completes synchronously from multipath reception device end solution simultaneously.
As shown in Figure 3, here taking two-way high speed serialization transceiver as example, Phase synchronization module comprises two FIFO to the structure of Phase synchronization module.After receiving data, two receiving terminals are written to respectively FIFO_0 and FIFO_1, the link link more corresponding than FIFO_1 that FIFO_0 is corresponding as we can see from the figure fallen behind a clock cycle, FIFO_0 is a high position for view data, FIFO_1 is the low level of view data, from FIFO_0 and FIFO_1, sense data can cause high-low-position dislocation after merging, and cannot restore image.
Phase synchronization module completes the synchronous of multiple high speed serialization transceiver link according to the flow process shown in Fig. 4:
1, first judge whether to read Synchronization Control code from FIFO_0 and FIFO_1 simultaneously, if it is synchronous reading two links of explanation simultaneously, do not do Phase synchronization processing, because Synchronization Control code is to insert in the mode of alternate image data in the starting position of each field synchronization, this time, if it is negative polarity by the polarity unification of the field sync signal of picture signal and line synchronizing signal that described polarity is unified module, field sync signal, line synchronizing signal, view data useful signal and picture signal are all 0, in the time receiving Synchronization Control code, can think that the data that receive are 0, thereby not affecting image signal data recovers.If it is positive polarity by the polarity unification of the field sync signal of picture signal and line synchronizing signal that described polarity is unified module, field sync signal and line synchronizing signal are 1, view data useful signal and picture signal are still 0, in the time receiving Synchronization Control code, can think in the data that receive that line synchronizing signal and field sync signal data bit are 1, other positions are 0, do not affect equally image signal data and recover.
2, if not read Synchronization Control code simultaneously, illustrate that two links are asynchronous, enable to write end and prepare reset FIFO.
3, when FIFO_0 writes end in the time receiving the Synchronization Control code of next field duration transmission, reset FIFO_0; When FIFO_0 writes end in the time receiving the Synchronization Control code of next field duration transmission, reset FIFO_1;
4, the rear horse back that resetted writes the data immediately following Synchronization Control code.
5, in the time that the data bulk in FIFO_0 and FIFO_1 is greater than the threshold value of setting simultaneously, read the data in FIFO_0 and FIFO_1 simultaneously, ensure the reading out data 1 simultaneously from two FIFO, complete data phase synchronous.
Two FIFO degree of depth are relevant with the difference of two links with read threshold, if the parameter such as two link impedances and length differs larger, the FIFO degree of depth and read threshold need arrange larger.Because all can do isometric design as the parallel high speed serialization transceiver using in hardware designs, so difference is generally not too large.
Compared with prior art, the advantage of this image transmission is as follows:
1, because present stage has the logical device price of high speed serialization transceiver and there is no being more or less the same of high speed serialization transceiver, cost is lower than increasing coding and decoding video chip.
The image signal data that 2, can use the high-speed transceiver transmission high bandwidth of low bandwidth, has further reduced cost.
3, can automatically complete multipath high-speed serial transceiver data phase synchronous, the image flower screen phenomenon of avoiding view data to misplace causing.
The above embodiment has only expressed several execution mode of the present invention, and it describes comparatively concrete and detailed, but can not therefore be interpreted as the restriction to the scope of the claims of the present invention.It should be pointed out that for the person of ordinary skill of the art, without departing from the inventive concept of the premise, can also make some distortion and improvement, these all belong to protection scope of the present invention.Therefore, the protection range of patent of the present invention should be as the criterion with claims.
Claims (5)
1. an image transmission, is characterized in that, comprises transmitting terminal and receiving terminal,
Described transmitting terminal comprises that signal selector, polarity unifies module, clock zone modular converter, Phase synchronization coding module, and multiple high speed serialization transmitter;
Described receiving terminal comprises multiple high-speed serial receivers, Phase synchronization module and local signal processing unit;
The number of described high-speed serial receiver and described high-speed serial receiver and the resolution of picture signal to be transmitted and frame per second adapt;
Described signal selector is sent to described polarity by selecteed picture signal and unifies module, it is positive polarity or negative polarity by the polarity unification of the field sync signal of picture signal and line synchronizing signal that described polarity is unified module, polarity picture signal is after reunification transformed into high speed serialization transmitter parallel data input clock territory by described clock zone modular converter, described Phase synchronization coding module inserts Synchronization Control code the starting position alternate image data of the field synchronization head of each, multiple described high speed serialization transmitters transfer to multiple described high-speed serial receivers by transmission link jointly by the picture signal after Phase synchronization coding,
The multiway images data that receive are sent to described Phase synchronization module by multiple described high-speed serial receivers, described Phase synchronization module judges whether to read the Synchronization Control code of multiway images data simultaneously, if multiway images data are mail to described local signal processing unit, multiway images data are carried out to Phase synchronization processing if not, then mail to described local signal processing unit.
2. image transmission according to claim 1, is characterized in that,
Described clock zone modular converter comprises writes control module, read control module and two FIFO memory: FIFO_a, FIFO_b;
The described control module of writing is written to FIFO_a according to the odd-numbered line of the line synchronizing signal control chart image signal of picture signal, even number line is written to FIFO_b, described read control module is according to alternately reading images signal from FIFO_a and FIFO_b of the line synchronizing signal of picture signal, when described when writing control module and write FIFO_a, read control module reads FIFO_b, when described when writing control module and writing FIFO_b, described read control module reads FIFO_a, the width of two FIFO memories is field sync signal, line synchronizing signal, the width sum of data useful signal and viewdata signal, the degree of depth is greater than the total pixel of row of ultimate resolution image in picture signal to be transmitted, the described pixel clock of writing control module picture signal carries out write operation, described read control module is carried out read operation with high speed serialization transmitter parallel data input clock, thereby complete the conversion of image clock signal territory.
3. image transmission according to claim 1 and 2, is characterized in that,
Described Phase synchronization module comprises multiple FIFO memories and synchronous processing module, high-speed serial receiver described in the corresponding road of each FIFO memory, be used for storing a road view data, described synchronous processing module reads Synchronization Control code from each FIFO memory, judge that multiway images data are synchronous if read simultaneously, judge that multiway images data are asynchronous if can not read simultaneously, in the time that one of them FIFO memory receives the Synchronization Control code of next field duration transmission, other FIFO memories reset, after completing, reset writes Synchronization Control code data afterwards.
4. image transmission according to claim 3, is characterized in that,
In described Phase synchronization module, in the time that the data bulk in multiple FIFO memories is greater than the threshold value of setting simultaneously, described synchronous processing module reads the data in multiple FIFO memories simultaneously.
5. image transmission according to claim 4, is characterized in that,
In described Phase synchronization module, the degree of depth of multiple FIFO memories and described threshold value increase along with the increase of the difference of impedance between transmission link and length.
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| CN201410129037.4A CN103888693B (en) | 2014-03-31 | 2014-03-31 | Image transmission |
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Cited By (9)
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| CN104349016A (en) * | 2014-10-31 | 2015-02-11 | 广东威创视讯科技股份有限公司 | High-definition image data transmission method and system |
| CN104378648A (en) * | 2014-10-31 | 2015-02-25 | 广东威创视讯科技股份有限公司 | Image coding, decoding and transmitting method and system |
| CN105657318A (en) * | 2016-01-04 | 2016-06-08 | 广东威创视讯科技股份有限公司 | Video transmission method and device based on LVDS signal |
| CN109639957A (en) * | 2017-10-05 | 2019-04-16 | 印芯科技股份有限公司 | Image data transmission system and image data transfer method |
| CN109862210A (en) * | 2019-03-26 | 2019-06-07 | 中国科学院长春光学精密机械与物理研究所 | The acquisition of multispectral section of serial image data of multichannel receives system |
| CN110636219A (en) * | 2019-09-03 | 2019-12-31 | 北京三快在线科技有限公司 | Video data stream transmission method and device |
| CN111133741A (en) * | 2019-12-17 | 2020-05-08 | 威创集团股份有限公司 | Video signal synchronization method, device and system for splicing wall |
| CN113038069A (en) * | 2019-12-25 | 2021-06-25 | 初速度（苏州）科技有限公司 | Data transmission system |
| CN114758606A (en) * | 2020-12-29 | 2022-07-15 | 杭州海康威视数字技术股份有限公司 | Sending method of field synchronization signal, controller and display control system |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105657318B (en) * | 2016-01-04 | 2018-08-07 | 广东威创视讯科技股份有限公司 | Video transmission method based on LVDS signals and device |
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| CN109862210B (en) * | 2019-03-26 | 2020-12-25 | 中国科学院长春光学精密机械与物理研究所 | Acquisition and receiving system for multi-path and multi-spectral-band serial image data |
| CN110636219A (en) * | 2019-09-03 | 2019-12-31 | 北京三快在线科技有限公司 | Video data stream transmission method and device |
| CN111133741A (en) * | 2019-12-17 | 2020-05-08 | 威创集团股份有限公司 | Video signal synchronization method, device and system for splicing wall |
| CN111133741B (en) * | 2019-12-17 | 2021-06-15 | 威创集团股份有限公司 | Video signal synchronization method, device and system for splicing wall |
| WO2021119967A1 (en) * | 2019-12-17 | 2021-06-24 | 威创集团股份有限公司 | Method, device, and system for mosaic wall video signal synchronization |
| CN113038069A (en) * | 2019-12-25 | 2021-06-25 | 初速度（苏州）科技有限公司 | Data transmission system |
| CN114758606A (en) * | 2020-12-29 | 2022-07-15 | 杭州海康威视数字技术股份有限公司 | Sending method of field synchronization signal, controller and display control system |
| CN114758606B (en) * | 2020-12-29 | 2023-09-26 | 杭州海康威视数字技术股份有限公司 | Method for transmitting field synchronizing signal, controller and display control system |
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