CN108121676B - Circuit for converting digital signal parallel input into serial output - Google Patents
Circuit for converting digital signal parallel input into serial output Download PDFInfo
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
- G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
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- G—PHYSICS
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/38—Universal adapter
- G06F2213/3852—Converter between protocols
Abstract
The invention discloses a digital signal parallel input-to-serial output circuit, which is formed by assembling at least two parallel-to-serial data processing units, a frame clock generating unit, a data clock generating unit and a synchronizing unit. The method comprises the steps of dividing parallel digital signals into at least two groups of parallel data, converting the at least two groups of parallel data to form serial data output, dividing the digital signals into at least two groups of parallel data, performing parallel-serial conversion to enable the serial output data not to be limited by the LVDS interface speed in the prior art, adjusting the time sequence in the process of converting parallel input into serial output by utilizing at least two groups of serial data with completely synchronous time sequence, frame clock signals with completely synchronous time sequence and data clock signals with completely synchronous time sequence, enabling an external receiving unit to accurately and quickly receive the parallel digital signals, and avoiding the problems that an external receiving unit in the prior art is difficult to receive data, and the time sequence is easy to generate errors in the receiving process.
Description
Technical Field
The invention relates to the field of high-speed and high-precision data processing, in particular to a circuit for converting parallel input of digital signals into serial output of the digital signals.
Background
With the continuous improvement of the sampling rate of a high-speed high-precision Analog-to-Digital Converter (ADC), the data output rate of the ADC is synchronously improved. The conventional CMOS digital interface logic cannot meet the application requirements of the high-speed ADC, and in order to solve the limitation of the data transmission rate, a parallel Low Voltage Differential Signaling (LVDS) output interface is widely used in the high-speed ADC output interface. With the improvement of ADC resolution and the application requirement of multi-channel integration, the number of output pins required by adopting a parallel output technology is too large, the design complexity of chip packaging and system PCB connecting lines is greatly increased, the number of data output pins is greatly less by adopting a serial LVDS output interface format, and the difficulty caused by the too large number of output pins can be effectively solved. In order to use a serial output interface to output data, digital codes generated by an ADC (analog to digital converter) must be converted into serial code streams firstly, digital signals with multiple bits are converted into a group of serial outputs, the converted serial outputs may exceed the maximum transmission rate of a subsequent serial interface due to the fact that the data transmission rate is too high, in order to solve the limitation of the transmission rate of the serial interface, the digital signals can be divided into multiple groups to be processed in parallel and serial, corresponding clock signals are required to be generated for receiving serial data outside a chip while the digital signals are processed in parallel and serial, the converted serial data is faster in speed, the difficulty of receiving data outside the chip is increased, the output serial code streams and the clock signals for receiving data outside the chip are required to ensure a relatively accurate time sequence relation, and higher requirements are provided for the system time sequence.
Disclosure of Invention
The invention aims to solve the problems that when the digital signal is input and output in parallel, the serial output is easily limited by the speed of a serial interface, the data is difficult to be received outside a chip, the time sequence error is easy to occur in the receiving process and the like in the prior art; a circuit for converting parallel input of digital signals into serial output of digital signals is provided.
In order to achieve the purpose, the invention is realized by the following technical scheme:
a digital signal parallel input-to-serial output circuit divides parallel digital signals into at least two groups of parallel data; the circuit includes:
each parallel-serial data processing unit converts a corresponding group of parallel data into a group of serial data and then outputs the serial data;
a frame clock generating unit for inputting a first forming input code and converting and outputting a frame clock signal;
a data clock generating unit for inputting the second forming input code and converting and outputting the serial second forming input code;
the synchronization unit is used for respectively inputting at least two groups of serial data, the frame clock signal and the serial second forming input code, outputting at least two groups of serial data with completely synchronous time sequence, the frame clock signal with completely synchronous time sequence and the data clock signal with completely synchronous time sequence after processing, and sending the signals to an external receiving unit;
the frame clock signal having a completely synchronous timing controls the external receiving unit to acquire at least two corresponding sets of the serial data forming the parallel digital signal; the data clock signal with fully synchronous timing controls the external receiving unit to recover the respective at least two sets of serial data into the parallel digital signal.
Preferably, each of the parallel-serial data processing units includes:
and the first parallel-serial converter is used for respectively inputting a first clock signal, a second clock signal and a corresponding group of parallel data and converting the parallel data into a group of serial data.
Preferably, the frame clock generating unit includes:
a second parallel-to-serial converter which inputs the first clock signal, the second clock signal, and the first forming input code, respectively, and converts the first forming input code into a serial first forming input code;
and a frame clock output mode controller which inputs the serial first forming input code and the frame clock control code and outputs the frame clock signal.
Preferably, the data clock generating unit includes:
and a third parallel-to-serial converter which inputs the first clock signal, the second clock signal, and the second forming input code, respectively, and converts the second forming input code into a serial second forming input code.
Preferably, the synchronization unit includes:
a first synchronization subunit which inputs a third clock signal, at least two sets of the serial data, the frame clock signal, and the serial second formation input code, performs first synchronization timing processing, and outputs at least two sets of the serial data having a first synchronization timing, the frame clock signal having a first synchronization timing, and the serial second formation input code having a first synchronization timing, respectively;
and the second synchronization subunit is used for respectively inputting the second clock signal, the fourth clock signal, the at least two groups of serial data with the first time synchronization timing sequence, the frame clock signal with the first time synchronization timing sequence and the second formation input code of the serial data with the first time synchronization timing sequence, performing second time synchronization timing sequence processing, and outputting the at least two groups of serial data with the complete synchronization timing sequence, the frame clock signal with the complete synchronization timing sequence and the data clock signal with the complete synchronization timing sequence after processing.
Preferably, the first synchronization subunit comprises:
at least two first synchronous processors, wherein each first synchronous processor respectively inputs the third clock signal and a corresponding group of serial data, carries out first synchronous processing on the corresponding group of serial data and outputs a group of serial data with first synchronous time sequence;
the second synchronous processor is used for respectively inputting the frame clock signal and the third clock signal, carrying out first synchronous processing on the frame clock signal and outputting the frame clock signal with the first synchronous time sequence;
a third synchronous processor for inputting the third clock signal and the serial second forming input code, respectively; and performing first synchronization processing on the serial second forming input code, and outputting the serial second forming input code with first synchronization timing.
Preferably, the second synchronization subunit includes:
at least two fourth synchronous processors, each of which respectively inputs the second clock signal and the corresponding group of serial data with the first time synchronous timing sequence, performs second synchronous processing on the group of serial data with the first time synchronous timing sequence, and outputs the group of serial data with the second time synchronous timing sequence;
at least two first equivalent delay units, each of which inputs a corresponding group of the serial data with a second synchronous timing and outputs the group of the serial data with a completely synchronous timing to the external receiving unit;
a fifth synchronous processor, which inputs the second clock signal and the frame clock signal with the first synchronous timing sequence, respectively, and performs a second synchronous processing on the frame clock signal, which is a frame clock signal with a second synchronous timing sequence;
a second equivalent delay unit which inputs the frame clock signal with the second time synchronous timing and outputs the frame clock signal with the complete synchronous timing;
and the data clock output mode controller is used for respectively inputting the serial second forming input code with the first time synchronous time sequence and the fourth clock signal, and outputting the data clock signal with the complete synchronous time sequence after processing.
Preferably, the second clock signal is a set frequency-multiplied clock signal of the first clock signal; the third clock signal is an inverted signal of the second clock signal; the fourth clock signal is at the same frequency as the second clock signal and has a fixed phase difference.
On the basis of the common knowledge in the field, the above preferred conditions can be combined randomly to obtain the preferred embodiments of the invention.
The positive progress effects of the invention are as follows:
the invention discloses a digital signal parallel input-to-serial output circuit which is formed by assembling at least two parallel-to-serial data processing units, a frame clock generating unit, a data clock generating unit and a synchronizing unit. The invention divides the parallel digital signal into at least two groups of parallel data, and then converts the at least two groups of parallel data to form serial data output, and utilizes at least two groups of serial data with completely synchronous time sequence, frame clock signal with completely synchronous time sequence and data clock signal with completely synchronous time sequence to realize the adjustment of time sequence in the process of converting parallel input into serial output, so that an external receiving unit can accurately and quickly realize the receiving of the parallel digital signal, and is not limited by the speed of an LVDS interface in the prior art, thereby avoiding the problems that the external receiving unit in the prior art is difficult to receive data, the receiving process is easy to generate time sequence error and the like.
Drawings
FIG. 1 is a circuit diagram of a parallel-to-serial conversion circuit for digital signals according to the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Example 1
As shown in fig. 1, a circuit for converting a digital signal from parallel input to serial output comprises: at least two parallel-serial data processing units 1, a frame clock generating unit 2, a data clock generating unit 3, and a synchronizing unit 4.
The circuit for converting parallel input of digital signals into serial output of digital signals disclosed by the embodiment has the following specific working principle:
first, the parallel digital signal is divided into at least two groups of parallel data.
In this embodiment, a 16-bit (bit) parallel digital signal is divided into two groups of 8-bit parallel data.
Next, each parallel-serial data processing unit 1 converts the corresponding set of parallel data into a set of serial data and outputs the converted set of serial data. Meanwhile, the frame clock generating unit 2 inputs the first forming input code, and converts and outputs a frame clock signal; the data clock generation unit 3 inputs the second forming input code, and converts and outputs the serial second forming input code.
In this embodiment, the first forming input code is an input code forming a frame clock signal, and may be input to the frame clock generating unit 2 in an encoding form of 11110000 or 00001111. The second forming input code is an input code forming a data clock signal, and may be input to the data clock generation unit 3 in an encoding form of 10101010 or 01010101. The two groups of 8-bit parallel data, frame clock signals and data clock signals are accurately aligned at the source, and the subsequent circuits can conveniently control the frame clock output and the data clock output.
Then, the synchronization unit 4 respectively inputs at least two sets of serial data, a frame clock signal, and a second forming input code, outputs at least two sets of serial data with a completely synchronous timing sequence, a frame clock signal with a completely synchronous timing sequence, and a data clock signal with a completely synchronous timing sequence after processing, and sends the signals to an external receiving unit.
Finally, the frame clock signal fco with a completely synchronous timing sequence controls the external receiving unit to acquire at least two groups of corresponding serial data forming the parallel digital signal; the data clock signal dco with fully synchronous timing controls the external receiving unit to recover the corresponding at least two sets of serial data to form parallel digital signals.
In this embodiment, two sets of 8-bit parallel data, frame clock signals, and data clock signals are synchronized by the synchronization unit 4, so that the parallel digital signals can be received in serial by the external receiving unit effectively and accurately, and the input parallel digital signals are recovered.
Compared with the prior art, the embodiment has simpler circuit design, realizes no limitation of hardware conditions (LVDS interface speed), ensures accurate transmission of data, and improves transmission efficiency and transmission accuracy.
Example 2
As shown in fig. 1, a circuit for converting a digital signal from parallel input to serial output comprises: at least two parallel-serial data processing units 1, a frame clock generating unit 2, a data clock generating unit 3, and a synchronizing unit 4.
In this embodiment, a 16-bit parallel digital signal with 140MSPS (Million Sample per Second) samples is serialized. Because the data rate of the 16-bit parallel digital signal after being serialized into a serial code stream reaches 16bits multiplied by 140MSPS (maximum likelihood) 2.24Gbps, the processing capacity of the LVDS interface connected later is exceeded (about 2Gbps fastest). Therefore, as shown in fig. 1, in the present invention, a 16-bit parallel digital signal input din <15:0> is divided into two groups of high 8-bit parallel input data din <15:8> and low 8-bit parallel input data din <7:0>, the two groups of 8-bit inputs are converted into serial data dout1 and dout0, and output is performed through two data paths, the data rates of the two groups of serial data are both 1.12Gbps, and the serial data can be normally output through a LVDS interface connected to the rear.
As shown in fig. 1, each parallel-serial data processing unit 1 includes: a first parallel-to-serial converter. The first parallel-serial converter respectively inputs a first clock signal, a second clock signal and a corresponding group of parallel data and converts the parallel data into a group of serial data.
The first clock signal clk1x is the clock signal of the low 8-bit parallel input data din <7:0>, in this embodiment, clk1x is 140MHz, and the second clock signal is set to be the 8 times the first clock signal. The second clock signal clk8x captures clk1x and generates a sel signal through logic processing, the sel signal is used as a selection control signal of the alternative multiplexer, the frequency of the sel signal is the same as that of clk1x, the high level lasts for 1 cycle of clk8x, low 8-bit parallel input data din <7:0> are gated into an input chain of the shift register in the high level time, and then 8-bit input is sequentially shifted and output, so that the 8-bit input is converted into a serial code stream. Two sets of high 8-bit in <15:8> and low 8-bit parallel input data din <7:0> are converted into two sets of serial data dout1 and dout0, respectively, by a first parallel-to-serial converter.
As shown in fig. 1, the frame clock generating unit 2 includes: a second parallel-to-serial converter 21, and a frame clock output mode controller 22.
The second parallel-to-serial converter 21 inputs the first clock signal, the second clock signal, and the first forming input code, respectively, and converts the first forming input code into a serial first forming input code. The frame clock output mode controller 22 inputs the serial first forming input code, the frame clock control code ctrl <1>, and outputs a frame clock signal.
In this embodiment, the first forming input code is an input code forming a frame clock signal, and may be input to the frame clock generating unit 2 in an encoding form of 11110000 or 00001111.
As shown in fig. 1, the data clock generating unit 3 includes: and a third parallel-to-serial converter. The third parallel-to-serial converter respectively inputs the first clock signal, the second clock signal and the second forming input code and converts the second forming input code into a serial second forming input code.
In this embodiment, the second forming input code is an input code forming a data clock signal, and may be input to the data clock generation unit 3 in an encoding form of 10101010 or 01010101.
In this embodiment, with regard to the design of the frame clock generating unit 2 and the data clock generating unit 3, two sets of 8-bit parallel data, the frame clock signal fco and the data clock signal dco are precisely aligned at the source, which is convenient for the subsequent circuit to control the frame clock output and the data clock output.
In this embodiment, the Frame clock output mode has two working modes, i.e., a 1x Frame and a 2x Frame, where the 1x Frame indicates the start of a new Frame of data by using the rising edge of fco, at this time, 1 Frame clock output period corresponds to one Frame of data, both the rising edge and the falling edge of the 2x Frame mode Frame clock output are used to indicate the start of a new Frame of data, and at this time, 1 Frame clock output period corresponds to 2 frames of data.
In this embodiment, the data clock signal dco is used as a clock signal for capturing a serial code stream, and has two operation modes, namely a Double Data Rate (DDR) mode and a Single Data Rate (SDR) mode, wherein a rising edge and a falling edge of the data clock signal dco in the DDR mode are both used as clock trigger edges for capturing data, and a rising edge of the data clock signal dco in the SDR mode is used as clock trigger edges for capturing data.
Since the frame clock generating unit 2 and the data clock generating unit 3 both generate delay, the synchronizing unit 4 is required to synchronize at least two sets of serial data, frame clock signals, and data clock signals.
As shown in fig. 1, the synchronization unit 4 includes: the first synchronization subunit and the second synchronization subunit.
The first synchronization subunit inputs a third clock signal, at least two sets of serial data, a frame clock signal and a serial second formation input code respectively, performs first synchronization timing processing, and outputs at least two sets of serial data with first synchronization timing, a frame clock signal with first synchronization timing and a serial second formation input code with first synchronization timing.
Since the third clock signal is an inverted signal of the second clock signal, the third clock signal is clk8x — n in this embodiment.
Further, the first synchronization subunit includes: at least two first synchronization processors 411, second synchronization processors 412, and third synchronization processors 413.
The specific working principle of the first synchronization subunit is as follows:
each first synchronization processor 411 inputs a third clock signal and a corresponding set of serial data, performs a first synchronization process on the corresponding set of serial data, and outputs a set of serial data with a first synchronization timing. The second synchronization processor 412 receives the frame clock signal and the third clock signal, respectively, performs first synchronization processing on the frame clock signal, and outputs a frame clock signal having first synchronization timing. A third synchronous process of inputting a third clock signal and a serial second formation input code, respectively; the serial second forming input code is subjected to a first synchronization process, and the serial second forming input code having the first synchronization timing is output.
In the invention, the fourth clock signal and the second clock signal have the same frequency and have a fixed phase difference value. Therefore, in the present embodiment, the phase difference between the fourth clock signal ck _ dco and the second clock signal clk8x may be any one of 0 °, 60 °, 120 °, and 180 °.
As shown in fig. 1, the second synchronization subunit respectively inputs the second clock signal, the fourth clock signal, at least two sets of serial data with the first time synchronization timing, the frame clock signal with the first time synchronization timing, and the second forming input code of the serial with the first time synchronization timing, performs the second time synchronization timing processing, and outputs at least two sets of serial data with the fully synchronized timing, the frame clock signal with the fully synchronized timing, and the data clock signal with the fully synchronized timing after the processing.
Further, the second synchronization subunit includes: at least two fourth synchronous processors 421, at least two first equivalent delay units 422, a fifth synchronous processor 423, a second equivalent delay unit 424, and a data clock output mode controller 425.
The specific working principle of the second synchronization subunit is as follows:
each of the fourth synchronous processors 421 respectively inputs the second clock signal and the set of serial data with the first time synchronous timing, performs the second time synchronous processing on the set of serial data with the first time synchronous timing, and outputs the set of serial data with the second time synchronous timing. Each of the first equivalent delay units 422 inputs a set of serial data having a second synchronous timing and outputs a set of serial data having a completely synchronous timing to an external receiving unit. The fifth synchronization processor 423 receives the second clock signal and the frame clock signal having the first synchronization timing, and performs the second synchronization processing on the frame clock signal to obtain the frame clock signal having the second synchronization timing. The second equivalent delay unit 424 inputs the frame clock signal having the second-time synchronization timing and outputs the frame clock signal having the completely synchronized timing. The data clock output mode controller 425 inputs the serial second forming input code and the serial fourth clock signal having the first synchronous timing, respectively, and outputs the data clock signal having the completely synchronous timing after processing.
In this embodiment, the first synchronization processor 411, the second synchronization processor 412, the third synchronization processor 413, the fourth synchronization processor 421 and the fifth synchronization processor 423 are all D flip-flops.
In this embodiment, the at least two first equivalent delay units 422 and the second equivalent delay unit 424 can be equivalent to the delay introduced by one multiplexer selected by the data clock output mode controller 425 in outputting the data clock signal dco, so that the data clock signal dco, the frame clock signal fco, and the at least two sets of serial data dout0, dout1 have the same delay in time sequence, and finally the four signals are output after the driving capability is adjusted by the same buffer, thereby realizing complete parallel input to serial output.
The frame clock signal fco having a completely synchronous timing controls the external receiving unit to acquire at least two sets of corresponding serial data forming the parallel digital signal. The data clock signal dco with fully synchronous timing controls the external receiving unit to recover the corresponding at least two sets of serial data to form parallel digital signals.
In this embodiment, the phase of the data clock signal dco relative to the at least two sets of serial data dout0, dout1 and the frame clock signal fco is precisely adjustable, which facilitates the readjustment of the system timing when the external receiving unit receives data.
Meanwhile, in the invention, the output modes of the data clock signal dco and the frame clock signal fco are adjustable; meanwhile, the time sequence relation between the signals and the output serial data can be ensured under various modes, and a user can conveniently receive data by using an external receiving unit.
While specific embodiments of the invention have been described above, it will be appreciated by those skilled in the art that these are by way of example only, and that the scope of the invention is defined by the appended claims. Various changes and modifications to these embodiments may be made by those skilled in the art without departing from the spirit and scope of the invention, and these changes and modifications are within the scope of the invention.
Claims (8)
1. A digital signal parallel input-to-serial output circuit divides parallel digital signals into at least two groups of parallel data; the circuit comprises: each parallel-serial data processing unit converts a corresponding group of parallel data into a group of serial data and then outputs the serial data; it is characterized in that the preparation method is characterized in that,
a frame clock generating unit for inputting a first forming input code and converting and outputting a frame clock signal;
a data clock generating unit for inputting the second forming input code and converting and outputting the serial second forming input code;
the synchronization unit is used for respectively inputting at least two groups of serial data, the frame clock signal and the serial second forming input code, outputting at least two groups of serial data with completely synchronous time sequence, the frame clock signal with completely synchronous time sequence and the data clock signal with completely synchronous time sequence after processing, and sending the signals to an external receiving unit;
the frame clock signal having a completely synchronous timing controls the external receiving unit to acquire at least two corresponding sets of the serial data forming the parallel digital signal; the data clock signal with fully synchronous timing controls the external receiving unit to recover the corresponding at least two groups of serial data to form the parallel digital signal.
2. The digital signal parallel-input-to-serial-output circuit according to claim 1, wherein each of said parallel-serial data processing units comprises:
and the first parallel-serial converter is used for respectively inputting a first clock signal, a second clock signal and a corresponding group of parallel data and converting the parallel data into a group of serial data.
3. The digital signal parallel-input-to-serial-output circuit according to claim 2, wherein the frame clock generating unit comprises:
a second parallel-to-serial converter which inputs the first clock signal, the second clock signal, and the first forming input code, respectively, and converts the first forming input code into a serial first forming input code;
and a frame clock output mode controller which inputs the serial first forming input code and the frame clock control code and outputs the frame clock signal.
4. The digital signal parallel-input-to-serial-output circuit of claim 3, wherein the data clock generating unit comprises:
and a third parallel-to-serial converter which inputs the first clock signal, the second clock signal, and the second forming input code, respectively, and converts the second forming input code into the serial second forming input code.
5. The circuit of claim 4, wherein the synchronization unit comprises:
a first synchronization subunit which inputs a third clock signal, at least two sets of the serial data, the frame clock signal, and the serial second formation input code, performs first synchronization timing processing, and outputs at least two sets of the serial data having a first synchronization timing, the frame clock signal having a first synchronization timing, and the serial second formation input code having a first synchronization timing, respectively;
and the second synchronization subunit is used for respectively inputting the second clock signal, the fourth clock signal, the at least two groups of serial data with the first time synchronization timing sequence, the frame clock signal with the first time synchronization timing sequence and the second formation input code of the serial data with the first time synchronization timing sequence, performing second time synchronization timing sequence processing, and outputting the at least two groups of serial data with the complete synchronization timing sequence, the frame clock signal with the complete synchronization timing sequence and the data clock signal with the complete synchronization timing sequence after processing.
6. The circuit of claim 5, wherein the first synchronization subunit comprises:
at least two first synchronous processors, wherein each first synchronous processor respectively inputs the third clock signal and a corresponding group of serial data, carries out first synchronous processing on the corresponding group of serial data and outputs a group of serial data with first synchronous time sequence;
the second synchronous processor is used for respectively inputting the frame clock signal and the third clock signal, carrying out first synchronous processing on the frame clock signal and outputting the frame clock signal with the first synchronous time sequence;
a third synchronous processor for inputting the third clock signal and the serial second forming input code, respectively; and performing first synchronization processing on the serial second forming input code, and outputting the serial second forming input code with first synchronization timing.
7. The circuit of claim 6, wherein the second synchronization subunit comprises:
at least two fourth synchronous processors, each of which respectively inputs the second clock signal and the group of serial data with the first time synchronous timing sequence, performs second synchronous processing on the group of serial data with the first time synchronous timing sequence, and outputs the group of serial data with the second time synchronous timing sequence;
at least two first equivalent delay units, each of which inputs a corresponding group of the serial data with a second synchronous timing and outputs the group of the serial data with a completely synchronous timing to the external receiving unit;
a fifth synchronous processor, which inputs the second clock signal and the frame clock signal with the first synchronous timing sequence, respectively, and performs a second synchronous processing on the frame clock signal, which is a frame clock signal with a second synchronous timing sequence;
a second equivalent delay unit which inputs the frame clock signal with the second time synchronous timing and outputs the frame clock signal with the complete synchronous timing;
and the data clock output mode controller is used for respectively inputting the serial second forming input code with the first time synchronous time sequence and the fourth clock signal, and outputting the data clock signal with the complete synchronous time sequence after processing.
8. The digital signal parallel-input-to-serial-output circuit of claim 5, wherein the second clock signal is a set multiple frequency clock signal of the first clock signal; the third clock signal is an inverted signal of the second clock signal; the fourth clock signal is at the same frequency as the second clock signal and has a fixed phase difference.
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| CN102740061A (en) * | 2012-06-14 | 2012-10-17 | 北京蛙视通信技术有限责任公司 | High-definition optical transceiver and multimedia video digital signal processing method |
| CN105404495A (en) * | 2015-10-21 | 2016-03-16 | 哈尔滨工业大学 | High-speed pseudorandom sequence generator and generation method for modulated wideband converter |
| CN105306068A (en) * | 2015-10-30 | 2016-02-03 | 南京理工大学 | Parallel-serial conversion circuit based on clock phase modulation |
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