CN1286289C - Circuit for recovering timing data and implementing method - Google Patents
Circuit for recovering timing data and implementing method Download PDFInfo
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- CN1286289C CN1286289C CN 03113331 CN03113331A CN1286289C CN 1286289 C CN1286289 C CN 1286289C CN 03113331 CN03113331 CN 03113331 CN 03113331 A CN03113331 A CN 03113331A CN 1286289 C CN1286289 C CN 1286289C
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Abstract
The present invention discloses a realizing method for a clock data recovery circuit, wherein the clock recovery circuit comprises a data phase detection module, N frequency division removal module, a data buffering module and a clock adjustment recovery module. The recovery of clock data is carried out on RZ signals by effectively using a buffering technology for data processing, and thus, a recovered clock can be flexibly and rapidly locked. The present invention has better low frequency and high frequency judder removing characteristics, and can be used for the recovery of the clock data in the process of synchronous data transmission in the field of communication.
Description
Technical field
The present invention relates to a kind of clock data recovery circuit and its implementation, relate in particular to a kind of clock data recovery circuit and its implementation in arrowband communication field E 1 data processing.
Background technology
In communication field for better synchronous driving data, generally clock lies among the user data, because user data has very big shake after disturbing through various outer signals, before entering the E1 data handling system, the stationarity of guaranteeing data just seems extremely important, thereby clock data recovery circuit should be used for guaranteeing the stability of clock data widely in communication field E1 data handling system.
Clock data recovery circuit is normally realized by Digital Analog Hybrid Circuits at present.User data extracts recovery by phase-locked loop circuit to user data and clock after analog-to-digital conversion.PHASE-LOCKED LOOP PLL TECHNIQUE be a kind of clock recovery circuitry the implementation method that extensively adopts.Accompanying drawing 2 is realized the method for clock and data recovery for PHASE-LOCKED LOOP PLL TECHNIQUE commonly used.Its basic operation principle is as follows: after the frequency lock, the clock that data sampling module is used is the stabilizing clock of voltage controlled oscillator output, when input signal produces shake, the phase demodulation module is carried out phase demodulation output with input signal phase place and voltage controlled oscillator output signal phase place, form the correspondent voltage difference signal by the charge pump module, low pass filter is finished the high frequency of this voltage differential signal and noise signal is removed function, the stability of assurance system loop, voltage differential signal acts on and impels its output signal frequency and frequency input signal to draw close until the frequency difference elimination on the voltage controlled oscillator, and then finishes the frequency lock function.Voltage controlled oscillator, charge pump, low pass filter and phase discriminator belong to core component in the whole system, and the height of its performance directly influences the ability of trembling of going of whole clock data recovery circuit.So at the various different requirements that recover frequency, these assemblies all have separately different algorithms and corresponding structure to finish.In to the quite high system of clock data stability requirement, clock frequency realizes by analog circuit than these modules under the condition with higher again, so that satisfy the high performance requirements of system.Because analog circuit is common bad the checking in the straight numerical system circuit, progressively begun in present many systems to adopt the phase-locked loop of pure digi-tal to realize clock and data recovery, but, clock and data recovery generally can occur and the poor situation of anti-jitter ability under low frequency, occur because various digital circuit implementation methods differ.
Summary of the invention
Problem to be solved by this invention is the method that has been to propose a kind of E1 of being used for data communication system clock data recovery circuit and realization thereof, can realize that clock and data recovery has the anti-preferably ability of trembling under low high frequency.
In order to realize the foregoing invention purpose, the invention provides a kind of clock data recovery circuit, its characteristics are, comprising: the data phase detection module, remove Fractional-N frequency module, data buffering module and recovered clock adjusting module; Described data phase detection module is used for input RZ signal is carried out phase-detection and expansion, produces needed triggering signal of described Fractional-N frequency module and the needed data input signal of described data buffering module; The described Fractional-N frequency module of removing receives triggering signal and external reference clock signal that described data phase detection module produces, handles producing the needed read-write clock signal of described data buffering module through frequency division; Described recovered clock adjusting module, be used for to described remove that N counter frequency division module produced write read clock signal adjustment substantially, with its read clock signal of writing as described data buffering module, thus finish to described RZ signal go to tremble adjustment, and output recovers read clock signal; Described data buffering module is used for data-signal that described phase detecting module is sent here, and the read-write clock signal of sending here according to described recovered clock adjusting module is finished the write-read at buffering area, and output non-return-to-zero NRZ signal.
Above-mentioned clock data recovery circuit, its characteristics are, described remove N counter frequency division module and receive the pulse triggering signal that described data phase detection module produces after, the cycle count of starting from scratch, according to N value automatic clear, the N value is used for determining the phase place adjusting range.
Above-mentioned clock data recovery circuit, its characteristics be, described to remove the Fractional-N frequency module be 24 frequency counters, and its reference clock XCLK that selects for use is 49.152MHz.
Above-mentioned clock data recovery circuit, its characteristics are that the recovered clock RCLK that is exported by described recovered clock adjusting module is 2.048MHz.
In order to realize the object of the invention better, the present invention also provides a kind of method of clock data recovery circuit realization, and its characteristics are, comprise the steps:
RZ carries out data phase detection and expansion to the input rz signal, detects data pulse signal, and produces pulse triggering signal, is used for the flip-flop number frequency division;
Reference clock signal is carried out frequency division, produce the read-write clock signal, the data that are used to control described rz signal Rz write/the sense data buffer area;
Write the jitter accumulation of buffering area according to described data, the corresponding recovered clock of carrying out is dynamically adjusted, and output recovered clock signal;
The data-signal that will go from the data buffer zone to tremble is exported as the NRZ signal.
The method that above-mentioned clock data recovery circuit is realized, its characteristics are: utilize pulse triggering signal to reset to writing clock WRCLK counter, and by the initial value that clock WRCLK counter is write in adjustment carry out described data-signal go tremble.
The method that above-mentioned clock data recovery circuit is realized, its characteristics are: the recovered clock adjustment is by the degree of depth of adjusting data buffer zone FIFO and adjusts going that the time slot width adjusted between the write-read clock carries out and tremble.
The method that above-mentioned clock data recovery circuit is realized, its characteristics are, described reference clock XCLK is carried out 24 frequency divisions, described XCLK is 49.152MHz.
The method that above-mentioned clock data recovery circuit is realized, its characteristics are that the recovered clock RCLK of output is 2.048MHz.
Clock data recovery circuit of the present invention, characteristics according to the E1 communication data, adopt buffer technology effectively, the RZ signal has been carried out the recovery of clock data, can lock recovered clock flexibly fast, have good low frequency and high frequency to go to tremble characteristic, whole system can well be integrated in the E1 framer of full-digital circuit as a very little module, provides level and smooth 2.048MHz recovered clock and NRZ signal to handle for framer.
Description of drawings
Fig. 1 is the position of clock recovery circuitry in the E1 system;
Fig. 2 utilizes the digital phase-locked loop structure to realize clock recovery circuitry;
Fig. 3 is the system construction drawing of clock data recovery circuit of the present invention;
Fig. 4 is Data Detection and read-write clock generating sequential chart;
Fig. 5 is that read/write address is relatively adjusted and read clock timing diagram.
Embodiment
Below in conjunction with accompanying drawing, the present invention is described in further detail.
Fig. 1 has described the position of clock and data recovery module in whole data handling system.By the accompanying drawing position of clock and data recovery module in the E1 system as can be seen, user data is being exported the RZ signal to the clock data recovery module through the equilibrium model number conversion, and the RZ signal is through recovering the system clock RCLK of whole module and the data NRZ signal that will further handle behind the clock data recovery circuit.
Fig. 3 is the system construction drawing of clock data recovery circuit of the present invention.It comprises four major parts: data detection module 11, Fractional-N frequency counter module 12, data buffering module 13 and clock adjusting module 14.In order to improve the sensitivity that clock is adjusted, level and smooth little clock jitter recovers the clock of 2.048MHz as required, and selecting reference clock XCLK for use is 49.152MHz.
The RZ signal that data detection module 11 is come in input carries out input, in the realization in order to improve jitter toleration to the RZ signal, these data detection module 11 suitable RZ signal are effectively expanded simultaneously, detect data pulse and produce triggering (TRIGGER) signal later on, this signal passes to Fractional-N frequency counter module 12, is used for the counter that generation data buffering module 13 is write clock WRCLK is carried out reset operation.Fractional-N frequency counter module 12 carries out 24 frequency divisions according to reference clock XCLK and produces WRCLK, and WRCLK writes the data buffer zone as the write data clock of data buffering module 13 with the RZ signal.In addition data buffering module 13 read clock RDCLK also by obtaining behind XCLK 24 frequency divisions, RDCLK goes to the data that cushion in the data buffer zone to tremble the back and reads with the speed of 2.048M.Reading clock RDCLK goes to tremble according to input RZ signal and adjusts function and finished by recovered clock adjusting module 14.Simultaneously, by recovered clock adjusting module 14 output recovered clock signal RCLK.
Fig. 4 has described the sequential relationship between reference clock XCLK and the pulse of RZ signal data and buffering area reading and writing clock RDCLK, the WRCLK.According to the characteristics of RZ signal, the posterior part at high impulse is determined in the collection of input data.The RZ signal is made up of the high level of preceding half clock cycle and the low level of back half clock cycle for the expression of signal " 1 "; The RZ signal is for the full low level that is expressed as of signal " 0 ".When pulse signal arrives, detect data pulse by the data phase detection module and produce triggering (TRIGGER) signal, the TRIGGER signal is promptly write clock WRCLK counter to the collection clock and is resetted, and corresponding 24 XCLK clock cycle of complete RZ signal in the system, so data acquisition clock to signal " 1 ", its rising edge original position can be arranged on 6～10 XCLK clock cycle after the TRIGGER signal, guarantee to collect corresponding data on the one hand, even a plurality of RZ signal jitter mutual superposition, also guarantee to collect corresponding data in the corresponding clock cycle, adjust the concrete size of the initial value of this clock counter on the other hand, that can improve low frequency dither goes the shake ability.As described in Figure 3, the RZ signal through module 11 expansion after, the rising edge setting of wRcLK clock can be after the TRIGGER signal 8～10 XCLK clock cycle data are gathered, the whole removing shudder performance is than higher like this.
Fig. 5 has described and has read clock RDCLK and write the sequential relationship of adjusting between the clock WRCLK.The first-in first-out FIFO of 8 byte degree of depth is adopted in the data buffer zone, and the degree of depth of this data buffer zone FIFO can be adjusted according to the situation of whole subscriber's line shake, can strengthen the degree of depth of FIFO under the situation of influence area not, improves the ability of trembling of going.A data write address of every reception WR_ADDR adds 1, whenever reads data and reads address RD_DDR and add 1.Added four in addition from address signal, WR_ADDR_A1 is the previous address of current write address, and WR_ADDR_A2 is that current write address WR_ADDR subtracts 2; RD_ADDR_A1 is that the current address RD_DDR that reads subtracts 1, and RD_ADDR_A2 is that the current address RD_ADDR that reads subtracts 2.The purpose of these four address signals is exactly to provide the space of two clock cycle to carry out the adjustment of clock between the read-write clock.Clock cycle is adjusted signal RD_CLK_ADV and RD_CLK_RET adjusted the clock cycle of RDCLK according to reading of relatively producing mutually of these four address signals, for example: RD_ADDR reaches WR_ADDR_A2 or WR_ADDR_A1 when the reading of data address, illustrate that then the speed that reads is faster than normal clock owing to writing data dithering, at this moment RD_CLK_ADV puts 1, clock counter is read in generation added 1 and increase and to read the clock cycle.When write data address WR_ADDR reaches RD_ADDR_A1 or RD_ADDR_A2, illustrate that the data that read this moment are owing to the shake that writes data has seemed slowly some, at this moment the RD_CLK_RET signal puts 1, clock counter is read in generation subtracted 1 and then reduce to read the clock cycle.Have and abovely can see the adjusting range scope that reads clock RDCLK at an XCLK within the cycle, reduced the shake of input RZ signal greatly, played and gone to tremble function, export the NRZ signal simultaneously.
On the one hand by described in preceding Fig. 4, adjusting the initial value of WRCLK, the ability of trembling of going of whole clock data recovery system can be adjusted and improve to the time slot width of adjusting between the degree of depth by flexible adjustment FIFO as shown in Figure 5 and WRCLK and the RDCLK clock on the one hand in addition flexibly.
Claims (7)
1, a kind of clock data recovery circuit is characterized in that, comprising: the data phase detection module, remove Fractional-N frequency module, data buffering module and recovered clock adjusting module;
Described data phase detection module is used for input RZ signal is carried out phase-detection and expansion, produces described needed triggering signal of Fractional-N frequency module and the needed data input signal of described data buffering module of removing;
The described Fractional-N frequency module of removing receives triggering signal and external reference clock signal that described data phase detection module produces, handles producing the needed read-write clock signal of described data buffering module through frequency division;
Described recovered clock adjusting module, be used for to described remove that the Fractional-N frequency module produced write the size that read clock signal is adjusted the initial value of counter substantially, perhaps the time slot width of adjusting between the degree of depth of data buffering area FIFO and the write-read clock is adjusted, with its read clock signal of writing as described data buffering module, thereby finish described RZ signal gone to tremble adjustment, and output recovered clock signal;
Described data buffering module is used for data-signal that described phase detecting module is sent here, and the read-write clock signal of sending here according to described recovered clock adjusting module is finished the write-read at buffering area, and output non-return-to-zero NRZ signal.
2, clock data recovery circuit as claimed in claim 1, it is characterized in that, described remove the Fractional-N frequency module and receive the pulse triggering signal that described data phase detection module produces after, the cycle count of starting from scratch, according to N value automatic clear, the N value is used for determining the phase place adjusting range.
3, clock data recovery circuit according to claim 1 and 2 is characterized in that, the described Fractional-N frequency module of removing is 24 frequency counters, and its reference clock XCLK that selects for use is 49.152MHz.
4, clock data recovery circuit according to claim 3 is characterized in that, reading clock RCLK by the recovery of described recovered clock adjusting module output is 2.048MHz.
5, a kind of method of clock data recovery circuit realization is characterized in that, comprises the steps:
RZ carries out data phase detection and expansion to the input rz signal, detects data pulse signal, and produces pulse triggering signal, is used for the flip-flop number frequency division;
Reference clock signal is carried out frequency division, produce the read-write clock signal, the data that are used to control described rz signal RZ write/the sense data buffer area;
Write the jitter accumulation of buffering area according to described data, utilize pulse triggering signal to reset to writing clock WRCLK counter, and write the initial value of clock WRCLK counter by adjustment, the perhaps degree of depth by adjusting data buffer zone FIFO and adjust the time slot width of adjusting between the write-read clock and carry out recovered clock and dynamically adjust, and output recovered clock signal;
The data-signal that will go from the data buffer zone to tremble is exported as the NRZ signal.
6, the method for clock data recovery circuit realization according to claim 5 is characterized in that described reference clock XCLK is carried out 24 frequency divisions, and described XCLK is 49.152MHz.
7, the method for clock data recovery circuit realization according to claim 6 is characterized in that it is 2.048MHz that clock RCLK is read in the recovery of output.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 03113331 CN1286289C (en) | 2003-04-25 | 2003-04-25 | Circuit for recovering timing data and implementing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 03113331 CN1286289C (en) | 2003-04-25 | 2003-04-25 | Circuit for recovering timing data and implementing method |
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| CN1540911A CN1540911A (en) | 2004-10-27 |
| CN1286289C true CN1286289C (en) | 2006-11-22 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN 03113331 Expired - Lifetime CN1286289C (en) | 2003-04-25 | 2003-04-25 | Circuit for recovering timing data and implementing method |
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Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4749168B2 (en) * | 2006-02-01 | 2011-08-17 | ルネサスエレクトロニクス株式会社 | Clock and data recovery circuit |
| CN1983888B (en) * | 2006-06-07 | 2010-10-27 | 华为技术有限公司 | Device and method for restoring clock |
| CN101621346B (en) * | 2009-07-09 | 2013-03-27 | 中兴通讯股份有限公司 | Source synchronous receiving device with adaptive feedback and source synchronizing method |
| CN102571080A (en) * | 2010-12-27 | 2012-07-11 | 北京中电华大电子设计有限责任公司 | clock recovery method and circuit supporting dynamic calibration |
| WO2012126420A2 (en) * | 2012-05-10 | 2012-09-27 | 华为技术有限公司 | Data and clock recovery module and data and clock recovery method |
| CN103414452B (en) * | 2013-07-23 | 2016-08-24 | 华为技术有限公司 | Clock data recovery device and electronic equipment |
| CN105281759A (en) * | 2015-10-23 | 2016-01-27 | 西安中科晶像光电科技有限公司 | System clock adjustment circuit |
| CN105356995B (en) * | 2015-11-24 | 2018-06-26 | 山东胜开电子科技有限公司 | A kind of two-way restoration methods of synchronous code and circuit |
| CN112187256B (en) * | 2019-07-04 | 2023-08-25 | 智原微电子(苏州)有限公司 | Clock data recovery device and operation method thereof |
-
2003
- 2003-04-25 CN CN 03113331 patent/CN1286289C/en not_active Expired - Lifetime
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| CN1540911A (en) | 2004-10-27 |
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Effective date of registration: 20160530 Address after: Dameisha Yantian District of Shenzhen City, Guangdong province 518085 Building No. 1 Patentee after: SANECHIPS TECHNOLOGY Co.,Ltd. Address before: 518057 Department of law, Zhongxing building, South Science and technology road, Nanshan District hi tech Industrial Park, Shenzhen Patentee before: ZTE Corp. |
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Application publication date: 20041027 Assignee: Xi'an Chris Semiconductor Technology Co.,Ltd. Assignor: SANECHIPS TECHNOLOGY Co.,Ltd. Contract record no.: 2019440020036 Denomination of invention: Circuit for recovering timing data and implementing method Granted publication date: 20061122 License type: Common License Record date: 20190619 |
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