CN105281759A - System clock adjustment circuit - Google Patents
System clock adjustment circuit Download PDFInfo
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- CN105281759A CN105281759A CN201510689329.8A CN201510689329A CN105281759A CN 105281759 A CN105281759 A CN 105281759A CN 201510689329 A CN201510689329 A CN 201510689329A CN 105281759 A CN105281759 A CN 105281759A
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Abstract
The invention discloses a system clock adjustment circuit. External additional devices of a system can be avoided; and furthermore, the fussy design of an internal analog circuit can be avoided. The system clock adjustment circuit is composed of three parts including a configuration circuit, a counting circuit and a control output circuit. The system detects a local clock and compares the local clock with a built-in clock in a broadcast code stream; the adjustment intensity and direction of the clock adjustment circuit are set through the configuration circuit according to a differential numerical value; the adjustment intensity is embodied through the counting circuit; the control output circuit inhibits clock pulse according to the counting circuit; the system speed can be artificially slowed by inhibiting the clock pulse; and the three parts of circuits form the complete clock adjustment circuit. The system clock adjustment circuit disclosed by the invention is designed for a pure digital circuit and has better effects in two aspects of the design complexity and the chip area.
Description
Technical field
The present invention relates to system clock regulating circuit, particularly relate to a kind of system clock regulating circuit of simplification.
Background technology
System clock adjustment has purposes widely in broadcast communication.Due to the existence of clock skew, local clock and radio clock have difference, and when this difference runs up to a certain degree, application system must make corresponding adjustment, otherwise the input of broadcast data punching will be overflowed, and decoding exports time of occurrence mistake.In order to solve the difference of local and radio clock; usual meeting first calculates difference size by system; then a magnitude of voltage is provided according to the numerical value of difference through DA D/A converting circuit; control outside VCXO (VCXO) by this voltage, considerably increase complexity and the cost of system.Substantially this scheme is not adopted at present.
In addition, also have some systems to adopt inner oscillator, provide an adjustable input clock to system PLL.This scheme is less than the former area, and system also eliminates VCXO.But what this scheme adopted is Analog Circuit Design, not only will design separately, and chip layout, wiring also will have special consideration.Thus add the complexity of system and the risk of design.
Summary of the invention
The object of this invention is to provide a kind of clock adjusting circuitry of simplification, it adopts totally digital circuit to design, and not only avoids its exterior additional device, and can avoid the loaded down with trivial details design of internal analogue circuit.
Clock adjusting circuitry of the present invention comprises configuration circuit, counting circuit and control circuit.Configuration circuit is used for the parameter according to the instruction configuration counting circuit received; Counting circuit, for the Selecting parameter count value configured according to configuration circuit, sends control signal to control circuit after counting is full; Control circuit, for suppressing clock pulse after receiving the control signal of counting circuit, and provides the clock after adjustment.
Configuration circuit in clock adjusting circuitry, its instruction received comprises clock difference numerical value, this clock difference numerical value is according to size and be positive and negatively divided into 32 grades, and using grade as described parameter, and clock difference numerical value determines the frequency of control circuit suppressor pulse.
Clock adjusting circuitry also comprises system processor, frequency dividing circuit and clock adjusting circuitry.System processor is used for sending instruction to configuration circuit; The clock pulse that frequency dividing circuit is used for control circuit suppresses carries out frequency division output, it act as the input clock providing counting circuit, system clock is 27MHz, and the input clock of counting circuit is far more than a frequency of 27MHz, will less times greater than 27MHz after frequency division; Control circuit is formed with door by one.
The invention has the advantages that it is totally digital circuit design, the VCXO of existing system peripheral costliness can be replaced, do not need chip internal to redesign analog circuit to adjust input clock simultaneously, have better effect from the viewpoint of design complexities and chip area two.
Accompanying drawing explanation
Fig. 1 is the structural representation of clock adjusting circuitry according to an embodiment of the invention.
Fig. 2 is the structural representation of clock adjusting circuitry according to another embodiment of the present invention.
Fig. 3 is the working waveform figure of the control circuit according to clock adjusting circuitry in one embodiment of the invention.
Embodiment
Design of the present invention is totally digital circuit, easy and other partial fusion of system, thus greatly reduces the design complexities of system.Be described for set-top-box system below.
In set-top box scenario, the method for outside VCXO or internal adjustment phase-locked loop shake (PLLjitter) that adopts is accelerated, is slowed down system clock more, thus reaches adjustment local clock, makes the object that itself and radio clock mate.
As shown in Figure 1, clock adjusting circuitry of the present invention forms primarily of three partial circuits: configuration circuit 11, counting circuit 12 and control circuit 13.System by detecting local clock, and and inside broadcast code stream the clock that carries compare, obtain clock difference numerical value.Configuration circuit 11 arranges the adjustment dynamics of clock adjusting circuitry according to the size of clock difference numerical value.Adjustment dynamics is embodied by configuration counting circuit 12.Control circuit 13 suppresses clock pulse according to counting circuit, by suppress clock pulse can be artificial slow down system speed.This three partial circuit constitutes a complete clock adjusting circuitry.
Fig. 2 is the structural representation of clock adjusting circuitry according to another embodiment of the present invention.In the embodiment depicted in figure 2, system clock regulating circuit comprises system processor 14, phase-locked loop 15 and frequency dividing circuit 16 further.
First system processor 14 compares local zone time and broadcast transmission time, and because set-top-box system specifies that the 27MHz clock difference of system must at +/-50ppm, this is the major parameter will noted when designing phase-locked loop.So be 50ppm to the maximum between local zone time and broadcast transmission end clock, adjusting range is then 100ppm.Consider the accumulative effect of clocking error, system processor 14 should detect the difference of local zone time STC and broadcast transmission end time SCR always.Local clock STC is counted by local system clock and produces, and broadcast transmission clock end SCR is then embedded in inside code stream.System processor 14 calculates the difference (STC-SCR) of local zone time STC and broadcast transmission end time SCR, i.e. clock difference numerical value.Clock difference numerical value is according to size and be positive and negatively divided into 32 grades.The size of grade is divided into 0 ~ 15 and 16 ~ 32 two parts according to positive and negative, and each part is equal to the scope of 50ppm, and equal proportion is divided into 16 regions.Then system processor 14 selects corresponding grade according to the difference of (STC-SCR), sends instruction, grade is controlled counting circuit 12 as parameter by configuration circuit 11 to configuration circuit 11.
The input clock of counting circuit 12 is far more than a frequency of 27MHz, is produced by phase-locked loop 15.Here to note a bit: in order to ensure that system has the ability of quickening and the local zone time that slows down simultaneously, the input clock of counting circuit 12 will less times greater than 27MHz after frequency division.According to class parameter, counting circuit 12 is selected corresponding numerical value to calculate.Once counting is full, then send a control signal to control circuit 13.
The effect of control circuit 13 is exactly briefly mask a clock pulse.Control circuit is formed with door by one, quite simply.Unique need consider meet control signal when rear end clock circuit connects up exactly and clock does not have burr (glitch).Input local clock with an input of door, another input then inputs the control signal of counting circuit, provides the clock source of system with the output of door.With reference to figure 3, the input clock of counting circuit 12 goes out phase-locked loop 15 to be provided, and the output waveform of control circuit 13 demonstrates, a clock pulse that the clock (outputclock) that control circuit 13 exports is correspondingly suppressed.
Generally speaking, system, according to local zone time and the clock difference of airtime, determines the frequency that control circuit 13 curbs pulse.If local zone time lags behind the airtime, this means that local clock needs to accelerate, need the count value that corresponding employing is larger, the output frequency of such counting circuit is just little, thus the pulse curbing PLL output is few, system clock frequency just increases, thus local zone time is progressively accelerated, and catches up with the airtime.Further, the backward difference (STC-SCR) of local zone time relative airtime is larger, then need to adopt larger count value.Otherwise, if local zone time is advanced, then need the local clock that slows down.Adopt smaller count value can improve the number of shielding PLL output clock pulse, this just causes system clock frequency to reduce, and reaches the object delaying local clock, makes it match with radio clock gradually.
The signal that control circuit 13 exports is the clock source that system needs, then can obtain the system clock of required 27MHz after frequency dividing circuit 16 carries out frequency division, audio frequency and video (AV) clock namely after adjustment.At this, utilize frequency dividing circuit 16, directly the clock source frequency division that the set-top-box system clock of required 27MHz exports from control circuit 13 is obtained, to save a phase-locked loop, also thus save chip area.
The invention has the advantages that it is totally digital circuit design, not only the outside spare system of removal system, and the loaded down with trivial details design of internal analogue circuit can be avoided.Current chip technique development, chip is in order to reduce costs the needs production technology that constantly follow-up is advanced, and analog circuit is necessary design iterations unavoidably, thus increases system design complexity and flow risk.Totally digital circuit can avoid the problem of this respect completely, and the circuit area of this part is also very little, further reduces system cost.
Claims (9)
1. a clock adjusting circuitry, is characterized in that, comprising:
Configuration circuit, for carrying out configuration parameter according to the instruction received;
Counting circuit, for according to described Selecting parameter count value, sends control signal after counting is full;
And control circuit, for suppressing clock pulse after receiving described control signal, provide the system clock after adjustment.
2. clock adjusting circuitry according to claim 1, is characterized in that, the instruction that configuration circuit receives comprises clock difference numerical value.
3. clock adjusting circuitry according to claim 2, is characterized in that, described clock difference numerical value is according to size and be positive and negatively divided into 32 grades, and using grade as described parameter.
4. clock adjusting circuitry according to claim 2, is characterized in that, clock difference numerical value determines the frequency of control circuit suppressor pulse.
5. clock adjusting circuitry according to claim 1 and 2, is characterized in that, also comprises system processor, for sending instruction to configuration circuit.
6. clock adjusting circuitry according to claim 1, is characterized in that, also comprises frequency dividing circuit, carries out frequency division output for the clock pulse suppressed control circuit.
7. clock adjusting circuitry according to claim 6, is characterized in that, for providing the input clock of counting circuit.
8. according to the clock adjusting circuitry shown in claim 7, it is characterized in that, system clock is 27MHz, and the input clock of counting circuit is far more than a frequency of 27MHz, will less times greater than 27MHz after frequency division.
9. clock adjusting circuitry according to claim 1, is characterized in that, control circuit is formed with door by one.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510689329.8A CN105281759A (en) | 2015-10-23 | 2015-10-23 | System clock adjustment circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510689329.8A CN105281759A (en) | 2015-10-23 | 2015-10-23 | System clock adjustment circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN105281759A true CN105281759A (en) | 2016-01-27 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510689329.8A Pending CN105281759A (en) | 2015-10-23 | 2015-10-23 | System clock adjustment circuit |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1376334A (en) * | 1999-09-28 | 2002-10-23 | 西门子公司 | Circuit arrangmeent for generating a clock-pulse signal having a frequency synchronous with a reference clock-pulse signal |
| CN1409490A (en) * | 2001-09-30 | 2003-04-09 | 深圳市中兴通讯股份有限公司上海第二研究所 | Shake-removing circuit based on digital lock phase loop |
| CN1540911A (en) * | 2003-04-25 | 2004-10-27 | 中兴通讯股份有限公司 | Circuit for recovering timing data and implementing method |
| CN101295981A (en) * | 2007-04-27 | 2008-10-29 | 上海芯致电子科技有限公司 | System clock regulating circuit |
-
2015
- 2015-10-23 CN CN201510689329.8A patent/CN105281759A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1376334A (en) * | 1999-09-28 | 2002-10-23 | 西门子公司 | Circuit arrangmeent for generating a clock-pulse signal having a frequency synchronous with a reference clock-pulse signal |
| CN1409490A (en) * | 2001-09-30 | 2003-04-09 | 深圳市中兴通讯股份有限公司上海第二研究所 | Shake-removing circuit based on digital lock phase loop |
| CN1540911A (en) * | 2003-04-25 | 2004-10-27 | 中兴通讯股份有限公司 | Circuit for recovering timing data and implementing method |
| CN101295981A (en) * | 2007-04-27 | 2008-10-29 | 上海芯致电子科技有限公司 | System clock regulating circuit |
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Application publication date: 20160127 |