CN101295981A

CN101295981A - System clock regulating circuit

Info

Publication number: CN101295981A
Application number: CNA2007100400659A
Authority: CN
Inventors: 张镭; 李春峰
Original assignee: SHANGHAI XINZHI ELECTRONIC TECHNOLOGY Co Ltd
Current assignee: SHANGHAI XINZHI ELECTRONIC TECHNOLOGY Co Ltd
Priority date: 2007-04-27
Filing date: 2007-04-27
Publication date: 2008-10-29

Abstract

The invention discloses a simplified circuit used for adjusting a system clock during audio and video decoding. The simplified circuit of the invention consists of three parts, a configuration circuit, a counting circuit and an output control circuit. The system detects a local clock and compares the local clock with a given clock in a broadcast bit stream. According to phase differential values, the configuration circuit configures the clock to adjust the adjusting intensity and the direction of the circuit and the adjusting intensity is reflected by the counting circuit. In addition, the output control circuit inhibits clock pulse by the counting circuit, which can manually slow down the system pace. Thus, the three parts of circuits constitute a complete clock adjusting circuit.

Description

System clock regulating circuit

Technical field

The present invention relates to system clock regulating circuit, relate in particular to a kind of system clock regulating circuit of simplification.

Background technology

System clock is adjusted at purposes widely in the broadcast communication.Because clock skew exists, local clock and radio clock have difference, and when this difference runs up to a certain degree, application system must adjust accordingly, otherwise the input buffering of broadcast data will overflow, and decoding output is with the time of occurrence mistake.In order to solve the difference of local and radio clock; usually can calculate the difference size earlier by system; numerical value according to difference provides a magnitude of voltage through the DA D/A converting circuit then, controls outside VCXO (VCXO) by this voltage, thereby reaches the purpose of adjusting input clock.As shown in Figure 1.But system need increase a DA modular converter like this, and VCXO of outside need, has increased the complexity and the cost of system greatly.Basically do not adopt this scheme at present.

In addition, also have some systems to adopt inner oscillator, an adjustable input clock is provided for the PLL of system.This scheme is littler than the former area, and system has also saved VCXO.What but this scheme adopted is Analog Circuit Design, not only will design separately, and chip layout, wiring also will have special consideration.Thereby the complexity of system design and the risk of design have been increased.

Summary of the invention

The clock that the purpose of this invention is to provide a kind of simplification is adjusted circuit, and it adopts the totally digital circuit design, not only avoids the outside additional device of system, and can avoid the loaded down with trivial details design of internal simulation circuit.

Clock of the present invention is adjusted circuit and is comprised configuration circuit, counting circuit and control circuit.Configuration circuit is used for according to the instruction configuration counting circuit parameters needed that receives; Counting circuit is used for selecting count value according to the parameter of configuration circuit configuration, sends control signal after counting is full and gives control circuit; Control circuit is used for suppressing clock pulse after receiving the control signal of counting circuit, and adjusted clock is provided.

The invention has the advantages that it is the totally digital circuit design, can replace outside expensive VCXO in the existing system, do not need simultaneously chip internal redesign analog circuit to adjust input clock, consider all to have better effect from design complexities and chip area two aspects.

Description of drawings

Fig. 1 is that clock is adjusted the structural representation of circuit according to an embodiment of the invention.

Fig. 2 is that clock is adjusted the structural representation of circuit according to another embodiment of the present invention.

Fig. 3 is a working waveform figure of adjusting the control circuit of circuit according to clock in one embodiment of the invention.

Embodiment

Design of the present invention is a totally digital circuit, and energy and system's other parts are easy to merge, thereby greatly reduces the design complexities of system.Be that example describes below with the set-top-box system.

System clock is accelerated, slowed down to many outside VCXO of employing or the inner methods of adjusting phase-locked loop shake (PLL jitter) in the set-top box scenario, thereby reach the adjusting local clock, the purpose that itself and radio clock are mated.

As shown in Figure 1, clock adjustment circuit of the present invention mainly is made up of three partial circuits: configuration circuit 11, counting circuit 12 and control circuit 13.System is by detecting local clock, and and the clock that carries of broadcasting code stream the inside compare, obtain clock and differ numerical value.Configuration circuit 11 is provided with the adjustment dynamics that clock is adjusted circuit according to the size that clock differs numerical value.The adjustment dynamics embodies by configuration counting circuit 12.13 of control circuits suppress clock pulse according to counting circuit, by suppressing the system speed that slows down that clock pulse can be artificial.This three partial circuit has constituted a complete clock and has adjusted circuit.

Fig. 2 is that clock is adjusted the structural representation of circuit according to another embodiment of the present invention.In embodiment illustrated in fig. 2, system clock regulating circuit further comprises system processor 14, phase-locked loop 15 and frequency dividing circuit 16.

System processor 14 is at first compared local zone time and broadcast transmission end time and since set-top-box system stipulate system 27MHz clock difference must+/-50ppm, this is the major parameter that will note during phase-locked loop in design.So be 50ppm to the maximum between local zone time and broadcast transmission end clock, adjusting range then is 100ppm.Consider the accumulative total effect of clocking error, system processor 14 should detect the difference of local zone time STC and broadcast transmission end time SCR always.Local clock STC is produced by the local system clock count, and broadcast transmission end clock SCR then is embedded in the code stream the inside.System processor 14 calculates the difference (STC-SCR) of local zone time STC and broadcast transmission end time SCR, and promptly clock differs numerical value.Clock differs numerical value according to size with positive and negatively be divided into 32 grades.The size of grade is according to positive and negative 0～15 and 16～32 two parts that are divided into, and each part is equal to the scope of 50ppm, and equal proportion is divided into 16 zones.System processor 14 is selected corresponding grade according to the difference of (STC-SCR) then, sends instruction to configuration circuit 11, and grade is controlled counting circuit 12 as parameter by configuration circuit 11.

The input clock of counting circuit 12 is frequencies that far surpass 27MHz, is produced by phase-locked loop 15.Here to note a bit: for the assurance system has the ability of the quickening and the local zone time that slows down simultaneously, will be behind the input clock process frequency division of counting circuit 12 less times greater than 27MHz.According to class parameter, counting circuit 12 selects corresponding numerical value to count.In case counting is full, then sends a control signal and give control circuit 13.

The effect of control circuit 13 simply says to be exactly to mask a clock pulse.Control circuit constitutes with door by one, and is quite simple.Unique need to consider when the rear end clock circuit connects up, satisfy control signal exactly and clock does not have burr (glitch) to get final product.With input input local clock of door, another input is then imported the control signal of counting circuit, provides the clock source of system with the output of door.Please refer to Fig. 3, the input clock of counting circuit 12 is provided by phase-locked loop 15, is controlled system clock (clock).When a trailing edge appearred in control signal (control signal), the output waveform of control circuit 13 demonstrated, and the clock (output clock) of control circuit 13 outputs correspondingly has been suppressed a clock pulse.

Generally speaking, system has determined control circuit 13 to curb the frequency of pulse according to the clock difference of local zone time and airtime.If local zone time lags behind the airtime, this means that local clock needs to accelerate, need the bigger count value of corresponding employing, the output frequency of counting circuit is just little like this, thereby the pulse that curbs PLL output is few, system clock frequency just increases, thereby makes local zone time progressively accelerate, and catches up with the airtime.And the backward difference (STC-SCR) of relative airtime of local zone time is big more, then needs to adopt big more count value.Otherwise if local zone time is leading, local clock then need slow down.Adopt smaller count value can improve the number of shielding PLL output clock pulse, this just causes system clock frequency to reduce, and reaches the purpose that delays local clock, and it is complementary with radio clock gradually.

The signal of control circuit 13 output is the clock source that system needs, and carries out can obtaining behind the frequency division system clock of needed 27MHz again through frequency dividing circuit 16, promptly adjusted audio frequency and video (AV) clock.At this, utilize frequency dividing circuit 16, directly the clock source frequency division of the set-top-box system clock of needed 27MHz from control circuit 13 output obtained, can save a phase-locked loop, also thereby saved chip area.

The invention has the advantages that it is totally digital circuit design, the outside additional device of removal system not only, and in can avoiding The loaded down with trivial details design of section's analog circuit. Current chip technology development, chip need constantly the follow-up advanced person's in order to reduce cost Production technology, the unavoidably necessary design iterations of analog circuit, thus increase system complexity and flow risk. Cardinar number The word circuit can be avoided the problem of this respect fully, and the area of this part circuit is also very little, has further reduced system's one-tenth This.

Claims

1. a clock is adjusted circuit, it is characterized in that, comprising:

Configuration circuit is used for coming configuration parameter according to the instruction that receives;

Counting circuit is used for selecting count value according to described parameter, sends control signal after counting is full;

And control circuit, be used for after receiving described control signal, suppressing clock pulse, adjusted system clock is provided.

2. adjust circuit according to the clock of claim 1, it is characterized in that the instruction that configuration circuit receives comprises that clock differs numerical value.

3. adjust circuit according to the described clock of claim 2, it is characterized in that, described clock differs numerical value according to size with positive and negatively be divided into 32 grades, and with grade as described parameter.

4. adjust circuit according to the clock of claim 2, it is characterized in that, clock differs the frequency of numerical value decision control circuit suppressor pulse.

5. adjust circuit according to claim 1 or 2 described clocks, it is characterized in that, also comprise system processor, be used for sending instruction to configuration circuit.

6. adjust circuit according to the clock of claim 1, it is characterized in that, also comprise frequency dividing circuit, be used for the clock pulse that control circuit suppresses is carried out frequency division output.

7. adjust circuit according to the clock of claim 6, it is characterized in that, also comprise phase-locked loop, be used to provide the input clock of counting circuit.

8. adjust circuit according to the clock of claim 7, it is characterized in that system clock is 27MHz, the input clock of counting circuit is the frequency of the 27MHz of surpassing far away, will be less times greater than 27MHz behind the process frequency division.

9. adjust circuit according to the clock of claim 1, it is characterized in that, control circuit constitutes with door by one.