CN106505997A - clock and data recovery circuit and clock and data recovery method - Google Patents
clock and data recovery circuit and clock and data recovery method Download PDFInfo
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- CN106505997A CN106505997A CN201510558974.6A CN201510558974A CN106505997A CN 106505997 A CN106505997 A CN 106505997A CN 201510558974 A CN201510558974 A CN 201510558974A CN 106505997 A CN106505997 A CN 106505997A
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Abstract
The invention provides a clock and data recovery circuit and a clock and data recovery method. The phase detector compares the input data signal with the divided frequency signal and generates a phase indicating signal indicating a phase difference between the input data signal and the divided frequency signal. The phase interpolator performs phase interpolation on the received first and second clock signals to generate a phase interpolated signal. The finite state machine is coupled with the phase detector and the phase interpolator, and generates a control signal based on the phase indication signal and the phase interpolation signal. The divider-controllable frequency divider is coupled to the phase detector and the phase interpolator, and divides the frequency of the phase-interpolated signal having the second frequency based on a divider to generate a divided frequency signal. The invention can obtain wider working frequency range on the premise of not reducing the linearity characteristic.
Description
Technical field
The invention relates to a kind of seasonal pulse and data recovery circuit and seasonal pulse and data reconstruction method, and special
Do not relate to a kind of can be not required to reduce linearity characteristic on the premise of realize wider operating frequency range
Seasonal pulse and data recovery circuit and seasonal pulse and data reconstruction method.
Background technology
Seasonal pulse and data recovery (clock and data recovery, referred to as：CDR) circuit would generally be set
Put in receivers to execute sampling input data signal, then obtain the seasonal pulse in input data signal, and
And the seasonal pulse of sampling is retimed, use the function of realizing that seasonal pulse recovers.In traditional seasonal pulse and data
In restoring circuit, it is the component that is frequently applied in order to adjust the phase interpolator of sampling seasonal pulse.
As seasonal pulse is mainly subject to phase place with the operating frequency range of data recovery circuit with the characteristic of the linearity
The circuit characteristic of interpolater is affected, and therefore designer may need to take a lot of time in work in design
(trade-off) is made trade-offs between working frequency and linearity performance, however, being however still difficult to ensure that two
Person can have good characteristic simultaneously.
For example, in traditional phase interpolator design, which can be by setting up all on the output
Change capacitor array (switch capacitor array, referred to as：SCA) lifting operating frequency range.So
And, under this arrangement, the equivalent capacity of the outfan of phase interpolator is as switch-capacitor array
Parasitic capacitance effect and increase therewith so that the linearity of phase interpolator and maximum operating speed reduce.
Content of the invention
The present invention provides a kind of seasonal pulse and data recovery circuit and seasonal pulse and data reconstruction method, and which can be not
On the premise of reducing linearity characteristic, wider operating frequency range is obtained.
The seasonal pulse of the present invention includes phase detectors, phase interpolator, finite state with data recovery circuit
Machine and the controllable frequency eliminator of divisor.Phase detectors compare input data signal and frequency elimination signal, and produce
Raw phase indication signal is examined with indicating the phase contrast between input data signal and frequency elimination signal, wherein phase place
Survey device and be operated in first frequency.Phase interpolator receives the first clock signal, the second clock signal and control
Signal processed and phase interpolation is carried out to first and second clock signal according to control signal, use generation phase
Position interpolated signal, wherein phase interpolator are operated in second frequency, and second frequency is more than first frequency.
Finite state machine coupling phase detectors and phase interpolator, wherein finite state machine are based on the first frequency
The phase indication signal of rate produces control signal with the phase interpolated signals with second frequency.Divisor is controllable
Frequency eliminator coupling phase detectors and phase interpolator, the controllable frequency eliminator of divisor is based on divisor to having second
The phase interpolated signals of frequency carry out frequency elimination, use and produce the frequency elimination signal with first frequency, wherein remove
Number is set according to first frequency and the ratio of second frequency.
In an embodiment of the present invention, the operating frequency of phase interpolator is not with the of input data signal
The change of one frequency and change.
In an embodiment of the present invention, when the first frequency of input data signal changes, divisor foundation changes
First frequency after change is adjusted with the ratio of unchanged second frequency.
In an embodiment of the present invention, when phase indication signal is phase-lead signal, finite state machine
During the pulse of phase-lead signal in, with phase interpolated signals each pulse step improve control
The signal level of signal processed, and each step size of signal level is in arteries and veins according to phase interpolated signals
Number of pulses in during punching is determined.
In an embodiment of the present invention, the signal level of control signal is interior accurate from reference signal during pulse
Position is promoted to peak signal level, uses the rising edge for constituting control signal.
In an embodiment of the present invention, when phase indication signal is phase place lagging signal, finite state machine
During the pulse of phase place lagging signal in, with phase interpolated signals each pulse step reduce controlling
The signal level of signal processed, and each step size of signal level is in arteries and veins according to phase interpolated signals
Number of pulses in during punching is determined.
In an embodiment of the present invention, the signal level of control signal is interior accurate from peak signal during pulse
Position drops to reference signal level, uses the trailing edge for constituting control signal.
In an embodiment of the present invention, seasonal pulse also includes phase-locked loop with data recovery circuit.Phase-locked loop
Coupling phase interpolator, wherein phase-locked loop produces first and second clock signal.
In an embodiment of the present invention, seasonal pulse also includes deserializer with data recovery circuit.Deserializer
Input data signal is converted to and line number by coupling phase detectors, wherein deserializer according to frequency elimination signal
It is believed that number.
The seasonal pulse of the present invention is comprised the following steps with data reconstruction method：By phase detectors receives input
Data signal, and the first clock signal and the second clock signal, wherein phase are received by phase interpolator
Bit detector is operated in first frequency, and phase interpolator is operated in second frequency；According to control signal
Phase interpolation is carried out to first and second clock signal, generation phase interpolated signals are used；It is based on divisor pair
The phase interpolated signals with second frequency carry out frequency elimination, use and produce the frequency elimination signal with first frequency,
Wherein divisor is set according to first frequency and the ratio of second frequency；Compare input data signal and remove
Frequency signal, uses generation phase indication signal to indicate the phase place between input data signal and frequency elimination signal
Difference；Produced with the phase interpolated signals with second frequency based on the phase indication signal with first frequency
And adjust control signal；And input data signal is converted to parallel data signal.
In an embodiment of the present invention, seasonal pulse is further comprising the steps of with data reconstruction method：When input number
It is believed that number first frequency when changing, according to the ratio of first frequency and unchanged second frequency after changing
Value adjustment divisor.
In an embodiment of the present invention, based on the phase indication signal with first frequency and with the second frequency
The phase interpolated signals of rate are produced and are included the step of adjusting control signal：When phase indication signal is phase place
During leading edge signal, interior during the enable of phase-lead signal, with each pulse of phase interpolated signals
Step ground improves the signal level of control signal, and each step size of wherein signal level is according to phase place
The interior number of pulses during enable of interpolated signal is determined.
In an embodiment of the present invention, based on the phase indication signal with first frequency and with the second frequency
The phase interpolated signals of rate are produced and are included the step of adjusting control signal：When phase indication signal is phase place
During lagging signal, interior during the enable of phase place lagging signal, with each pulse of phase interpolated signals
Step ground reduces the signal level of control signal, and each step size of wherein signal level is according to phase place
The interior number of pulses during enable of interpolated signal is determined.
Based on above-mentioned, it is extensive with data with data recovery circuit and seasonal pulse that the embodiment of the present invention proposes a kind of seasonal pulse
Compound recipe method.By applying the framework of the controllable frequency eliminator of divisor, designer in seasonal pulse with data recovery circuit
Can be on the premise of being not required to additionally consider the frequency of input data signal, by the work frequency of phase interpolator
Rate is designed in the frequency with the highest linearity.Due to seasonal pulse main with the linearity of data recovery circuit
Affected by the characteristic of phase interpolator, therefore the seasonal pulse of the embodiment of the present invention can be not with data recovery circuit
On the premise of linearity characteristic need to be sacrificed, the characteristic of wider operational frequency range is realized.
It is that the features described above and advantage of the present invention can be become apparent, special embodiment below, and coordinate
Accompanying drawing accompanying drawing is described in detail below.
Description of the drawings
Schematic diagrams of the Fig. 1 for the seasonal pulse and data recovery circuit of one embodiment of the invention；
Signal waveform schematic diagrams of the Fig. 2A for the seasonal pulse and data recovery circuit of one embodiment of the invention；
Signal waveform schematic diagrams of Fig. 2 B for the seasonal pulse and data recovery circuit of another embodiment of the present invention；
The step of Fig. 3 is the seasonal pulse and data reconstruction method of one embodiment of the invention flow chart.
Description of reference numerals：
100：Seasonal pulse and data recovery circuit；
110：Phase detectors；
120：Phase interpolator；
130：Finite state machine；
140：The controllable frequency eliminator of divisor；
150：Phase-locked loop；
160：Deserializer；
DIN：Input data signal；
DOUT：Parallel data signal；
DN：Phase-lead signal；
F1：First frequency；
F2：Second frequency；
FE：The trailing edge of control signal；
RE：The rising edge of control signal；
S310～S360：Step；
SC：Control signal；
SIND：Phase indication signal；
SI：First clock signal；
SPI：Phase interpolated signals；
SPI’：Frequency elimination signal；
SQ：Second clock signal；
t1、t2、t3、t4：Period；
tPI、tPI’：Cycle；
UP：Phase place lagging signal；
VH：Peak signal level；
VL：Reference signal level；
VU：Unit signal level.
Specific embodiment
In order that present disclosure easily can be understood, below especially exemplified by embodiment as of the invention true
The example that can implement according to this in fact.In addition, all possible parts, identical used in drawings and the embodiments
Element/component/the step of label, is to represent same or like part.
Schematic diagrams of the Fig. 1 for the seasonal pulse and data recovery circuit of one embodiment of the invention.In the present embodiment,
Seasonal pulse and data recovery circuit 100 can be configured in receiver (receiver), and in order to recover from
The seasonal pulse of the input data that transmitter is received.Fig. 1 is refer to, seasonal pulse is included with data recovery circuit 100
Phase detectors 110, phase interpolator 120, finite state machine (finite state machine, referred to as：
FSM) 130, the controllable frequency eliminator 140, phase-locked loop of divisor (phase locked loop, referred to as：PLL)
150 and deserializer 160.
Phase detectors 110 are in order to comparing input data signal DINWith by controllable 140 institute of frequency eliminator of divisor
The frequency elimination signal S of outputPI', and produce instruction input data signal D according to thisINWith frequency elimination signal SPI'
The phase indication signal S of phase contrastIND.Phase detectors 110 can pass through to sample input data signal DIN
With frequency elimination signal SPI' in the voltage for being close to rising edge or trailing edge, and compare the voltage that is sampled to sentence
Disconnected input data signal DINPhase place be ahead or behind frequency elimination signal SPI' phase place, defeated so as to determine
Enter data signal DINWith frequency elimination signal SPI' between phase contrast.For example, work as input data signal
DINPhase-lead in frequency elimination signal SPI' phase place when, phase detectors 110 can produce phase-lead letter
Number DN is using as phase indication signal SIND.As input data signal DINPhase place lag behind frequency elimination signal
SPI' phase place when, phase detectors 110 can then produce phase place lagging signal UP using as phase place indicate letter
Number SIND.
In the present embodiment, phase detectors 110 are operated in first frequency F1, and which represents phase detectors
Signal (that is, input data signal D received by 110INWith frequency elimination signal SPI') it is first frequency F1
Signal.Furthermore, the operating frequency of phase detectors 110 be can be according to input data signal
DINAnd corresponding selection.
Additionally, the signal received by phase detectors 110 from the controllable frequency eliminator 140 of divisor can be considered
Seasonal pulse after one recovery.Phase detectors 110 can further by recovery after seasonal pulse and input data believe
Number DINIt is supplied to deserializer 160.
The controllable frequency eliminator 140 of the coupling finite state machine 130, divisor of phase interpolator 120 and lock phase are returned
Road 150.Phase interpolator 120 receives the first clock signal S exported by phase-locked loop 150IWith
Two clock signal SQ, and control signal S exported according to finite state machine 130CFirst seasonal pulse is believed
Number SIWith the second clock signal SQInterpolative operation is carried out, generation phase interpolated signals S are usedPI.
In the present embodiment, phase interpolator 120 is operated in second frequency F2, and which represents phase interpolator
Signal (that is, the first clock signal S received by 120IWith the second clock signal SQ) with produced
Signal (that is, phase interpolated signals SPI) it is all second frequency F2.Furthermore, phase interpolator
120 operating frequency is can be considered according to the optimization of its linearity and be selected.In actual applications, by
In the operating frequency of phase detectors 110 be according to input data signal DINFrequency and select and phase
The operating frequency of position interpolater 120 is to consider according to its linearity optimization and select, therefore described second
Frequency F2 is typically larger than first frequency F1.
Finite state machine 130 is coupled phase detectors 110 and is referred to based on the phase place with first frequency F1
Show signal S-IND with phase interpolated signals S with second frequency F2PIProduce control signal SC, use
The interpolative operation of control phase interpolator 120.
The controllable coupling of frequency eliminator 140 phase detectors 110 of divisor and phase interpolator 120.Divisor is controllable
Frequency eliminator 140 be in order to based on divisor N to phase interpolated signals S with second frequency F2PICarry out
Frequency elimination, uses and produces the frequency elimination signal S with first frequency F1PI’.In the present embodiment, divisor N is
Set according to first frequency F1 and the ratio of second frequency F2.For example, if first frequency F1
For 2.5GHz, and second frequency F2 is 40GHz, then divisor N can be set to 16.
Phase-locked loop 150 couples phase interpolator 120 and produces the first clock signal SIWith the second seasonal pulse
Signal SQ, wherein the first clock signal SIFor in-phase signal, and the second clock signal SQFor frequency and the
One clock signal SIIdentical orthogonal signalling, and the first clock signal SIWith the second clock signal SQ's
Phase place is mutually orthogonal.In other words, the first clock signal SIWith the second clock signal SQBetween have 90 degree
Phase contrast.
Seasonal pulse (that is, frequency elimination letter after the coupling phase detectors 110 of deserializer 160 and foundation recovery
Number SPI') by input data signal DINBe converted to parallel data signal DOUT.
In the seasonal pulse of the present embodiment with the design of data recovery circuit 100, due to the controllable frequency eliminator of divisor
140 divisor N is can to set with the ratio of second frequency F2 according to first frequency F1, and divisor
Controllable frequency eliminator 140 is that second frequency F2 frequency eliminations are converted to first frequency F1, therefore phase interpolator
120 is can be not required to consider input data signal DINFrequency and design in the frequency with the highest linearity
In rate.In other words, the operating frequency of phase interpolator 120 is not required to input data signal DIN?
The change of one frequency F1 and change.
On the other hand, in the existing practice, traditional finite state machine would generally be based on two and there is phase
The reference signal of same frequency is producing control signal.However, in an embodiment of the present invention, finite state
Machine 130 can produce control signal S based on the reference signal of two different frequenciesCSo that phase interpolator 120
Operating frequency can be fixed on maintain optimum linear degree frequency, without with input data signal
DINFrequency adjustment.The concrete running of finite state machine 130 can be further described in subsequent embodiment.
Accordingly, the linearity due to seasonal pulse with data recovery circuit 100 is mainly subject to phase interpolator 120
Characteristic affect, therefore the seasonal pulse of the embodiment of the present invention and data recovery circuit 100 can be not required to sacrifice linear
On the premise of degree characteristic, the characteristic of wider operating frequency range is realized.
The beneath finite state machine 130 for further illustrating this case with Fig. 2A and Fig. 2 B embodiments concrete
Running.Signal waveform schematic diagrams of the Fig. 2A for the seasonal pulse and data recovery circuit of one embodiment of the invention.
Signal waveform schematic diagrams of Fig. 2 B for the seasonal pulse and data recovery circuit of another embodiment of the present invention.
Referring to Fig. 1 and Fig. 2A, in 16 times that this hypothesis second frequency F2 is first frequency F1
(that is, divisor N is equal to 16) is so that the linearity can be optimized.With phase indication signal SIND, phase place
Interpolated signal SPIAnd control signal SCFrom the point of view of the waveform in period t1, phase-lead signal DN can be in
Enable (being pulled to high levle) in period t1, its represent now input data signal DINPhase place fall behind
In frequency elimination signal SPI'/phase interpolated signals SPIPhase place.
In period t1, finite state machine 130 can be with phase interpolated signals SPIEach pulse step
Ground lifts control signal SCSignal level.For example, control signal SCSignal level can be in phase
Position interpolated signal SPICycle tPIInterior from reference signal level VLRise unit signal level VU, connect
In phase interpolated signals SPINext cycle rise unit signal level V againU, until control letter
Number SCSignal level reach peak signal level VH.Accordingly, control signal SCSignal level i.e. can
From reference signal level V in during the pulse of phase-lead signal DNLIt is promoted to peak signal level
VH, use composition control signal SCRising edge RE in waveform.
On the other hand, with phase indication signal SIND, phase interpolated signals SPIAnd control signal SCYu Qi
Between from the point of view of waveform in t2, phase-lead signal DN can be in forbidden energy (being pulled down to low level) in period t2
And phase place lagging signal UP then can be in enable in period t2, which represents now input data signal DIN's
Phase-lead is in frequency elimination signal SPI'/phase interpolated signals SPIPhase place.
In period t2, finite state machine 130 can be with phase interpolated signals SPIEach pulse step
Ground reduces control signal SCSignal level.For example, control signal SCSignal level can be in phase
Position interpolated signal SPICycle tPI' interior from peak signal level VHReduce unit signal level VU, connect
In phase interpolated signals SPINext cycle reduce unit signal level V againU, until control letter
Number SCSignal level be down to reference signal level VL.Accordingly, control signal SCSignal level i.e. can
From peak signal level V in during the pulse of phase place lagging signal UPHIt is reduced to reference signal level
VL, use composition control signal SCTrailing edge FE in waveform.
In the present embodiment, signal level size (that is, unit signal level V of each stepUSize)
It is according to phase interpolated signals SPIDuring the pulse of phase-lead signal DN/ phase place lagging signal UP
Number of pulses determined.As the present embodiment assumes that 16 that second frequency F2 is first frequency F1
Times, therefore interior during the pulse of phase-lead signal DN/ phase place lagging signal UP, phase interpolation is believed
Number SPIThere can be 16 pulses so that unit signal level VUSize can utilize (VH-VL)/16
Calculate.
Referring to Fig. 1 and Fig. 2 B, the running of the finite state machine 130 depicted in Fig. 2 B substantially with
Aforementioned Fig. 2A embodiments are similar.Main Differences between the two are that the present embodiment assumes that second frequency F2
There can be the optimal linearity during 8 times (that is, divisor N be equal to 8) for first frequency F1.
With control signal SCOverall waveform from the point of view of, rising edge RE is respectively formed in phase with trailing edge FE
T4 during the pulse of t3 and phase place lagging signal UP during the pulse of position leading edge signal DN.It follows that
Even if input data signal DINFrequency be changed into the twice of previous embodiment, finite state machine 130 still may be used
Produce corresponding control signal SCSo that phase interpolator 120 carries out interpolative operation.That is, work as input
Data signal DINFrequency shift when, designer only needs to adjust the divisor N of controllable for divisor frequency eliminator 140
Whole to the operating frequency demand for meeting phase detectors 110, without adjustment phase place interpolater again
120 operating frequency.
The step of Fig. 3 is the seasonal pulse and data reconstruction method of one embodiment of the invention flow chart.Refer to figure
3, in step S310,110 receives input data signal D of phase detectorsIN, and phase interpolator
120 receive the first clock signal SIWith the second clock signal SQ.In the present embodiment, phase detectors 110
It is to be operated in first frequency F1, and phase interpolator 120 is to be operated in second frequency F2.
In step s 320, device 120 is pitched in phase place according to control signal SCTo the first clock signal SIWith
Second clock signal SQInterpolative operation is carried out, generation phase interpolated signals S are usedPI.Believe in phase interpolation
Number SPIAfter generation, in step S330, the controllable frequency eliminator 140 of divisor can be based on divisor N to having the
Phase interpolated signals S of two frequencies F2PIFrequency elimination is carried out, is used and is produced the frequency elimination letter with first frequency F1
Number SPI’.In the present embodiment, divisor N be ratio according to first frequency F1 with second frequency F2 and
Set.
In step S340, phase detectors 110 can compare input data signal DINWith frequency elimination signal
SPI', generation is used in order to indicating input data signal DINWith frequency elimination signal SPI' between phase contrast phase
Position indication signal SIND.Accordingly, in step S350, finite state machine 130 can be based on has first
The phase indication signal S of frequency F1INDWith phase interpolated signals S for all having second frequency F2PIProduce simultaneously
Adjustment control signal SC.In step S360, the seasonal pulse after deserializer 160 is understood based on recovery will be defeated
Enter data signal DINBe converted to parallel data signal DOUT, and by parallel data signal DOUTIt is transferred to
Back-end circuit.
In addition, aforementioned Fig. 1 to Fig. 2 B embodiments can be based in one skilled in the art, and
The sufficient teaching for being related to the seasonal pulse described in Fig. 3 and data reconstruction method is obtained, therefore is not repeated to go to live in the household of one's in-laws on getting married in this
State.
In sum, a kind of seasonal pulse of embodiment of the present invention proposition is extensive with data with data recovery circuit and seasonal pulse
Compound recipe method.By applying the framework of the controllable frequency eliminator of divisor, designer in seasonal pulse with data recovery circuit
Can be on the premise of being not required to additionally consider the frequency of input data signal, by the work frequency of phase interpolator
Rate is designed in the frequency with the highest linearity.Due to seasonal pulse main with the linearity of data recovery circuit
Affected by the characteristic of phase interpolator, therefore the seasonal pulse of the embodiment of the present invention can be not with data recovery circuit
On the premise of linearity characteristic need to be sacrificed, the characteristic of wider operational frequency range is realized.
Finally it should be noted that：Various embodiments above is only in order to illustrating technical scheme rather than right
Which limits；Although being described in detail to the present invention with reference to foregoing embodiments, this area common
Technical staff should be understood：Which still can be modified to the technical scheme described in foregoing embodiments,
Or equivalent is carried out to which part or all technical characteristic；And these modifications or replacement, and
The scope of the essence disengaging various embodiments of the present invention technical scheme of appropriate technical solution is not made.
Claims (15)
1. a kind of seasonal pulse and data recovery circuit, it is characterised in that include：
Phase detectors, compare input data signal and frequency elimination signal, and produce phase indication signal with
Indicate the phase contrast between the input data signal and the frequency elimination signal, wherein described phase detectors
It is operated in first frequency；
Phase interpolator, receives the first clock signal, the second clock signal and control signal and foundation
The control signal carries out phase interpolation to described first with second clock signal, uses generation phase place
Interpolated signal, wherein described phase interpolator are operated in second frequency, and the second frequency is more than institute
State first frequency；
Finite state machine, couples the phase detectors and the phase interpolator, wherein described limited shape
State machine based on the phase indication signal with the first frequency and has described in the second frequency
Phase interpolated signals produce the control signal；And
The controllable frequency eliminator of divisor, couples the phase detectors and the phase interpolator, and the divisor can
Control frequency eliminator carries out frequency elimination based on divisor to the phase interpolated signals with the second frequency, uses
The frequency elimination signal with the first frequency is produced, wherein described divisor is according to the first frequency
Set with the ratio of the second frequency.
2. seasonal pulse according to claim 1 and data recovery circuit, it is characterised in that the phase
The operating frequency of position interpolater does not become with the change of the first frequency of the input data signal
Dynamic.
3. seasonal pulse according to claim 2 and data recovery circuit, it is characterised in that when described
When the first frequency of input data signal changes, the divisor is according to the first frequency after changing
Adjust with the ratio of the unchanged second frequency.
4. seasonal pulse according to claim 1 and data recovery circuit, it is characterised in that when described
When phase indication signal is phase-lead signal, arteries and veins of the finite state machine in the phase-lead signal
During punching, with the phase interpolated signals each pulse step improve the letter of the control signal
Number level, and each step size of the signal level is described according to the phase interpolated signals
Number of pulses in during pulse is determined.
5. seasonal pulse according to claim 4 and data recovery circuit, it is characterised in that the control
The signal level of signal processed is interior during the pulse to be promoted to peak signal level from reference signal level,
Use the rising edge for constituting the control signal.
6. seasonal pulse according to claim 1 and data recovery circuit, it is characterised in that when described
When phase indication signal is phase place lagging signal, arteries and veins of the finite state machine in the phase place lagging signal
During punching, with the phase interpolated signals each pulse step reduce the letter of the control signal
Number level, and each step size of the signal level is described according to the phase interpolated signals
Number of pulses in during pulse is determined.
7. seasonal pulse according to claim 6 and data recovery circuit, it is characterised in that the control
The signal level of signal processed is interior during the pulse to drop to reference signal level from peak signal level,
Use the trailing edge for constituting the control signal.
8. seasonal pulse according to claim 1 and data recovery circuit, it is characterised in that also include：
Phase-locked loop, couples the phase interpolator, and wherein described phase-locked loop produces described first and institute
State the second clock signal.
9. seasonal pulse according to claim 1 and data recovery circuit, it is characterised in that also include：
Deserializer, couples the phase detectors, and wherein described deserializer is according to the frequency elimination signal
The input data signal is converted to parallel data signal.
10. a kind of seasonal pulse and data reconstruction method, it is characterised in that include：
By phase detectors receives input data signal, and the first seasonal pulse is received by phase interpolator
Signal and the second clock signal, wherein described phase detectors are operated in first frequency, and the phase place
Interpolator operative is in second frequency；
Phase interpolation is carried out to described first with second clock signal according to control signal, use generation
Phase interpolated signals；
Frequency elimination is carried out to the phase interpolated signals with the second frequency based on divisor, generation is used
There is the frequency elimination signal of the first frequency, wherein described divisor is according to the first frequency and described the
The ratio of two frequencies and set；
The comparison input data signal and the frequency elimination signal, use generation phase indication signal to indicate
Phase contrast between the input data signal and the frequency elimination signal；
Based on the phase indication signal with the first frequency and with described in the second frequency
Phase interpolated signals are produced and adjust the control signal；And
The input data signal is converted to parallel data signal.
11. seasonal pulse according to claim 10 and data reconstruction method, it is characterised in that also wrap
Include：
When the first frequency of the input data signal changes, according to first frequency after changing
Rate adjusts the divisor with the ratio of the unchanged second frequency.
12. seasonal pulse according to claim 10 and data reconstruction method, it is characterised in that be based on
There is the phase indication signal and the phase interpolation with the second frequency of the first frequency
Signal is produced and is included the step of adjusting the control signal：
When the phase indication signal is phase-lead signal, in the enable phase of the phase-lead signal
In, with the phase interpolated signals each pulse step improve the control signal signal accurate
Position, each step size of wherein described signal level is in the enable according to the phase interpolated signals
Number of pulses in period is determined.
13. seasonal pulse according to claim 12 and data reconstruction method, it is characterised in that described
The signal level of control signal is interior during the enable to be promoted to peak signal standard from reference signal level
Position, uses the rising edge for constituting the control signal.
14. seasonal pulse according to claim 10 and data reconstruction method, it is characterised in that be based on
There is the phase indication signal and the phase interpolation with the second frequency of the first frequency
Signal is produced and is included the step of adjusting the control signal：
When the phase indication signal is phase place lagging signal, in the enable phase of the phase place lagging signal
In, with the phase interpolated signals each pulse step reduce the control signal signal accurate
Position, each step size of wherein described signal level is in the enable according to the phase interpolated signals
Number of pulses in period is determined.
15. seasonal pulse according to claim 14 and data reconstruction method, it is characterised in that described
The signal level of control signal is interior during the enable to drop to reference signal standard from peak signal level
Position, uses the trailing edge for constituting the control signal.
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| CN201510558974.6A CN106505997B (en) | 2015-09-06 | 2015-09-06 | Clock and data recovery circuit and clock and data recovery method |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109412584A (en) * | 2017-08-16 | 2019-03-01 | 台湾积体电路制造股份有限公司 | Clock and data recovery circuit and its implementation method |
| CN111092617A (en) * | 2018-10-23 | 2020-05-01 | 台湾积体电路制造股份有限公司 | Frequency divider circuit |
| CN112260685A (en) * | 2019-07-22 | 2021-01-22 | 创意电子股份有限公司 | Clock data recovery device and method |
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| CN109412584A (en) * | 2017-08-16 | 2019-03-01 | 台湾积体电路制造股份有限公司 | Clock and data recovery circuit and its implementation method |
| CN109412584B (en) * | 2017-08-16 | 2022-07-01 | 台湾积体电路制造股份有限公司 | Clock and data recovery circuit and method of implementing the same |
| CN111092617A (en) * | 2018-10-23 | 2020-05-01 | 台湾积体电路制造股份有限公司 | Frequency divider circuit |
| CN112260685A (en) * | 2019-07-22 | 2021-01-22 | 创意电子股份有限公司 | Clock data recovery device and method |
| CN112260685B (en) * | 2019-07-22 | 2023-08-11 | 创意电子股份有限公司 | Clock data recovery device and method |
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