CN106505997B - Clock and data recovery circuit and clock and data recovery method - Google Patents
Clock and data recovery circuit and clock and data recovery method Download PDFInfo
- Publication number
- CN106505997B CN106505997B CN201510558974.6A CN201510558974A CN106505997B CN 106505997 B CN106505997 B CN 106505997B CN 201510558974 A CN201510558974 A CN 201510558974A CN 106505997 B CN106505997 B CN 106505997B
- Authority
- CN
- China
- Prior art keywords
- signal
- phase
- frequency
- pulse
- clock
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000011084 recovery Methods 0.000 title claims abstract description 46
- 238000000034 method Methods 0.000 title claims abstract description 20
- 230000008030 elimination Effects 0.000 claims description 36
- 238000003379 elimination reaction Methods 0.000 claims description 36
- 230000000630 rising effect Effects 0.000 claims description 6
- 210000001367 artery Anatomy 0.000 claims description 3
- 210000003462 vein Anatomy 0.000 claims description 3
- 230000007423 decrease Effects 0.000 claims 2
- 238000010586 diagram Methods 0.000 description 6
- 239000003990 capacitor Substances 0.000 description 3
- 238000005070 sampling Methods 0.000 description 3
- 238000005457 optimization Methods 0.000 description 2
- 230000018199 S phase Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000012423 maintenance Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
Landscapes
- Manipulation Of Pulses (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
本发明提供一种时脉与数据恢复电路及时脉与数据恢复方法，所述时脉与数据恢复电路包括相位检测器、相位内插器、有限状态机以及除数可控除频器。相位检测器比较输入数据信号与除频信号并产生相位指示信号以指示输入数据信号与除频信号间的相位差。相位内插器对所接收的第一与第二时脉信号进行相位内插，藉以产生相位内插信号。有限状态机耦接相位检测器与相位内插器，并且基于相位指示信号与相位内插信号产生控制信号。除数可控除频器耦接相位检测器与相位内插器，并且基于一除数对具有第二频率的相位内插信号进行除频，藉以产生除频信号。本发明可在不降低线性度特性的前提下，获得较宽的工作频率范围。
The present invention provides a clock and data recovery circuit and a clock and data recovery method, wherein the clock and data recovery circuit includes a phase detector, a phase interpolator, a finite state machine, and a divisor-controllable frequency divider. The phase detector compares the input data signal with the frequency division signal and generates a phase indication signal to indicate the phase difference between the input data signal and the frequency division signal. The phase interpolator performs phase interpolation on the received first and second clock signals to generate a phase interpolation signal. The finite state machine couples the phase detector and the phase interpolator, and generates a control signal based on the phase indication signal and the phase interpolation signal. The divisor-controllable frequency divider couples the phase detector and the phase interpolator, and performs frequency division on the phase interpolation signal having a second frequency based on a divisor to generate a frequency division signal. The present invention can obtain a wider operating frequency range without reducing the linearity characteristics.
Description
Technical field
The invention relates to a kind of clock pulses and data recovery circuit and clock pulse and data reconstruction method, and more particularly to
It can realize that the clock pulse of wider operating frequency range and data restore electricity under the premise of being not required to reduces linearity characteristic in a kind of
Road and clock pulse and data reconstruction method.
Background technique
Clock pulse and data, which restore (clock and data recovery, referred to as: CDR) circuit, would generally be arranged on and connect
Input data signal is sampled to execute in receipts machine, then obtains the clock pulse in input data signal, and again by the clock pulse of sampling
Periodically, the function of realizing that clock pulse restores is used.In traditional clock pulse and data recovery circuit, to adjust the phase of sampling clock pulse
Position interpolater is the circuit element being frequently applied to.
Due to clock pulse and data recovery circuit operating frequency range and the linearity characteristic mainly by phase interpolator
Circuit characteristic influenced, therefore designer may need to take a lot of time and show in working frequency and the linearity in design
Between make trade-offs (trade-off), however, both being however still difficult to ensure can there is good characteristic simultaneously.
It for example, can be by adding a switch-capacitor battle array on the output in traditional phase interpolator design
Column (switch capacitor array, referred to as: SCA) Lai Tisheng operating frequency range.However, under this arrangement, in phase
Plug in device output end equivalent capacity as the parasitic capacitance effect of switch-capacitor array and increase therewith so that in phase
The linearity and maximum operating speed for plugging in device reduce.
Summary of the invention
The present invention provides a kind of clock pulse and data recovery circuit and clock pulse and data reconstruction method, can not reduce it is linear
Under the premise of spending characteristic, wider operating frequency range is obtained.
Clock pulse of the invention includes phase detectors, phase interpolator, finite state machine with data recovery circuit and removes
The controllable frequency eliminator of number.Phase detectors compare input data signal and frequency elimination signal, and generate phase indication signal to indicate
Phase difference between input data signal and frequency elimination signal, wherein phase detectors work is in first frequency.Phase interpolator connects
Receive the first clock signal, the second clock signal and control signal and according to control signal to first and second clock signal into
Row phase interpolation uses generation phase interpolated signals, and wherein phase interpolator work is in second frequency, and second frequency is greater than
First frequency.Finite state machine couples phase detectors and phase interpolator, and wherein finite state machine is based on having first frequency
Phase indication signal with second frequency phase interpolated signals generate control signal.The controllable frequency eliminator of divisor couples phase
Detector and phase interpolator, the controllable frequency eliminator of divisor remove the phase interpolated signals with second frequency based on divisor
Frequently, the frequency elimination signal for generating and there is first frequency is used, wherein divisor is the ratio according to first frequency and second frequency and sets
It is fixed.
In an embodiment of the present invention, the working frequency of phase interpolator is not with the first frequency of input data signal
Change and changes.
In an embodiment of the present invention, when the first frequency of input data signal changes, divisor is according to the after changing
The ratio of one frequency and unchanged second frequency and adjust.
In an embodiment of the present invention, when phase indication signal is phase-lead signal, finite state machine is led in phase
During the pulse of first signal, with phase interpolated signals each pulse step improve control signal signal level, and
And each step size of signal level is that number of pulses of foundation phase interpolated signals during pulse is determined.
In an embodiment of the present invention, the signal level for controlling signal is promoted to during pulse from reference signal level
Peak signal level uses the rising edge for constituting control signal.
In an embodiment of the present invention, when phase indication signal is phase lagging signal, finite state machine is fallen in phase
Afterwards during the pulse of signal, with phase interpolated signals each pulse step the signal level of low control signal drops, and
And each step size of signal level is that number of pulses of foundation phase interpolated signals during pulse is determined.
In an embodiment of the present invention, the signal level for controlling signal drops to during pulse from peak signal level
Reference signal level uses the failing edge for constituting control signal.
In an embodiment of the present invention, clock pulse and data recovery circuit further include phase-locked loop.Phase-locked loop couples phase
Interpolater, wherein phase-locked loop generates first and second clock signal.
In an embodiment of the present invention, clock pulse and data recovery circuit further include deserializer.Deserializer couples phase
Detector, wherein input data signal is converted to parallel data signal according to frequency elimination signal by deserializer.
Clock pulse and data reconstruction method of the invention is the following steps are included: receive input data letter by phase detectors
Number, and the first clock signal and the second clock signal are received by phase interpolator, wherein phase detectors work is first
Frequency, and phase interpolator work is in second frequency；First and second clock signal is carried out in phase according to control signal
It inserts, uses generation phase interpolated signals；Frequency elimination is carried out to the phase interpolated signals with second frequency based on divisor, uses generation
Frequency elimination signal with first frequency, wherein divisor is the ratio according to first frequency and second frequency and sets；Compare input
Data-signal and frequency elimination signal are used and generate phase indication signal to indicate the phase between input data signal and frequency elimination signal
Difference；It is generated based on the phase indication signal with first frequency with the phase interpolated signals with second frequency and adjusts control letter
Number；And input data signal is converted into parallel data signal.
In an embodiment of the present invention, clock pulse and data reconstruction method are further comprising the steps of: when input data signal
When first frequency changes, the ratio according to first frequency and unchanged second frequency after changing adjusts divisor.
In an embodiment of the present invention, based on the phase indication signal with first frequency and with the phase of second frequency
Interpolated signal generates and includes: to lead when phase indication signal is phase-lead signal in phase the step of adjusting control signal
During the enable of first signal, with phase interpolated signals each pulse step improve control signal signal level,
Each step size of middle signal level is that the number of pulses according to phase interpolated signals during enable is determined.
In an embodiment of the present invention, based on the phase indication signal with first frequency and with the phase of second frequency
Interpolated signal generates and includes: to fall when phase indication signal is phase lagging signal in phase the step of adjusting control signal
Afterwards during the enable of signal, with phase interpolated signals each pulse step the signal level of low control signal drops,
Each step size of middle signal level is that the number of pulses according to phase interpolated signals during enable is determined.
Based on above-mentioned, the embodiment of the present invention proposes a kind of clock pulse and data recovery circuit and clock pulse and data reconstruction method.
By applying the framework of the controllable frequency eliminator of divisor in clock pulse and data recovery circuit, designer can be not required to additionally consider it is defeated
Under the premise of the frequency for entering data-signal, the working frequency of phase interpolator is designed in the frequency with the highest linearity.
Characteristic due to the linearity of clock pulse and data recovery circuit mainly by phase interpolator is influenced, thus the embodiment of the present invention when
Arteries and veins and data recovery circuit can realize the characteristic of wider operational frequency range under the premise of being not required to sacrifice linearity characteristic.
To make the foregoing features and advantages of the present invention clearer and more comprehensible, special embodiment below, and cooperate attached drawing attached drawing
It is described in detail below.
Detailed description of the invention
Fig. 1 is the clock pulse of one embodiment of the invention and the schematic diagram of data recovery circuit；
Fig. 2A is the clock pulse of one embodiment of the invention and the signal waveform schematic diagram of data recovery circuit；
Fig. 2 B is the clock pulse of another embodiment of the present invention and the signal waveform schematic diagram of data recovery circuit；
Fig. 3 is the clock pulse of one embodiment of the invention and the step flow chart of data reconstruction method.
Description of symbols:
100: clock pulse and data recovery circuit；
110: phase detectors；
120: phase interpolator；
130: finite state machine；
140: the controllable frequency eliminator of divisor；
150: phase-locked loop；
160: deserializer；
DIN: input data signal；
DOUT: parallel data signal；
DN: phase-lead signal；
F1: first frequency；
F2: second frequency；
FE: the failing edge of signal is controlled；
RE: the rising edge of signal is controlled；
S310~S360: step；
SC: control signal；
SIND: phase indication signal；
SI: the first clock signal；
SPI: phase interpolated signals；
SPI': frequency elimination signal；
SQ: the second clock signal；
T1, t2, t3, t4: period；
tPI、tPI': the period；
UP: phase lagging signal；
VH: peak signal level；
VL: reference signal level；
VU: unit signal level.
Specific embodiment
In order to be illustrated that the contents of the present invention more easily, spy can actually evidence as the present invention for embodiment below
With the example of implementation.In addition, all possible places, use element/component/step of identical label in the drawings and embodiments,
It is to represent same or like component.
Fig. 1 is the clock pulse of one embodiment of the invention and the schematic diagram of data recovery circuit.In the present embodiment, clock pulse and number
It can be configured in receiver (receiver) according to restoring circuit 100, and to restore from the received input data of transmitter
Clock pulse.Fig. 1 is please referred to, clock pulse and data recovery circuit 100 include phase detectors 110, phase interpolator 120, limited shape
130, the controllable frequency eliminator 140 of divisor, phase-locked loop (phase state machine (finite state machine, referred to as: FSM)
Locked loop, referred to as: PLL) 150 and deserializer 160.
Phase detectors 110 are to compare input data signal DINWith the frequency elimination exported by the controllable frequency eliminator 140 of divisor
Signal SPI', and instruction input data signal D is generated accordinglyINWith frequency elimination signal SPI' phase difference phase indication signal
SIND.Phase detectors 110 can be by sampling input data signal DINWith frequency elimination signal SPI' in close to rising edge or failing edge
Voltage, and compare the voltage that is sampled to judge input data signal DINPhase be ahead or behind frequency elimination signal SPI’
Phase, to determine input data signal DINWith frequency elimination signal SPI' between phase difference.For example, when input data is believed
Number DINPhase-lead in frequency elimination signal SPI' phase when, phase detectors 110 can generate phase-lead signal DN using as
Phase indication signal SIND.As input data signal DINPhase lag behind frequency elimination signal SPI' phase when, phase detectors
110 can generate phase lagging signal UP using as phase indication signal SIND。
In the present embodiment, the work of phase detectors 110 indicates that phase detectors 110 are received in first frequency F1
The signal arrived is (that is, input data signal DINWith frequency elimination signal SPI') be first frequency F1 signal.Furthermore, phase
The working frequency of detector 110 is can be according to input data signal DINAnd corresponding selection.
In addition, after the signal received by the controllable frequency eliminator 140 of divisor of phase detectors 110 can be considered as a recovery
Clock pulse.Phase detectors 110 can be further by the clock pulse and input data signal D after recoveryINIt is supplied to deserializer 160.
Phase interpolator 120 couples finite state machine 130, the controllable frequency eliminator 140 of divisor and phase-locked loop 150.Phase
Interpolater 120 receives the first clock signal S exported by phase-locked loop 150IWith the second clock signal SQ, and according to limited
The control signal S that state machine 130 is exportedCTo the first clock signal SIWith the second clock signal SQInterpolative operation is carried out, production is used
Raw phase interpolated signals SPI。
In the present embodiment, the work of phase interpolator 120 indicates that phase interpolator 120 is received in second frequency F2
The signal arrived is (that is, the first clock signal SIWith the second clock signal SQ) with generated signal (that is, phase interpolated signals SPI)
It is all second frequency F2.Furthermore, the working frequency of phase interpolator 120 is can be examined according to the optimization of its linearity
It measures and selects.In practical applications, since the working frequency of phase detectors 110 is according to input data signal DINFrequency and
It selects and the working frequency of phase interpolator 120 is considered and selected according to its linearity optimization, therefore second frequency
Rate F2 is typically larger than first frequency F1.
Finite state machine 130 couples phase detectors 110 and based on the phase indication signal S- with first frequency F1
The IND and phase interpolated signals S with second frequency F2PIGenerate control signal SC, use the interpolation of control phase interpolator 120
Operation.
The controllable frequency eliminator 140 of divisor couples phase detectors 110 and phase interpolator 120.The controllable frequency eliminator 140 of divisor is
To based on divisor N and to the phase interpolated signals S with second frequency F2PIFrequency elimination is carried out, using generation has first frequency
The frequency elimination signal S of F1PI'.In the present embodiment, divisor N be according to first frequency F1 and second frequency F2 ratio and set.It lifts
For example, if first frequency F1 is 2.5GHz, and second frequency F2 is 40GHz, then divisor N can be set to 16.
Phase-locked loop 150 couples phase interpolator 120 and generates the first clock signal SIWith the second clock signal SQ,
In the first clock signal SIFor in-phase signal, and the second clock signal SQFor frequency and the first clock signal SIIdentical orthogonal letter
Number, and the first clock signal SIWith the second clock signal SQPhase it is mutually orthogonal.In other words, the first clock signal SIWith
Two clock signal SQBetween with 90 degree of phase difference.
Deserializer 160 couples phase detectors 110 and according to the clock pulse after recovery (that is, frequency elimination signal SPI') will be defeated
Enter data-signal DINBe converted to parallel data signal DOUT。
In the clock pulse of the present embodiment and the design of data recovery circuit 100, due to the divisor of the controllable frequency eliminator 140 of divisor
N be can according to first frequency F1 and second frequency F2 ratio and set, and the controllable frequency eliminator 140 of divisor is by second frequency
F2 frequency elimination is converted to first frequency F1, therefore phase interpolator 120 is can be not required to consider input data signal DINFrequency and
Design is in the frequency with the highest linearity.In other words, the working frequency of phase interpolator 120 is not required to believe with input data
Number DINFirst frequency F1 change and change.
On the other hand, in the existing practice, traditional finite state machine would generally have identical frequency based on two
Reference signal generates control signal.However, in an embodiment of the present invention, finite state machine 130 can be based on two different frequencies
Reference signal come generate control signal SC, the working frequency of phase interpolator 120 is allowed to be fixed on maintenance optimum linear
The frequency of degree, without with input data signal DINFrequency adjustment.The specific running of finite state machine 130 can be subsequent
Embodiment further describes.
Accordingly, since the linearity of clock pulse and data recovery circuit 100 is mainly by the characteristic shadow of phase interpolator 120
Ring, thus the clock pulse of the embodiment of the present invention and data recovery circuit 100 can under the premise of being not required to sacrifice linearity characteristic, realize compared with
The characteristic of wide operating frequency range.
The beneath specific running that the finite state machine 130 of this case is further illustrated with Fig. 2A and Fig. 2 B embodiment.Fig. 2A
For the clock pulse of one embodiment of the invention and the signal waveform schematic diagram of data recovery circuit.Fig. 2 B is another embodiment of the present invention
The signal waveform schematic diagram of clock pulse and data recovery circuit.
Referring to Fig. 1 and Fig. 2A, in 16 times that this hypothesis second frequency F2 is first frequency F1 (that is, divisor N is equal to
16) so that the linearity can be optimized.With phase indication signal SIND, phase interpolated signals SPIAnd control signal SCIn period t1
From the point of view of interior waveform, phase-lead signal DN can indicate input data at this time in enable (being pulled to high levle) in period t1
Signal DINPhase lag behind frequency elimination signal SPI'/phase interpolated signals SPIPhase.
In period t1, finite state machine 130 can be with phase interpolated signals SPIEach pulse step promote control
Signal SCSignal level.For example, signal S is controlledCSignal level can be in phase interpolated signals SPIPeriod tPIIt is interior from
Reference signal level VLRise a unit signal level VU, then in phase interpolated signals SPITo rise one again single next period
Position signal level VU, until controlling signal SCSignal level reach peak signal level VH.Accordingly, signal S is controlledCSignal
Level i.e. can be during the pulse of phase-lead signal DN from reference signal level VLIt is promoted to peak signal level VH, use
Constitute control signal SCRising edge RE in waveform.
On the other hand, with phase indication signal SIND, phase interpolated signals SPIAnd control signal SCWaveform in period t2
From the point of view of, phase-lead signal DN can be in forbidden energy (being pulled down to low level) in period t2 and phase lagging signal UP then can be in period t2
Interior enable indicates input data signal D at this timeINPhase-lead in frequency elimination signal SPI'/phase interpolated signals SPIPhase.
In period t2, finite state machine 130 can be with phase interpolated signals SPIEach pulse step reduce control
Signal SCSignal level.For example, signal S is controlledCSignal level can be in phase interpolated signals SPIPeriod tPI' in from
Peak signal level VHReduce a unit signal level VU, then in phase interpolated signals SPITo reduce by one again single next period
Position signal level VU, until controlling signal SCSignal level be down to reference signal level VL.Accordingly, signal S is controlledCSignal
Level i.e. can be during the pulse of phase lagging signal UP from peak signal level VHIt is reduced to reference signal level VL, use
Constitute control signal SCFailing edge FE in waveform.
In the present embodiment, the signal level size of each step is (that is, unit signal level VUSize) it is according to phase
Interpolated signal SPIThe number of pulses during pulse of phase-lead signal DN/ phase lagging signal UP is determined.Due to this
Embodiment assumes that second frequency F2 is 16 times of first frequency F1, therefore in phase-lead signal DN/ phase lagging signal UP
Pulse during, phase interpolated signals SPIThere can be 16 pulses, so that unit signal level VUSize can use
(VH-VL)/16 calculate.
Referring to Fig. 1 and Fig. 2 B, the running of finite state machine 130 depicted in Fig. 2 B is substantially implemented with earlier figures 2A
Example is similar.Main difference between the two is that the present embodiment assumes that second frequency F2 is 8 times of first frequency F1 (that is, divisor N
Equal to 8) when can have the optimal linearity.
To control signal SCOverall waveform from the point of view of, rising edge RE and failing edge FE are respectively formed in phase-lead signal DN
Pulse during t3 and phase lagging signal UP pulse during t4.It follows that even if input data signal DINFrequency become
It is twice of previous embodiment, finite state machine 130 still can produce corresponding control signal SC, so that phase interpolator 120 into
Row interpolative operation.Also that is, working as input data signal DINFrequency shift when, designer only needs the controllable frequency eliminator 140 of divisor
Divisor N is adjusted to the working frequency demand for meeting phase detectors 110, without adjustment phase place interpolater 120 again
Working frequency.
Fig. 3 is the clock pulse of one embodiment of the invention and the step flow chart of data reconstruction method.Referring to figure 3., in step
In S310, phase detectors 110 receive input data signal DIN, and phase interpolator 120 receives the first clock signal SIWith
Second clock signal SQ.In the present embodiment, phase detectors 110 are work in first frequency F1, and phase interpolator 120
It is work in second frequency F2.
In step s 320, device 120 is pitched in phase according to control signal SCTo the first clock signal SIWith the second clock signal
SQInterpolative operation is carried out, uses and generates phase interpolated signals SPI.In phase interpolated signals SPIAfter generation, in step S330, remove
The controllable frequency eliminator 140 of number can be based on divisor N to the phase interpolated signals S with second frequency F2PIFrequency elimination is carried out, generation tool is used
There is the frequency elimination signal S of first frequency F1PI'.In the present embodiment, divisor N is the ratio according to first frequency F1 and second frequency F2
It is worth and sets.
In step S340, phase detectors 110 can compare input data signal DINWith frequency elimination signal SPI', use generation
To indicate input data signal DINWith frequency elimination signal SPI' between phase difference phase indication signal SIND.Accordingly, in step
In S350, finite state machine 130 can be based on the phase indication signal S with first frequency F1INDWith all have second frequency F2's
Phase interpolated signals SPIIt generates and adjusts control signal SC.In step S360, deserializer 160 can be based on the clock pulse after recovery
By input data signal DINBe converted to parallel data signal DOUT, and by parallel data signal DOUTIt is transferred to back-end circuit.
In addition to this, in one skilled in the art can based on earlier figures 1 to Fig. 2 B embodiment, and obtain about
Clock pulse described in Fig. 3 and the sufficient of data reconstruction method are taught, therefore it is no longer repeated in this.
In conclusion the embodiment of the present invention proposes a kind of clock pulse and data recovery circuit and clock pulse and data reconstruction method.
By applying the framework of the controllable frequency eliminator of divisor in clock pulse and data recovery circuit, designer can be not required to additionally consider it is defeated
Under the premise of the frequency for entering data-signal, the working frequency of phase interpolator is designed in the frequency with the highest linearity.
Characteristic due to the linearity of clock pulse and data recovery circuit mainly by phase interpolator is influenced, thus the embodiment of the present invention when
Arteries and veins and data recovery circuit can realize the characteristic of wider operational frequency range under the premise of being not required to sacrifice linearity characteristic.
Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present invention., rather than its limitations；To the greatest extent
Pipe present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that: its according to
So be possible to modify the technical solutions described in the foregoing embodiments, or to some or all of the technical features into
Row equivalent replacement；And these are modified or replaceed, various embodiments of the present invention technology that it does not separate the essence of the corresponding technical solution
The range of scheme.
Claims (15)
1. a kind of clock pulse and data recovery circuit characterized by comprising
Phase detectors compare input data signal and frequency elimination signal, and generate phase indication signal to indicate the input
Phase difference between data-signal and the frequency elimination signal, wherein phase detectors work is in first frequency；
Phase interpolator receives the first clock signal, the second clock signal and control signal and according to the control signal
Phase interpolation is carried out with second clock signal to described first, generation phase interpolated signals are used, wherein in the phase
Device work is inserted in second frequency, and the second frequency is greater than the first frequency；
Finite state machine couples the phase detectors and the phase interpolator, receive the phase indication signal with it is described
Phase interpolated signals, to generate the control signal, wherein pulse period of the finite state machine in the phase indication signal
In, with each pulse of the phase interpolated signals, the signal level of the control signal is adjusted to step, and described
Every Walk rank size of signal level is determined according to number of pulses of the phase interpolated signals during pulse；
And
The controllable frequency eliminator of divisor, couples the phase detectors and the phase interpolator, and the controllable frequency eliminator of divisor is based on
Divisor carries out frequency elimination to the phase interpolated signals with the second frequency, uses the institute for generating and having the first frequency
Frequency elimination signal is stated, wherein the divisor is the ratio according to the first frequency with the second frequency and sets.
2. clock pulse according to claim 1 and data recovery circuit, which is characterized in that the work frequency of the phase interpolator
Rate is not changed with the change of the first frequency of the input data signal.
3. clock pulse according to claim 2 and data recovery circuit, which is characterized in that when the institute of the input data signal
When stating first frequency change, ratio of the divisor according to the first frequency and the unchanged second frequency after changing
And it adjusts.
4. clock pulse according to claim 1 and data recovery circuit, which is characterized in that when the phase indication signal is phase
When the leading edge signal of position, the finite state machine is during the pulse of the phase-lead signal, in the phase
Improve the signal level of the control signal with inserting each pulse step of signal.
5. clock pulse according to claim 4 and data recovery circuit, which is characterized in that the signal level of the control signal
It is promoted to peak signal level from reference signal level during the pulse, uses the rising for constituting the control signal
Edge.
6. clock pulse according to claim 1 and data recovery circuit, which is characterized in that when the phase indication signal is phase
When the lagging signal of position, the finite state machine is during the pulse of the phase lagging signal, in the phase
Reduce the signal level of the control signal with inserting each pulse step of signal.
7. clock pulse according to claim 6 and data recovery circuit, which is characterized in that the signal level of the control signal
Reference signal level is dropped to from peak signal level during the pulse, uses the decline for constituting the control signal
Edge.
8. clock pulse according to claim 1 and data recovery circuit, which is characterized in that further include:
Phase-locked loop couples the phase interpolator, believes wherein the phase-locked loop generates described first with second clock pulse
Number.
9. clock pulse according to claim 1 and data recovery circuit, which is characterized in that further include:
Deserializer couples the phase detectors, wherein the deserializer is according to the frequency elimination signal by the input number
It is believed that number being converted to parallel data signal.
10. a kind of clock pulse and data reconstruction method characterized by comprising
When receiving input data signal by phase detectors, and receiving the first clock signal and second by phase interpolator
Arteries and veins signal, wherein the phase detectors work in first frequency, and phase interpolator work is in second frequency；
Phase interpolation is carried out with second clock signal to described first according to control signal, uses and generates phase interpolation letter
Number；
Frequency elimination is carried out to the phase interpolated signals with the second frequency based on divisor, using generation has described first
The frequency elimination signal of frequency, wherein the divisor is the ratio according to the first frequency with the second frequency and sets；
Compare the input data signal and the frequency elimination signal, uses and generate phase indication signal to indicate the input data
Phase difference between signal and the frequency elimination signal；
Believed based on the phase indication signal with the first frequency with the phase interpolation with the second frequency
It number generates and adjusts the control signal, wherein during the pulse of the phase indication signal, with the phase interpolation
Each terrace pulse , Walk of signal adjusts the signal level of the control signal, and each step of the signal level is big
Small determined according to number of pulses of the phase interpolated signals during pulse；And
The input data signal is converted into parallel data signal.
11. clock pulse according to claim 10 and data reconstruction method, which is characterized in that further include:
When the input data signal the first frequency change when, according to change after the first frequency with it is unchanged
The ratio of the second frequency adjusts the divisor.
12. clock pulse according to claim 10 and data reconstruction method, which is characterized in that based on the first frequency
The phase indication signal generate with the phase interpolated signals of the second frequency and adjust the control signal
The step of include:
When the phase indication signal is phase-lead signal, during the pulse of the phase-lead signal, with
Each pulse step of the phase interpolated signals improve it is described control signal the signal level.
13. clock pulse according to claim 12 and data reconstruction method, which is characterized in that the signal of the control signal is quasi-
Position is promoted to peak signal level from reference signal level during the pulse, uses the rising for constituting the control signal
Edge.
14. clock pulse according to claim 10 and data reconstruction method, which is characterized in that based on the first frequency
The phase indication signal generate with the phase interpolated signals of the second frequency and adjust the control signal
The step of include:
When the phase indication signal is phase lagging signal, during the pulse of the phase lagging signal, with
Each pulse step of the phase interpolated signals reduce it is described control signal the signal level.
15. clock pulse according to claim 14 and data reconstruction method, which is characterized in that the signal of the control signal is quasi-
Position drops to reference signal level from peak signal level during the pulse, uses the decline for constituting the control signal
Edge.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510558974.6A CN106505997B (en) | 2015-09-06 | 2015-09-06 | Clock and data recovery circuit and clock and data recovery method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510558974.6A CN106505997B (en) | 2015-09-06 | 2015-09-06 | Clock and data recovery circuit and clock and data recovery method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106505997A CN106505997A (en) | 2017-03-15 |
| CN106505997B true CN106505997B (en) | 2019-05-21 |
Family
ID=58286463
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510558974.6A Active CN106505997B (en) | 2015-09-06 | 2015-09-06 | Clock and data recovery circuit and clock and data recovery method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106505997B (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10224978B1 (en) * | 2017-08-16 | 2019-03-05 | Taiwan Semiconductor Manufacturing Co., Ltd. | Clock and data recovery circuit |
| US10924125B2 (en) * | 2018-10-23 | 2021-02-16 | Taiwan Semiconductor Manufacturing Company Ltd. | Frequency divider circuit, method and compensation circuit for frequency divider circuit |
| CN112260685B (en) * | 2019-07-22 | 2023-08-11 | 创意电子股份有限公司 | Clock data recovery device and method |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7366267B1 (en) * | 2001-03-07 | 2008-04-29 | Altera Corporation | Clock data recovery with double edge clocking based phase detector and serializer/deserializer |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100633774B1 (en) * | 2005-08-24 | 2006-10-16 | 삼성전자주식회사 | Clock recovery circuit with wide phase margin |
| US9503252B2 (en) * | 2013-03-14 | 2016-11-22 | Taiwan Semiconductor Manufacturing Co., Ltd. | Phase interpolator with linear phase change |
-
2015
- 2015-09-06 CN CN201510558974.6A patent/CN106505997B/en active Active
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7366267B1 (en) * | 2001-03-07 | 2008-04-29 | Altera Corporation | Clock data recovery with double edge clocking based phase detector and serializer/deserializer |
Non-Patent Citations (2)
| Title |
|---|
| A Multichannel Serial Link Receiver With Dual-Loop Clock-and-Data Recovery and Channel Equalization;Nader Kalantari, James F. Buckwalter;《IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS-I: REGULAR PAPERS》;20131130;正文第IV小节，图11 * |
| Nader Kalantari, James F. Buckwalter.A Multichannel Serial Link Receiver With Dual-Loop Clock-and-Data Recovery and Channel Equalization.《IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS-I: REGULAR PAPERS》.2013, * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN106505997A (en) | 2017-03-15 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9520883B2 (en) | Frequency detection circuit and reception circuit | |
| US8634509B2 (en) | Synchronized clock phase interpolator | |
| JP4756954B2 (en) | Clock and data recovery circuit | |
| US8170168B2 (en) | Clock data recovery circuit | |
| CN105577142A (en) | Clock duty cycle adjusting device and method | |
| CN106505997B (en) | Clock and data recovery circuit and clock and data recovery method | |
| JP2012109931A (en) | Oversampling circuit and serial communication apparatus and serial communication method using the same | |
| JP6596234B2 (en) | Oscillator circuit, voltage controlled oscillator, serial data receiver | |
| EP2804322A1 (en) | Systems and methods for tracking a received data signal in a clock and data recovery circuit | |
| CN102710257A (en) | Frequency locking method, voltage-controlled oscillator and frequency generating unit | |
| KR101858471B1 (en) | Delay lock loop | |
| KR102476654B1 (en) | Clock generating circuit and semiconductor apparatus including the same | |
| US9059837B1 (en) | Clock data recovery circuit and clock data recovery method | |
| CN110855288B (en) | Clock circuit and clock signal generation method | |
| KR100531457B1 (en) | Delay Locked Loop For Generating Multi-Phase Clocks Without Voltage-Controlled Oscillator | |
| JP5433432B2 (en) | Phase frequency comparator and serial transmission device | |
| US9461811B1 (en) | Clock and data recovery circuit and clock and data recovery method | |
| EP2804321A1 (en) | Systems and methods for acquiring a received data signal in a clock and data recovery circuit | |
| TW201707383A (en) | Clock and data recovery circuit and clock and data recovery method | |
| JP2006101268A (en) | Clock and data recovery circuit | |
| US8774325B2 (en) | Clock and data recovery circuits | |
| CN105811967A (en) | Circuit for generating fractional frequency-division clock based on HDMI standard | |
| KR101700745B1 (en) | Clock multiplier and clock/data recovery circuit comprising the same | |
| KR20120135706A (en) | Delay-locked loop for decreasing the noise of input phase | |
| KR101298416B1 (en) | Clock data recovery circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |