CN110855288B

CN110855288B - Clock circuit and clock signal generation method

Info

Publication number: CN110855288B
Application number: CN201911182851.1A
Authority: CN
Inventors: 贾雪绒
Original assignee: Xian Unilc Semiconductors Co Ltd
Current assignee: Xian Unilc Semiconductors Co Ltd
Priority date: 2019-11-27
Filing date: 2019-11-27
Publication date: 2023-09-19
Anticipated expiration: 2039-11-27
Also published as: CN110855288A

Abstract

The invention discloses a clock circuit, comprising: a first lc phase-locked loop and a first annular phase-locked loop; the first inductance-capacitance type phase-locked loop is used for performing frequency multiplication processing on a first input clock signal to generate a first high-frequency clock signal; the first annular phase-locked loop is used for performing frequency multiplication processing on the first high-frequency clock signal to generate a first target clock signal. The invention solves the technical problem that the clock signal with high speed, wide frequency and low jitter can not be provided in the prior art.

Description

Clock circuit and clock signal generation method

Technical Field

The present invention relates to the field of clock generating circuits, and in particular, to a clock circuit and a clock signal generating method.

Background

Compared with the traditional DDR3/4/LPDDR4 physical interface PHY, the GDDR6 physical interface PHY of the graphic dynamic random access memory needs to provide a data transmission rate of up to 16Gbps, and the system level puts more strict requirements on the clock generating circuit, and needs a high-speed high-performance low-jitter clock generating circuit, which specifically comprises the following requirements:

1. it is desirable to provide a high-speed clock signal, up to 8GHz.

2. It is desirable to provide a low jitter clock signal to meet that the overall system is controlled to within 0.2 unit time intervals UI.

3. It is desirable to provide a clock signal that can cover a relatively wide frequency range, supporting frequencies in the range of 5 GH-8 GHz (especially 5/6/6.5/7/8 GHz).

However, the clock signal provided by the clock circuit in the prior art cannot simultaneously have three performances of high speed, wide frequency and low jitter, and cannot meet the requirements of the GDDR6 physical interface PHY on the clock generation circuit.

Disclosure of Invention

The embodiment of the application solves the technical problem that the clock signal with high speed, wide frequency and low jitter cannot be provided in the prior art by providing the clock circuit and the clock signal generation method.

In a first aspect, the present application provides, according to an embodiment of the present application, the following technical solutions:

a clock circuit, comprising: a first lc phase-locked loop and a first annular phase-locked loop; the first inductance-capacitance type phase-locked loop is used for performing frequency multiplication processing on a first input clock signal to generate a first high-frequency clock signal; the first annular phase-locked loop is used for performing frequency multiplication processing on the first high-frequency clock signal to generate a first target clock signal.

In one embodiment, the frequency of the first target clock signal is determined according to fout=fin×n/M, where Fout is the frequency of the first target clock signal, fin is the frequency of the first high-frequency clock signal, M and N are frequency configuration coefficients of the first annular phase-locked loop, N has a value of 1 to 16, and M has a value of 1 to 2.

In one embodiment, the bandwidth of the first annular phase locked loop is set to one twentieth of the frequency of the first high frequency clock signal to one tenth of the frequency of the first high frequency clock signal.

In one embodiment, the first input clock signal is provided by an external crystal oscillator.

In one embodiment, the first lc phase locked loop includes: the first phase frequency discriminator is used for detecting the frequency difference and the phase difference between the first input clock signal and the first internal feedback signal and generating a first control signal according to the frequency difference and the phase difference between the first input clock signal and the first internal feedback signal; the first charge pump is used for amplifying the first control signal and outputting a first amplified signal; the first loop filter is used for carrying out low-pass filtering processing on the first amplified signal and outputting a first filtering signal; a first inductance-capacitance type voltage-controlled oscillator for outputting the first high-frequency clock signal according to the first filtering signal; and the first feedback frequency divider is used for carrying out frequency division processing on the first high-frequency clock signal to obtain the first internal feedback signal.

In one embodiment, the first annular phase-locked loop comprises: the first automatic frequency calibration module is used for detecting the frequency difference between the first high-frequency clock signal and the second internal feedback signal and generating a second control signal according to the frequency difference between the first high-frequency clock signal and the second internal feedback signal; a second phase frequency detector for detecting a frequency difference and a phase difference between the first high frequency clock signal and the second internal feedback signal, and generating a third control signal according to the frequency difference and the phase difference between the first high frequency clock signal and the second internal feedback signal; the second charge pump is used for amplifying the third control signal and outputting a second amplified signal; the first voltage control switch is used for collecting the second amplified signal and outputting a corresponding first voltage pulse signal; the second loop filter is used for carrying out low-pass filtering processing on the first voltage pulse signal to obtain a second filtering signal; the first annular voltage-controlled oscillator is used for outputting the first target clock signal according to the second filtering signal and the second control signal; and the second feedback frequency divider is used for carrying out frequency division processing on the first target clock signal and outputting the second internal feedback signal.

In a second aspect, the present application provides, according to an embodiment of the present application, the following technical solutions:

a clock circuit, comprising: the second inductance-capacitance phase-locked loop, the frequency divider and the second annular phase-locked loop; the second inductance-capacitance phase-locked loop is used for performing frequency multiplication processing on a second input clock signal to generate a second high-frequency clock signal; the frequency divider is used for performing frequency division processing on the second high-frequency clock signal to generate a third high-frequency clock signal; the second annular phase-locked loop is used for performing frequency multiplication processing on the third high-frequency clock signal to generate a second target clock signal.

In one embodiment, the number of the second annular phase-locked loops is more than two, and the more than two second annular phase-locked loops have different frequency configuration coefficients, and the frequency configuration coefficients are used for configuring the frequency of the second target clock signal; the input end of each second annular phase-locked loop is connected with the output end of the frequency divider.

In one embodiment, the number of the frequency dividers is more than two, and more than two frequency dividers have different frequency division coefficients; the input end of each frequency divider is connected with the output end of the second inductance-capacitance phase-locked loop, and the output end of each frequency divider is connected with the input end of the second annular phase-locked loop.

In one embodiment, the number of the second annular phase-locked loops is more than two, and the more than two second annular phase-locked loops are in one-to-one correspondence with the more than two frequency dividers, wherein the more than two second annular phase-locked loops have the same frequency configuration coefficient, and the frequency configuration coefficient is used for configuring the frequency of the second target clock signal.

In one embodiment, the number of the second annular phase-locked loops is more than two, and the more than two second annular phase-locked loops are in one-to-one correspondence with the more than two frequency dividers, wherein the more than two second annular phase-locked loops have different frequency configuration coefficients, and the frequency configuration coefficients are used for configuring the frequency of the second target clock signal.

In one embodiment, the frequency of the second target clock signal is determined according to fout=fin×n/M, where Fout is the frequency of the second target clock signal, fin is the frequency of the third high-frequency clock signal, M and N are frequency configuration coefficients of the first annular phase-locked loop, N has a value of 1 to 16, and M has a value of 1 to 2.

In one embodiment, the bandwidth of the second annular phase locked loop is set to one twentieth of the frequency of the third high frequency clock signal to one tenth of the frequency of the third high frequency clock signal.

In one embodiment, the second input clock signal is provided by an external crystal oscillator.

In one embodiment, the second lc phase locked loop includes: a third phase frequency detector for detecting a frequency difference and a phase difference between the second input clock signal and a third internal feedback signal, and generating a fourth control signal according to the frequency difference and the phase difference between the second input clock signal and the third internal feedback signal; the third charge pump is used for amplifying the fourth control signal and outputting a third amplified signal; the third loop filter is used for carrying out low-pass filtering processing on the third amplified signal and outputting a third filtering signal; the second inductance-capacitance type voltage-controlled oscillator is used for outputting the second high-frequency clock signal according to the third filtering signal; and the third feedback frequency divider is used for carrying out frequency division processing on the second high-frequency clock signal to obtain the third internal feedback signal.

In one embodiment, the second annular phase locked loop includes: the second automatic frequency calibration module is used for detecting the frequency difference between the third high-frequency clock signal and the fourth internal feedback signal and generating a fifth control signal according to the frequency difference between the third high-frequency clock signal and the fourth internal feedback signal; a fourth phase frequency detector for detecting a frequency difference and a phase difference between the third high frequency clock signal and the fourth internal feedback signal, and generating a sixth control signal according to the frequency difference and the phase difference between the third high frequency clock signal and the second internal feedback signal; a fourth charge pump for amplifying the sixth control signal and outputting a fourth amplified signal; the second voltage control switch is used for collecting the fourth amplified signal and outputting a corresponding second voltage pulse signal; the fourth loop filter is used for carrying out low-pass filtering processing on the second voltage pulse signal to obtain a fourth filtering signal; a second ring voltage controlled oscillator for outputting the second target clock signal according to the fifth control signal and the fourth filtered signal; and the fourth feedback frequency divider is used for carrying out frequency division processing on the second target clock signal and outputting the fourth internal feedback signal.

In a third aspect, the present application provides, according to an embodiment of the present application, the following technical solutions:

a clock signal generation method, comprising: receiving a first input clock signal by a first inductance-capacitance type phase-locked loop, and performing frequency multiplication processing on the first input clock signal to generate a first high-frequency clock signal; and performing frequency multiplication processing on the first high-frequency clock signal by a first annular phase-locked loop to generate a first target clock signal.

In one embodiment, the receiving, by the first lc phase-locked loop, the first input clock signal, and performing frequency multiplication processing on the first input clock signal, to generate a first high-frequency clock signal, includes: receiving and detecting a frequency difference and a phase difference between the first input clock signal and a first internal feedback signal by a first phase frequency discriminator, and generating a first control signal according to the frequency difference and the phase difference between the first input clock signal and the first internal feedback signal; amplifying the first control signal by a first charge pump, and outputting a first amplified signal; the first loop filter carries out low-pass filtering processing on the first amplified signal and outputs a first filtering signal; outputting the first high-frequency clock signal by a first inductance-capacitance type voltage-controlled oscillator according to the first filtering signal; and the first feedback frequency divider carries out frequency division processing on the first high-frequency clock signal to obtain the first internal feedback signal.

In one embodiment, the multiplying the first high frequency clock signal by a first annular phase-locked loop to generate a first target clock signal includes: detecting, by a first automatic frequency calibration module, a frequency difference between the first high frequency clock signal and a second internal feedback signal, and generating a second control signal based on the frequency difference between the first high frequency clock signal and the second internal feedback signal; detecting, by a second phase frequency detector, a frequency difference and a phase difference between the first high frequency clock signal and the second internal feedback signal, and generating a third control signal based on the frequency difference and the phase difference between the first high frequency clock signal and the second internal feedback signal; amplifying the third control signal by a second charge pump, and outputting a second amplified signal; the second amplified signal is acquired by a first voltage control switch, and a corresponding first voltage pulse signal is output; the second loop filter performs low-pass filtering processing on the first voltage pulse signal to obtain a second filtering signal; outputting, by a first ring voltage controlled oscillator, the first target clock signal in accordance with the second filtered signal and the second control signal; and the second feedback frequency divider performs frequency division processing on the first target clock signal and outputs the second internal feedback signal.

In a fourth aspect, the present application provides, according to an embodiment of the present application, the following technical solutions:

a method of generating a clock signal, comprising: receiving a second input clock signal by a second inductance-capacitance type phase-locked loop, and performing frequency multiplication processing on the second input clock signal to generate a second high-frequency clock signal; the frequency divider carries out frequency division processing on the second high-frequency clock signal to generate a third high-frequency clock signal; and performing frequency multiplication processing on the third high-frequency clock signal by a second annular phase-locked loop to generate a second target clock signal.

In one embodiment, the receiving, by the second lc phase-locked loop, the second input clock signal, and performing frequency multiplication processing on the second input clock signal, to generate a second high-frequency clock signal, includes: receiving and detecting a frequency difference and a phase difference between the second input clock signal and a third internal feedback signal by a third phase frequency detector, and generating a fourth control signal according to the frequency difference and the phase difference between the second input clock signal and the third internal feedback signal; amplifying the fourth control signal by a third charge pump, and outputting a third amplified signal; the third loop filter carries out low-pass filtering processing on the third amplified signal and outputs a third filtering signal; outputting the second high-frequency clock signal by a second inductance-capacitance type voltage-controlled oscillator according to the third filtering signal; and the third feedback frequency divider performs frequency division processing on the second high-frequency clock signal to obtain the third internal feedback signal.

In one embodiment, the multiplying the third high frequency clock signal by a second loop phase-locked loop to generate a second target clock signal includes: detecting, by a second automatic frequency calibration module, a frequency difference between the third high frequency clock signal and a fourth internal feedback signal, and generating a fifth control signal based on the frequency difference between the third high frequency clock signal and the fourth internal feedback signal; detecting, by a fourth phase frequency detector, a frequency difference and a phase difference between the third high frequency clock signal and the fourth internal feedback signal, and generating a sixth control signal based on the frequency difference and the phase difference between the third high frequency clock signal and the second internal feedback signal; amplifying the sixth control signal by a fourth charge pump and outputting a fourth amplified signal; the second voltage control switch collects the fourth amplified signal and outputs a corresponding second voltage pulse signal; the second voltage pulse signal is subjected to low-pass filtering processing by a fourth loop filter, so that a fourth filtering signal is obtained; outputting, by a second ring voltage controlled oscillator, the second target clock signal in accordance with the fifth control signal and the fourth filtered signal; and the fourth feedback frequency divider performs frequency division processing on the second target clock signal and outputs the fourth internal feedback signal.

One or more technical solutions provided in the embodiments of the present application at least have the following technical effects or advantages:

in the scheme, an inductance-capacitance type phase-locked loop is utilized to generate a clock signal with low jitter and high frequency, the high frequency signal is used as an input signal of the annular phase-locked loop, and the output of the clock signal with high speed, wide frequency and low jitter is completed through the configuration of the frequency configuration coefficient of the annular phase-locked loop. The overall bandwidth of the annular phase-locked loop is greatly improved due to the high frequency of the input signal, so that phase noise generated by the loop itself is suppressed. The input clock signal of the annular phase-locked loop has better phase noise while the phase noise generated by the loop is restrained, so that the jitter performance of the final output target clock signal is optimized in the whole clock circuit. In addition, since the loop phase locked loop supports the configuration of frequency configuration coefficients, a clock signal of a wider frequency is supported. Compared with the technical problem that the prior art cannot provide a clock signal with high speed, wide frequency and low jitter, the clock circuit of the scheme can ensure that the jitter of the output clock signal is greatly reduced while ensuring the high frequency and the wide frequency.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for the description of the embodiments will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a block diagram of a clock circuit according to a preferred embodiment of the present application;

fig. 2 is a circuit configuration diagram of the first lc phase-locked loop in fig. 1;

fig. 3 is a circuit configuration diagram of the first loop phase-locked loop of fig. 1;

FIG. 4 is a block diagram of a clock circuit according to another embodiment of the present application;

FIG. 5 is a block diagram of a clock circuit according to another embodiment of the present application;

FIG. 6 is a block diagram of a clock circuit according to another embodiment of the present application;

FIG. 7 is a block diagram of a clock circuit according to another embodiment of the present application;

fig. 8 is a circuit configuration diagram of the second lc phase-locked loop of fig. 4;

fig. 9 is a circuit configuration diagram of the second loop phase-locked loop of fig. 4;

FIG. 10 is a phase noise characteristic diagram of a separate annular phase locked loop according to a preferred embodiment of the present application;

FIG. 11 is a diagram showing phase noise characteristics of a clock circuit according to a preferred embodiment of the present application;

FIG. 12 is a flowchart of a clock signal generation method according to a preferred embodiment of the present application;

fig. 13 is a flowchart of another clock signal generating method according to the preferred embodiment of the present application.

Detailed Description

The technical scheme of the embodiment of the application aims to solve the technical problems, and the overall thought is as follows:

The technical scheme provided by the embodiment of the application at least has the following technical effects or advantages:

in the scheme, the first inductance-capacitance type phase-locked loop is utilized to generate a clock signal with low jitter and high frequency, the high frequency signal is used as an input signal of the first annular phase-locked loop, and the output of the clock signal with high speed, wide frequency and low jitter is completed through the configuration of the frequency configuration coefficient of the first annular phase-locked loop.

The overall bandwidth of the first annular phase-locked loop is greatly increased due to the high frequency of the input signal, thereby suppressing phase noise generated by the loop itself. The phase noise generated by the loop is restrained, and the input clock signal of the first annular phase-locked loop has better phase noise, so that the whole clock circuit integrally optimizes the jitter performance of the finally output first target clock signal.

In addition, since the first annular phase-locked loop supports the configuration of the frequency configuration coefficients, a clock signal of a wider frequency is supported. Compared with the technical problem that the prior art cannot provide a clock signal with high speed, wide frequency and low jitter, the clock circuit of the scheme can ensure that the jitter of the output clock signal is greatly reduced while ensuring the high frequency and the wide frequency.

In order to better understand the above technical solutions, the following detailed description will refer to the accompanying drawings and specific embodiments.

Example 1

As shown in fig. 1, the present embodiment provides a clock circuit including:

a first LC-PLL (LC-PLL, inductor Capacitor-Phase Locked Loop) and a first annular PLL 2 (Ring-PLL, ring-Phase Locked Loop) cascaded in this order;

The first inductance-capacitance type phase-locked loop 1 is used for performing frequency multiplication processing on a first input clock signal to generate a first high-frequency clock signal;

the first annular phase-locked loop 2 performs frequency multiplication processing on the first high-frequency clock signal based on a frequency configuration coefficient to generate a first target clock signal, where the frequency configuration coefficient is used to configure the frequency of the first target clock signal.

It should be noted that the first high-frequency clock signal provided by the first lc phase-locked loop 1 is a high-frequency clock signal, and the high-frequency clock signal has the advantages of high frequency and low jitter (i.e., good phase noise characteristics). The bandwidth of the first loop-shaped phase-locked loop 2 is adjusted based on the frequency of the first high-frequency clock signal outputted from the first lc-type phase-locked loop 1, and the higher the bandwidth of the first loop-shaped phase-locked loop 2, the higher the frequency of the input clock signal that can be locked, in other words, the higher the frequency of the input clock signal, the higher the bandwidth of the first loop-shaped phase-locked loop 2 needs to be set. As for the specific value of the frequency of the first high-frequency clock signal, it is necessary to adjust the performance requirement of the clock signal finally output by the clock circuit. In general, in the whole clock circuit, the higher the frequency of the first high-frequency clock signal provided by the first lc phase-locked loop 1, the wider the bandwidth that needs to be configured for the first pll 2, the wider the bandwidth of the first pll 2, the stronger the phase noise suppression capability for the voltage-controlled oscillator inside the first pll 2, and in the case that the input clock signal of the first pll 2 (i.e., the first high-frequency clock signal output by the first lc phase-locked loop 1) has low jitter, the lower the jitter of the clock signal output by the whole clock circuit. The adjustable bandwidth of the first loop phase-locked loop 2 is limited and cannot grow all the time, and therefore the first high frequency clock signal provided by the first lc phase-locked loop 1 cannot grow without an upper limit.

As an optional embodiment, the frequency of the first target clock signal is determined according to fout=fin, where Fout is the frequency of the first target clock signal, fin is the frequency of the first high-frequency clock signal, M and N are frequency configuration coefficients of the first annular phase-locked loop, N has a value of 1 to 16, and M has a value of 1 to 2.

As an alternative embodiment, the bandwidth of the first annular phase locked loop is one twentieth of the frequency of the first high frequency clock signal to one tenth of the frequency of the first high frequency clock signal.

As an alternative embodiment, the first input clock signal is provided by an external crystal oscillator.

In an actual implementation process, the first input clock signal may be provided by an external crystal oscillator; the frequency configuration coefficient of the first annular phase-locked loop 2 may be configured by a coefficient N and a coefficient M, specifically:

Fout＝Fin*N/M(N＝1～16，M＝1～2)，

wherein Fout is the frequency of the output clock signal of the first annular phase-locked loop 2, corresponding to the embodiment, fout is the frequency of the first target clock signal, fin is the frequency of the input clock signal of the first annular phase-locked loop 2, corresponding to the embodiment, fin is the frequency of the first high-frequency clock signal;

The frequency of the first high-frequency clock signal output by the first lc phase-locked loop 1 may be set to be above 500M, the bandwidth of the first annular phase-locked loop 2 is set to be between one tenth and one twentieth of the input frequency, corresponding to the embodiment, the frequency of the first high-frequency clock signal output by the first lc phase-locked loop 1 is set to be between one tenth and one twentieth of the frequency, and the overall performance and stability of the clock circuit loop under the bandwidth are good.

Specifically, for the requirements of the GDDR6 physical interface PHY for the clock generation circuitry: it is desirable to provide a high speed (up to 8GHz at maximum), low jitter, and relatively wide frequency coverage (5 GHz to 8 GHz) clock signal. The clock signal can provide a first high-frequency clock signal of 500MHz-1GHz to the first annular phase-locked loop 2 through the first inductance-capacitance phase-locked loop 1, and finally can realize the output of a clock signal of 5GHz-8GHz through various configurations of the frequency configuration coefficient N/M of the first annular phase-locked loop 2, for example: fout=fin N/M (n=1 to 16, m=1 to 2), for example fin=1 GHz, n=16, m=2, fout=8 GHz, can satisfy the requirement of the GDDR6 physical interface PHY for the clock signal. In the clock circuit, in order to receive the high-frequency signal of 500MHz-1GHz, the bandwidth of the first annular phase-locked loop 2 is adjusted to be a high bandwidth corresponding to the frequency of 500MHz-1GHz, namely, a bandwidth of 0.05GHz-0.1GHz, and under the high bandwidth, the phase noise of the voltage-controlled oscillator in the first annular phase-locked loop 2 is greatly inhibited, so that the final jitter of the clock circuit is further optimized.

It should be noted that, the first lc phase-locked loop 1 may implement better jitter, but the first lc phase-locked loop 1 can only support one frequency point, and for the requirement of the GDDR6 physical interface PHY on the clock generation circuit: if multiple frequency points are supported, a clock signal with a wide frequency range, low jitter and high frequency is provided, and a plurality of inductance capacitance resonance circuits (LC-tank) are generally used in the prior art to support the wide range of the multiple frequency points. This design would lead to a large increase in area, which would be detrimental to integration.

As an alternative embodiment, as shown in fig. 2, the first lc phase-locked loop 1 includes:

a first phase frequency detector 11 (PFD, phase frequency detector) for detecting a frequency difference and a phase difference between the first input clock signal and a first internal feedback signal and generating a first control signal based on the frequency difference and the phase difference between the first input clock signal and the first internal feedback signal;

a first Charge Pump 12 (CP) connected to the first phase frequency detector 11, and configured to amplify the first control signal and output a first amplified signal;

a first loop Filter 13 (LPF) coupled to the first charge pump 12 for performing a Low-pass filtering process on the first amplified signal, and outputting a first filtered signal;

A first LC-VCO (LC-VCO, inductor Capacitor Voltage-Controlled Oscillator) connected to the first loop filter 13 for outputting the first high frequency clock signal based on the first filtered signal;

and the first feedback frequency divider 15 is connected with the first inductance-capacitance type voltage-controlled oscillator 14 and is used for performing frequency division processing on the first high-frequency clock signal to obtain the first internal feedback signal.

In the real-time implementation process, by changing the inductance parameter L and the capacitance parameter C (mainly, changing the capacitance parameter C) of the first lc-type vco 14, the frequency and jitter of the output clock signal of the first lc-type pll 1 can be changed, so as to realize the output with high frequency and low jitter.

As an alternative embodiment, as shown in fig. 3, the first annular phase-locked loop 2 includes:

a first automatic frequency calibration module 27 (AFC, automatic Frequency Calibration) for detecting a frequency difference between the first high frequency clock signal and the second internal feedback signal and generating a second control signal based on the frequency difference between the first high frequency clock signal and the second internal feedback signal;

A second phase frequency detector 21 (PFD, phase frequency detector) for detecting a frequency difference and a phase difference between the first high frequency clock signal and the second internal feedback signal and generating a third control signal according to the frequency difference and the phase difference between the first high frequency clock signal and the second internal feedback signal;

a second Charge Pump 22 (CP) connected to the second phase frequency detector 21, and configured to amplify the third control signal and output a second amplified signal;

a first voltage control switch 23 connected to the second charge pump 22 and outputting a corresponding first voltage pulse signal;

a second loop Filter 24 (LPF) connected to the first voltage control switch 23, for performing a Low-pass filtering process on the first voltage pulse signal to obtain a second filtered signal;

a first Ring Voltage controlled oscillator 25 (Ring-VCO, ring Voltage-Controlled Oscillator) connected to the second loop filter 24, and the first automatic frequency calibration module 27 for outputting the first target clock signal according to the second filtered signal and the second control signal;

and a second feedback frequency divider 26, connected to the first ring voltage-controlled oscillator 25, for performing frequency division processing on the first target clock signal, and outputting the second internal feedback signal.

Specifically, the first automatic frequency calibration module 27 is connected to the first ring voltage controlled oscillator 25 through the first voltage controlled oscillator array switch 251, and when the first ring phase locked loop 2 is powered on, the second control signal is utilized to select the working frequency of the most suitable voltage controlled oscillator by controlling the first voltage controlled oscillator array switch 251, so as to ensure that the PLL finally outputs a high-performance and low-jitter target clock signal; the second charge pump 22 is connected with a first charge pump current adjusting switch 221, and the first charge pump current adjusting switch 221 adjusts the current of the second charge pump 22 through a first current control signal; the output end of the first annular voltage-controlled oscillator 25 is connected with the second feedback frequency divider 26 through a first voltage-controlled oscillator buffer 261 and a first CMOS buffer 263 in sequence, and the first voltage-controlled oscillator buffer 261 is also connected with a first virtual buffer 262; the output signal of the first ring voltage controlled oscillator 25 is processed by a first clock divider 28 to output the first target clock signal.

In the actual implementation process, the bandwidth of the annular phase-locked loop 2 can be adjusted by changing the gain coefficient of the second phase-frequency detector 21, the gain coefficient of the second charge pump 22, the resistance R/capacitance C of the second loop filter 24, the gain coefficient of the annular voltage-controlled oscillator 25, and the like.

in the scheme, the first inductance-capacitance type phase-locked loop is utilized to generate a clock signal with low jitter and high frequency, the first high-frequency clock signal is used as an input signal of the first annular phase-locked loop, and the output of the clock signal with high speed, wide frequency and low jitter is completed through the configuration of the frequency configuration coefficient of the first annular phase-locked loop. The overall bandwidth of the first annular phase-locked loop is greatly increased due to the high frequency of the input signal, thereby suppressing phase noise generated by the loop itself. The phase noise generated by the loop is restrained, and the input clock signal of the first annular phase-locked loop has better phase noise, so that the whole clock circuit integrally optimizes the jitter performance of the finally output first target clock signal. In addition, since the first annular phase-locked loop supports the configuration of the frequency configuration coefficients, a clock signal of a wider frequency is supported. Compared with the technical problem that the prior art cannot provide a clock signal with high speed, wide frequency and low jitter, the clock circuit of the scheme can ensure that the jitter of the output clock signal is greatly reduced while ensuring the high frequency and the wide frequency.

Example two

As shown in fig. 4, the present embodiment provides a clock circuit including:

the second inductance-capacitance phase-locked loop 3, the frequency divider 5 and the second annular phase-locked loop 4 are cascaded in sequence;

the second lc phase locked loop 3 is configured to perform frequency multiplication processing on a second input clock signal to generate a second high-frequency clock signal;

the frequency divider 5 is configured to perform frequency division processing on the second high-frequency clock signal, and generate a third high-frequency clock signal;

the second annular phase-locked loop 4 performs frequency multiplication processing on the third high-frequency clock signal based on a frequency configuration coefficient, and generates a second target clock signal, where the frequency configuration coefficient is used to configure the frequency of the second target clock signal.

As an alternative embodiment, the frequency of the second target clock signal is determined according to fout=fin×n/M, where Fout is the frequency of the second target clock signal, fin is the frequency of the third high frequency clock signal, M and N are frequency configuration coefficients of the first annular phase-locked loop, n=1 to 16, and m=1 to 2.

As an alternative embodiment, the bandwidth of the second annular phase locked loop is set to one twentieth of the frequency of the third high frequency clock signal to one tenth of the frequency of the third high frequency clock signal.

As an alternative embodiment, the second input clock signal is provided by an external crystal oscillator.

In practical implementation, the second input clock signal may be provided by an external crystal oscillator, and the output frequency of the second annular phase-locked loop 4 is configured by a frequency configuration coefficient N, M, specifically, fout=fin×n/M (n=1-16, m=1-2), where Fout is the frequency of the output clock signal of the second annular phase-locked loop 4, here the frequency of the second target clock signal, fin is the frequency of the input clock signal of the second annular phase-locked loop 4, here the frequency of the third high-frequency clock signal.

It should be noted that, compared to the second high-frequency clock signal, the third high-frequency clock signal divided by the frequency divider 5 may further reduce jitter of the clock signal. Jitter is present at each rising edge of the clock signal, and the clock signal at a higher frequency has more rising edges than the signal at a lower frequency, so that the frequency-divided lower frequency signal reduces jitter that would otherwise occur at each rising edge, thereby reducing jitter in the clock signal.

The second high frequency clock signal provided by the second lc phase locked loop 3 is a high frequency clock signal which has the advantage of high frequency, low jitter (i.e. good phase noise characteristics). The third high-frequency clock signal divided by the frequency divider 5 has lower jitter (i.e., good phase noise characteristics). The bandwidth of the second annular phase-locked loop 4 is adjusted based on the frequency of the third high-frequency clock signal divided by the frequency divider 5, and the higher the bandwidth of the second annular phase-locked loop 4, the higher the frequency of the input clock signal that can be locked, in other words, the higher the frequency of the input clock signal, the higher the bandwidth of the second annular phase-locked loop 4 needs to be set. As for the specific values of the frequencies of the second high-frequency clock signal and the third high-frequency clock signal, the specific values need to be adjusted according to the performance requirement of the clock signal finally output by the clock circuit, in general, in the whole clock circuit, the higher the frequency of the third high-frequency clock signal provided by the frequency divider 5, the wider the bandwidth of the second annular phase-locked loop 4 needs to be configured, the wider the bandwidth of the second annular phase-locked loop 4, the stronger the phase noise suppression capability of the voltage-controlled oscillator inside the second annular phase-locked loop 4, and in the case that the input clock signal (i.e. the third high-frequency clock signal output by the frequency divider 5) of the second annular phase-locked loop 4 has low jitter, the jitter of the clock signal output by the whole clock circuit is lower. The lower the jitter of the clock signal output by the overall clock circuit. But the adjustable bandwidth of the second annular phase locked loop 4 is limited and cannot grow all the time, and therefore the frequency of the third high frequency clock signal provided by the frequency divider 5 cannot grow without an upper limit.

In the actual implementation process, the second input clock signal can be provided by an external crystal oscillator; the output frequency of the second annular phase-locked loop 4 is configured by a frequency configuration coefficient N, M, specifically, fout=fin N/M (n=1-16, m=1-2), where Fout is the frequency of the output clock signal of the second annular phase-locked loop 4, corresponding to the embodiment, fout is the frequency of the second target clock signal, fin is the frequency of the input clock signal of the second annular phase-locked loop 4, corresponding to the embodiment, fin is the frequency of the third high-frequency clock signal; the frequency of the second high-frequency clock signal output by the second lc phase-locked loop 3 may be set to be above 4GHz, the frequency of the third high-frequency clock signal output by the frequency divider 5 may be set to be above 500MHz, the bandwidth of the second loop phase-locked loop 4 is set to be between one tenth and one twentieth of the input frequency, and the overall performance and stability of the clock circuit loop under this bandwidth are good, corresponding to the present embodiment, set to be between one tenth and one twentieth of the frequency of the third high-frequency clock signal output by the frequency divider 5.

Specifically, for the requirements of the GDDR6 physical interface PHY for the clock generation circuitry: it is desirable to provide a high speed (up to 8GHz at maximum), low jitter, and relatively wide frequency coverage (5 GHz to 8 GHz) clock signal. The clock circuit provides a second input clock signal with low frequency and low jitter through an external crystal oscillator, the second input clock signal is input into a second inductance-capacitance type phase-locked loop 3, a second high-frequency clock signal with 8GHz is provided for a frequency divider 5 through the second inductance-capacitance type phase-locked loop 3, the frequency divider 5 divides the frequency of the second high-frequency clock signal, a third high-frequency clock signal with 500MHz-1GHz is provided for a second annular phase-locked loop 4, and finally, the output of the clock signal with 5GHz-8GHz can be realized through various configurations of the frequency configuration coefficient N/M of the second annular phase-locked loop 4, for example: fout=fin N/M (n=1 to 16, m=1 to 2), for example fin=1 GHz, n=16, m=2, fout=8 GHz, can satisfy the requirement of the GDDR6 physical interface PHY for the clock signal. In the present clock circuit, in order to receive the high-frequency signal of 500MHz-1GHz, the bandwidth of the second annular phase-locked loop 4 is adjusted to a high bandwidth corresponding to the frequency of 500MHz-1GHz, that is, a bandwidth of 0.05GHz-0.1GHz (set to one tenth of the frequency of the second high-frequency clock signal), under this high bandwidth, the phase noise of the voltage-controlled oscillator VCO itself inside the second annular phase-locked loop 4 is greatly suppressed, the final jitter of the present clock circuit is further optimized, referring to fig. 10 and 11, fig. 11 are phase-noise characteristics of the second annular phase-locked loop 4 in the present clock circuit, compared with the phase-noise characteristics of the second annular phase-locked loop 4 alone in fig. 10, the phase-noise characteristics of LPF, VCO, CP in the loop in the present clock circuit are all suppressed to different extents, especially the phase-noise characteristics of the VCO of the second annular phase-locked loop 4 are suppressed, the final jitter jrms=0.86 ps, and jrms=1.34 ps of the jitter of the second annular phase-locked loop 4 alone.

As an alternative embodiment, the number of the second annular phase-locked loops 4 is more than two, and more than two second annular phase-locked loops 4 have different frequency configuration coefficients; the frequency configuration coefficient is used to configure the frequency of the second target clock signal.

An input of each second annular phase locked loop 4 is connected to an output of the frequency divider 5.

For the clock circuit with only one second annular phase-locked loop 4, only one clock signal with one frequency can be output at the same time, and in order to realize the output of a plurality of frequency points, the frequency configuration coefficient of the second annular phase-locked loop 4 needs to be adjusted at any time. While the present embodiment is configured with a plurality of second annular phase-locked loops 4 having different frequency configuration coefficients so as to output clock signals of various frequencies at the same time.

As shown in fig. 5, a block diagram of two clock circuits of the second annular phase-locked loop 4 is provided, and the connection relationship is shown in the figure, which is not described here.

As an alternative embodiment, the number of the frequency dividers 5 is more than two, and more than two frequency dividers 5 have different frequency division coefficients;

the input end of each frequency divider 5 is connected with the output end of the second inductance-capacitance phase-locked loop 3, and the output end of each frequency divider 5 is connected with the input end of the second annular phase-locked loop 4.

Compared with a clock circuit with only one frequency divider 5, the embodiment realizes the output of the third high-frequency clock signals with different frequency points by configuring a plurality of frequency dividers 5 with different frequency division coefficients, and can realize the output of the clock signals with wider frequency range after the frequency multiplication of the third high-frequency clock signals with different frequencies by the same second annular phase-locked loop 4. It should be noted that, in the present embodiment, the power control of the frequency divider 5 may be used to turn on or off the frequency divider 5 to determine whether to enable the frequency divider 5 to generate the third high frequency clock signal, or a selector may be provided after the frequency divider 5 to select the frequency divider 5 to be used.

As shown in fig. 6, a block diagram of a clock circuit with two frequency dividers 5 and one second annular phase-locked loop 4 is provided, and the connection relationship is shown in the figure, which is not described here.

As an alternative embodiment, the number of the second annular phase-locked loops 4 is more than two, and more than two second annular phase-locked loops 4 are in one-to-one correspondence with more than two frequency dividers 5; wherein two or more of the second annular phase-locked loops 4 have the same frequency configuration coefficient for configuring the frequency of the second target clock signal.

For the clock circuit with only one second annular phase-locked loop 4, only one clock signal with one frequency can be output at the same time, and in order to realize the output of a plurality of frequency points, the frequency configuration coefficient of the second annular phase-locked loop 4 needs to be adjusted at any time. In this embodiment, by configuring a plurality of frequency dividers 5 with different frequency division coefficients, the simultaneous output of the third high-frequency clock signals with different frequency points is realized, and after the third high-frequency clock signals with different frequencies are respectively multiplied by the second annular phase-locked loop 4 with the same frequency configuration coefficient, the clock signals with various frequencies can be simultaneously output.

As shown in fig. 7, a block diagram of a clock circuit with two frequency dividers 5 and two second annular phase-locked loops 4 is provided, and the connection relationship is shown in the figure, which is not described herein, and the frequency configuration coefficients for the two second annular phase-locked loops 4 in this embodiment are the same.

As an alternative embodiment, the number of the second annular phase-locked loops 4 is more than two, and more than two second annular phase-locked loops 4 are in one-to-one correspondence with more than two frequency dividers 5; wherein two or more of the second annular phase locked loops 4 have different frequency configuration coefficients for configuring the frequency of the second target clock signal.

As shown in fig. 7, a block diagram of a clock circuit with two frequency dividers 5 and two second annular phase-locked loops 4 is provided, and the connection relationship is shown in the figure, which is not described herein, and frequency configuration coefficients for the two second annular phase-locked loops 4 in this embodiment are different.

For the clock circuit with only one second annular phase-locked loop 4, only one clock signal with one frequency can be output at the same time, and in order to realize the output of a plurality of frequency points, the frequency configuration coefficient of the second annular phase-locked loop 4 needs to be adjusted at any time. In the present embodiment, by configuring a plurality of frequency dividers 5 with different frequency division coefficients, the simultaneous output of the third high-frequency clock signals with different frequency points is realized, and for the third high-frequency clock signals with different frequencies, after the third high-frequency clock signals are multiplied by the second annular phase-locked loop 4 with different frequency configuration coefficients, the simultaneous output of the clock signals with a wider frequency range can be realized compared with the previous embodiment.

As an alternative embodiment, as shown in fig. 8, the second lc phase-locked loop 3 includes:

a third phase frequency detector 31 for detecting a frequency difference and a phase difference between the second input clock signal and a third internal feedback signal, and generating a fourth control signal corresponding to the frequency difference and the phase difference between the second input clock signal and the third internal feedback signal;

A third charge pump 32, connected to the third phase frequency detector 31, for amplifying the fourth control signal and outputting a third amplified signal;

a third loop filter 33 connected to the third charge pump 32, and configured to perform low-pass filtering on the third amplified signal, and output a third filtered signal;

a second lc-type voltage-controlled oscillator 34 connected to the third loop filter 33, and configured to output the second high-frequency clock signal having a frequency corresponding to the third filtered signal according to the third filtered signal;

and a third feedback frequency divider 35 connected to the second lc vco 34, and configured to divide the second high-frequency clock signal to obtain the third internal feedback signal.

As an alternative embodiment, as shown in fig. 9, the second annular phase-locked loop 4 includes:

a second automatic frequency calibration module 47 for detecting a frequency difference between the third high frequency clock signal and a fourth internal feedback signal and generating a fifth control signal corresponding to the frequency difference between the third high frequency clock signal and the fourth internal feedback signal;

a fourth phase frequency detector 41 for detecting a frequency difference and a phase difference between the third high frequency clock signal and the fourth internal feedback signal, and generating a sixth control signal corresponding to the frequency difference and the phase difference between the third high frequency clock signal and the fourth internal feedback signal;

A fourth charge pump 42 connected to the fourth phase frequency detector 41, and configured to amplify the sixth control signal and output a fourth amplified signal;

a second voltage control switch 43 connected to the fourth charge pump 42, for collecting the fourth amplified signal and outputting a corresponding second voltage pulse signal;

a fourth loop filter 44 connected to the second voltage control switch 43, and configured to perform low-pass filtering processing on the second voltage pulse signal to obtain a fourth filtered signal;

a second ring voltage controlled oscillator 45 connected to the fourth loop filter 44 and the second automatic frequency calibration module 47 for outputting the second target clock signal according to the fourth filtered signal and the fifth control signal;

a fourth feedback frequency divider 546, coupled to the second ring voltage-controlled oscillator 45, for performing frequency division on the second target clock signal and outputting the fourth internal feedback signal.

Specifically, the second automatic frequency calibration module 47 is connected to the second ring voltage controlled oscillator 45 through the second voltage controlled oscillator array switch 451, and when the second ring phase locked loop 4 is powered on, the fifth control signal is utilized to select the working frequency of the most suitable voltage controlled oscillator by controlling the second voltage controlled oscillator array switch 451, so as to ensure that the PLL finally outputs the second target clock signal with high performance and low jitter; the fourth charge pump 42 is connected with a second charge pump current adjusting switch 421, and the second charge pump current adjusting switch 421 adjusts the current of the fourth charge pump 42 through a second current control signal; the output end of the second ring voltage controlled oscillator 45 is connected to the fourth feedback frequency divider 546 through the second voltage controlled oscillator buffer 461 and the second CMOS buffer 463 in sequence, and the second voltage controlled oscillator buffer is also connected to the second virtual buffer 462; the output signal of the second ring voltage controlled oscillator 45 passes through the second clock divider 48 and then outputs the second target clock signal.

in the scheme, a second inductance-capacitance type phase-locked loop is utilized to generate a clock signal with low jitter and high frequency, the second high-frequency clock signal is input into a frequency divider to be divided to obtain a high-frequency clock signal with relatively low jitter, the third high-frequency clock signal is used as an input signal of a second annular phase-locked loop, and the output of the clock signal with high speed, wide frequency and low jitter is completed through the configuration of the frequency configuration coefficient of the second annular phase-locked loop. The frequency divider divides the frequency of the output signal of the second inductance-capacitance phase-locked loop, so that jitter can be relatively reduced; in addition, the input signal frequency of the second annular phase-locked loop is high, the overall bandwidth of the second annular phase-locked loop is greatly improved, so that phase noise generated by the loop is restrained, and the input clock signal of the second annular phase-locked loop has better phase noise while the phase noise generated by the loop is restrained, and therefore the jitter performance of a finally output second target clock signal is integrally optimized by the whole clock circuit. In addition, since the second annular phase-locked loop supports the configuration of the frequency configuration coefficients, a clock signal of a wider frequency is supported. Compared with the technical problem that the prior art cannot provide a clock signal with high speed, wide frequency and low jitter, the clock circuit of the scheme can ensure that the jitter of the output clock signal is greatly reduced while ensuring the high frequency and the wide frequency.

Example III

As shown in fig. 12, the present embodiment provides a clock signal generating method, including:

step S101: receiving a first input clock signal by a first inductance-capacitance type phase-locked loop, and performing frequency multiplication processing on the first input clock signal to generate a first high-frequency clock signal;

step S102: the first high-frequency clock signal is subjected to frequency multiplication processing by a first annular phase-locked loop to generate a first target clock signal.

The first high-frequency clock signal generated by the first lc phase-locked loop is a high-frequency clock signal, and the high-frequency clock signal has the advantages of high frequency and low jitter (i.e., good phase noise characteristics). The bandwidth of the first loop-shaped phase-locked loop is adjusted based on the frequency of the first high-frequency clock signal output by the first inductance-capacitance phase-locked loop, and the higher the bandwidth of the first loop-shaped phase-locked loop is, the higher the frequency of the input clock signal which can be locked is, in other words, the higher the frequency of the input clock signal is, the higher the bandwidth of the first loop-shaped phase-locked loop needs to be set. As for the specific value of the frequency of the first high-frequency clock signal, it is necessary to adjust the frequency according to the performance requirement of the finally output clock signal. In general, in the clock signal generating process, the higher the frequency of the first high-frequency clock signal provided by the first inductance-capacitance type phase-locked loop, the wider the bandwidth that needs to be configured for the first annular phase-locked loop, the wider the bandwidth of the first annular phase-locked loop, the stronger the phase noise suppression capability of the voltage-controlled oscillator inside the first annular phase-locked loop, and in the case that the input clock signal of the first annular phase-locked loop (i.e., the first high-frequency clock signal output by the first inductance-capacitance type phase-locked loop 1) has low jitter, the lower the jitter of the first target clock signal finally output. However, the adjustable bandwidth of the first loop phase-locked loop is limited and cannot grow all the time, so that the first high-frequency clock signal provided by the first inductance-capacitance phase-locked loop cannot grow without an upper limit.

As an alternative embodiment, the frequency of the first target clock signal is determined according to fout=fin×n/M, where Fout is the frequency of the first target clock signal, fin is the frequency of the first high frequency clock signal, M and N are frequency configuration coefficients of the first annular phase-locked loop, N has a value of 1 to 16, and M has a value of 1 to 2.

As an alternative embodiment, the bandwidth of the first annular phase locked loop is set to one twentieth of the frequency of the first high frequency clock signal to one tenth of the frequency of the first high frequency clock signal.

In an actual implementation process, the first input clock signal may be provided by an external crystal oscillator; the frequency configuration coefficient of the first annular phase-locked loop can be configured by a coefficient N and a coefficient M, and specifically:

Fout＝Fin*N/M(N＝1～16，M＝1～2)，

wherein Fout is the frequency of the output clock signal of the first annular phase-locked loop, corresponding to the embodiment, fout is the frequency of the first target clock signal, fin is the frequency of the input clock signal of the first annular phase-locked loop, corresponding to the embodiment, fin is the frequency of the first high-frequency clock signal;

the frequency of the first high-frequency clock signal output by the first inductance-capacitance type phase-locked loop can be set to be more than 500M, the bandwidth of the first annular phase-locked loop is set to be between one tenth and one twentieth of the input frequency, corresponding to the embodiment, the bandwidth is set to be between one tenth and one twentieth of the frequency of the first high-frequency clock signal output by the first inductance-capacitance type phase-locked loop, and the overall performance and stability of the clock circuit loop under the bandwidth are good.

Specifically, for the requirements of the GDDR6 physical interface PHY on the clock signal: it is desirable to provide a high speed (up to 8GHz at maximum), low jitter, and relatively wide frequency coverage (5 GHz to 8 GHz) clock signal. The clock signal can provide a first high-frequency clock signal of 500MHz-1GHz to the first annular phase-locked loop through the first inductance-capacitance phase-locked loop, and finally can realize the output of the clock signal of 5GHz-8GHz through various configurations of the frequency configuration coefficient N/M of the first annular phase-locked loop, for example: fout=fin N/M (n=1 to 16, m=1 to 2), for example fin=1 GHz, n=16, m=2, fout=8 GHz, can satisfy the requirement of the GDDR6 physical interface PHY for the clock signal. In the scheme, in order to receive the high-frequency signal of 500MHz-1GHz, the bandwidth of the first annular phase-locked loop is adjusted to be high bandwidth corresponding to the frequency of 500MHz-1GHz, namely, the bandwidth of 0.05GHz-0.1GHz, and under the high bandwidth, the phase noise of a voltage-controlled oscillator in the first annular phase-locked loop is greatly inhibited, so that the final jitter of the clock circuit is further optimized.

As an alternative embodiment, step S101 includes:

receiving and detecting a frequency difference and a phase difference between a first input clock signal and a first internal feedback signal by a first frequency-discrimination phase detector, and generating a first control signal according to the frequency difference and the phase difference between the first input clock signal and the first internal feedback signal;

Amplifying the first control signal by a first charge pump, and outputting a first amplified signal;

the first loop filter carries out low-pass filtering processing on the first amplified signal and outputs a first filtering signal;

outputting a first high-frequency clock signal by a first inductance-capacitance type voltage-controlled oscillator according to a first filtering signal;

the first feedback frequency divider divides the frequency of the first high-frequency clock signal to obtain a first internal feedback signal.

In the real-time implementation process, the frequency and jitter of the output clock signal of the first inductance-capacitance type phase-locked loop can be changed by changing the inductance parameter L and the capacitance parameter C (mainly changing the capacitance parameter C) of the first inductance-capacitance type voltage-controlled oscillator, so that the output with high frequency and low jitter is realized.

As an alternative embodiment, step S102 includes:

detecting, by the first automatic frequency calibration module, a frequency difference between the first high frequency clock signal and the second internal feedback signal, and generating a second control signal based on the frequency difference between the first high frequency clock signal and the second internal feedback signal;

detecting a frequency difference and a phase difference between the first high frequency clock signal and the second internal feedback signal by a second phase frequency detector, and generating a third control signal according to the frequency difference and the phase difference between the first high frequency clock signal and the second internal feedback signal;

Amplifying the third control signal by a second charge pump, and outputting a second amplified signal;

the first voltage control switch collects the second amplified signal and outputs a corresponding first voltage pulse signal;

the second loop filter performs low-pass filtering processing on the first voltage pulse signal to obtain a second filtering signal;

outputting a first target clock signal by the first annular voltage-controlled oscillator according to the second filtering signal and the second control signal;

the first target clock signal is subjected to frequency division processing by a second feedback frequency divider, and a second internal feedback signal is output.

In the actual implementation process, the adjustment of the bandwidth of the annular phase-locked loop can be realized by changing the gain coefficient of the second phase frequency detector, the gain coefficient of the second charge pump, the resistor R/capacitor C of the second loop filter, the gain coefficient of the annular voltage-controlled oscillator and the like.

Example IV

As shown in fig. 13, the present embodiment provides a method for generating a clock signal, including:

step S201: receiving a second input clock signal by a second inductance-capacitance type phase-locked loop, and performing frequency multiplication processing on the second input clock signal to generate a second high-frequency clock signal;

step S202: the frequency divider carries out frequency division processing on the second high-frequency clock signal to generate a third high-frequency clock signal;

it should be noted that, compared with the second high-frequency clock signal, the jitter of the clock signal can be further reduced by the third high-frequency clock signal divided by the frequency divider. Jitter is present at each rising edge of the clock signal, and the clock signal at a higher frequency has more rising edges than the signal at a lower frequency, so that the frequency-divided lower frequency signal reduces jitter that would otherwise occur at each rising edge, thereby reducing jitter in the clock signal.

Step S203: and performing frequency multiplication processing on the third high-frequency clock signal by a second annular phase-locked loop to generate a second target clock signal.

As an alternative embodiment, the frequency of the second target clock signal is determined according to fout=fin×n/M, where Fout is the frequency of the second target clock signal, fin is the frequency of the third high frequency clock signal, M and N are frequency configuration coefficients of the first annular phase-locked loop, N has a value of 1 to 16, and M has a value of 1 to 2.

As an alternative embodiment the bandwidth of the second annular phase locked loop is arranged to be one twentieth of the frequency of the third high frequency clock signal to one tenth of the frequency of the third high frequency clock signal.

It should be noted that the second high-frequency clock signal provided by the second lc phase-locked loop is a high-frequency clock signal, and this high-frequency clock signal has the advantage of high frequency and low jitter (i.e., good phase noise characteristics). The third high-frequency clock signal divided by the frequency divider has lower jitter (i.e., good phase noise characteristics). The bandwidth of the second annular phase-locked loop is adjusted based on the frequency of the third high-frequency clock signal after the frequency divider divides, and the higher the bandwidth of the second annular phase-locked loop, the higher the frequency of the input clock signal that can be locked, in other words, the higher the frequency of the input clock signal, the higher the bandwidth of the second annular phase-locked loop needs to be set. As for the specific values of the frequencies of the second high-frequency clock signal and the third high-frequency clock signal, the specific values need to be adjusted according to the performance requirement of the finally output clock signal, in general, in the clock signal generating process, the higher the frequency of the third high-frequency clock signal provided by the frequency divider is, the wider the bandwidth of the second annular phase-locked loop needs to be configured, the wider the bandwidth of the second annular phase-locked loop is, the stronger the phase noise suppression capability of the voltage-controlled oscillator inside the second annular phase-locked loop is, and the lower the jitter of the finally output second target clock signal is under the condition that the input clock signal (namely the third high-frequency clock signal output by the frequency divider) of the second annular phase-locked loop has low jitter. However, the adjustable bandwidth of the second annular phase locked loop is limited and cannot be increased all the time, so that the frequency of the third high frequency clock signal provided by the frequency divider cannot be increased without an upper limit.

In the actual implementation process, the second input clock signal can be provided by an external crystal oscillator; the output frequency of the second annular phase-locked loop is configured by a frequency configuration coefficient N, M, specifically, fout=fin N/M (n=1-16, m=1-2), where Fout is the frequency of the output clock signal of the second annular phase-locked loop, corresponding to the embodiment, fout is the frequency of the second target clock signal, fin is the frequency of the input clock signal of the second annular phase-locked loop, corresponding to the embodiment, fin is the frequency of the third high-frequency clock signal; the frequency of the second high-frequency clock signal output by the second inductance-capacitance type phase-locked loop can be set to be more than 4GHz, the frequency of the third high-frequency clock signal output by the frequency divider can be set to be more than 500MHz, the bandwidth of the second annular phase-locked loop is set to be between one tenth and one twentieth of the input frequency, corresponding to the embodiment, the frequency of the third high-frequency clock signal output by the frequency divider is set to be between one tenth and one twentieth of the frequency, and the overall performance and stability of the clock circuit loop under the bandwidth are good.

Specifically, for the requirements of the GDDR6 physical interface PHY on the clock signal: it is desirable to provide a high speed (up to 8GHz at maximum), low jitter, and relatively wide frequency coverage (5 GHz to 8 GHz) clock signal. In this embodiment, the external crystal oscillator provides a low-frequency and low-jitter second input clock signal, the second input clock signal is input into the second inductance-capacitance phase-locked loop, the second inductance-capacitance phase-locked loop provides a second high-frequency clock signal of 8GHz to the frequency divider, the frequency divider divides the second high-frequency clock signal and provides a third high-frequency clock signal of 500MHz-1GHz to the second annular phase-locked loop, and the clock signal output of 5GHz-8GHz can be finally realized through various configurations of the frequency configuration coefficient N/M of the second annular phase-locked loop, for example: fout=fin N/M (n=1 to 16, m=1 to 2), for example fin=1 GHz, n=16, m=2, fout=8 GHz, can satisfy the requirement of the GDDR6 physical interface PHY for the clock signal. In this embodiment, in order to receive a high-frequency signal of 500MHz-1GHz, the bandwidth of the second annular phase-locked loop is adjusted to a high bandwidth corresponding to the frequency of 500MHz-1GHz, that is, a bandwidth of 0.05GHz-0.1GHz (set to one tenth of the frequency of the second high-frequency clock signal), under this high bandwidth, the phase noise of the voltage-controlled oscillator VCO itself inside the second annular phase-locked loop is greatly suppressed, the final jitter is further optimized, referring to the phase-noise characteristic curves of fig. 10 and 11, fig. 11 is the phase-noise characteristic of the second annular phase-locked loop in the present clock circuit, compared with the phase-noise characteristic of the second annular phase-locked loop alone in fig. 10, the phase-noise characteristic of LPF, VCO, CP in the loop in the present clock circuit is suppressed to a different extent, especially the phase-noise characteristic of the VCO of the second annular phase-locked loop is suppressed, the final jitter jrms=0.86 ps of the present clock circuit, and the jitter jrms=1.34 ps of the second annular phase-locked loop alone.

As an alternative embodiment, step S201 includes:

receiving and detecting a frequency difference and a phase difference between the second input clock signal and a third internal feedback signal by a third phase frequency detector, and generating a fourth control signal according to the frequency difference and the phase difference between the second input clock signal and the third internal feedback signal;

amplifying the fourth control signal by a third charge pump, and outputting a third amplified signal;

the third loop filter carries out low-pass filtering processing on the third amplified signal and outputs a third filtering signal;

outputting a second high-frequency clock signal by a second inductance-capacitance type voltage-controlled oscillator according to the third filtering signal;

and the third feedback frequency divider performs frequency division processing on the second high-frequency clock signal to obtain a third internal feedback signal.

As an alternative embodiment, step S203 includes:

detecting, by the second automatic frequency calibration module, a frequency difference between the third high frequency clock signal and the fourth internal feedback signal, and generating a fifth control signal according to the frequency difference between the third high frequency clock signal and the fourth internal feedback signal;

detecting a frequency difference and a phase difference between the third high frequency clock signal and a fourth internal feedback signal by a fourth phase frequency detector, and generating a sixth control signal according to the frequency difference and the phase difference between the third high frequency clock signal and the second internal feedback signal;

Amplifying the sixth control signal by a fourth charge pump and outputting a fourth amplified signal;

the second voltage control switch collects the fourth amplified signal and outputs a corresponding second voltage pulse signal;

the fourth loop filter performs low-pass filtering processing on the second voltage pulse signal to obtain a fourth filtering signal;

outputting a second target clock signal by a second annular voltage-controlled oscillator according to the fifth control signal and the fourth filtering signal;

the fourth feedback frequency divider performs frequency division processing on the second target clock signal and outputs a fourth internal feedback signal.

While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiments and all such alterations and modifications as fall within the scope of the invention.

It will be apparent to those skilled in the art that various modifications and variations can be made to the present invention without departing from the spirit or scope of the invention. Thus, it is intended that the present invention also include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.

Claims

1. A clock circuit, comprising:

a first lc phase-locked loop and a first annular phase-locked loop;

the first lc phase locked loop includes:

the first phase frequency discriminator is used for detecting the frequency difference and the phase difference between a first input clock signal and a first internal feedback signal and generating a first control signal according to the frequency difference and the phase difference between the first input clock signal and the first internal feedback signal;

the first charge pump is used for amplifying the first control signal and outputting a first amplified signal;

The first loop filter is used for carrying out low-pass filtering processing on the first amplified signal and outputting a first filtering signal;

the first inductance-capacitance type voltage-controlled oscillator is used for outputting a first high-frequency clock signal according to the first filtering signal;

the first feedback frequency divider is used for carrying out frequency division processing on the first high-frequency clock signal to obtain the first internal feedback signal;

the first annular phase-locked loop includes:

the first automatic frequency calibration module is used for detecting the frequency difference between the first high-frequency clock signal and the second internal feedback signal and generating a second control signal according to the frequency difference between the first high-frequency clock signal and the second internal feedback signal;

a second phase frequency detector for detecting a frequency difference and a phase difference between the first high frequency clock signal and the second internal feedback signal, and generating a third control signal according to the frequency difference and the phase difference between the first high frequency clock signal and the second internal feedback signal;

the second charge pump is used for amplifying the third control signal and outputting a second amplified signal;

the first voltage control switch is used for collecting the second amplified signal and outputting a corresponding first voltage pulse signal;

The second loop filter is used for carrying out low-pass filtering processing on the first voltage pulse signal to obtain a second filtering signal;

the first annular voltage-controlled oscillator is used for outputting a first target clock signal according to the second filtering signal and the second control signal;

the second feedback frequency divider is used for performing frequency division processing on the first target clock signal and outputting the second internal feedback signal;

the first inductance-capacitance type phase-locked loop is used for performing frequency multiplication processing on a first input clock signal to generate a first high-frequency clock signal;

the first annular phase-locked loop is used for performing frequency multiplication processing on the first high-frequency clock signal to generate a first target clock signal.

2. The clock circuit of claim 1, wherein the frequency of the first target clock signal is determined according to Fout = Fin x N/M, wherein Fout is the frequency of the first target clock signal, fin is the frequency of the first high frequency clock signal, M and N are frequency configuration coefficients of the first annular phase-locked loop, N has a value of 1 to 16, and M has a value of 1 to 2.

3. The clock circuit of claim 1, wherein a bandwidth of the first annular phase locked loop is set to one twentieth of a frequency of the first high frequency clock signal to one tenth of the frequency of the first high frequency clock signal.

4. The clock circuit of claim 1, wherein the first input clock signal is provided by an external crystal oscillator.

5. A clock circuit, comprising:

the second inductance-capacitance phase-locked loop, the frequency divider and the second annular phase-locked loop;

the second lc phase locked loop includes:

a third phase frequency detector for detecting a frequency difference and a phase difference between a second input clock signal and a third internal feedback signal, and generating a fourth control signal according to the frequency difference and the phase difference between the second input clock signal and the third internal feedback signal;

the third charge pump is used for amplifying the fourth control signal and outputting a third amplified signal;

the third loop filter is used for carrying out low-pass filtering processing on the third amplified signal and outputting a third filtering signal;

the second inductance-capacitance type voltage-controlled oscillator is used for outputting a second high-frequency clock signal according to the third filtering signal;

the third feedback frequency divider is used for carrying out frequency division processing on the second high-frequency clock signal to obtain the third internal feedback signal;

the second annular phase-locked loop includes:

the second automatic frequency calibration module is used for detecting the frequency difference between a third high-frequency clock signal and a fourth internal feedback signal and generating a fifth control signal according to the frequency difference between the third high-frequency clock signal and the fourth internal feedback signal;

A fourth phase frequency detector for detecting a frequency difference and a phase difference between the third high frequency clock signal and the fourth internal feedback signal, and generating a sixth control signal according to the frequency difference and the phase difference between the third high frequency clock signal and the fourth internal feedback signal;

a fourth charge pump for amplifying the sixth control signal and outputting a fourth amplified signal;

the second voltage control switch is used for collecting the fourth amplified signal and outputting a corresponding second voltage pulse signal;

the fourth loop filter is used for carrying out low-pass filtering processing on the second voltage pulse signal to obtain a fourth filtering signal;

the second annular voltage-controlled oscillator is used for outputting a second target clock signal according to the fifth control signal and the fourth filtering signal;

the fourth feedback frequency divider is used for performing frequency division processing on the second target clock signal and outputting a fourth internal feedback signal;

the second inductance-capacitance phase-locked loop is used for performing frequency multiplication processing on a second input clock signal to generate a second high-frequency clock signal;

the frequency divider is used for performing frequency division processing on the second high-frequency clock signal to generate a third high-frequency clock signal;

The second annular phase-locked loop is used for performing frequency multiplication processing on the third high-frequency clock signal to generate a second target clock signal.

6. The clock circuit of claim 5, wherein the number of second loop-shaped phase-locked loops is more than two, the more than two second loop-shaped phase-locked loops having different frequency configuration coefficients for configuring the frequency of the second target clock signal;

the input end of each second annular phase-locked loop is connected with the output end of the frequency divider.

7. The clock circuit of claim 5, wherein the number of frequency dividers is more than two, the more than two frequency dividers having different division coefficients;

the input end of each frequency divider is connected with the output end of the second inductance-capacitance phase-locked loop, and the output end of each frequency divider is connected with the input end of the second annular phase-locked loop.

8. The clock circuit of claim 7, wherein the number of second loop-shaped phase-locked loops is more than two, the more than two second loop-shaped phase-locked loops are in one-to-one correspondence with the more than two frequency dividers, wherein the more than two second loop-shaped phase-locked loops have the same frequency configuration coefficient for configuring the frequency of the second target clock signal.

9. The clock circuit of claim 7, wherein the number of second loop-shaped phase-locked loops is more than two, the more than two second loop-shaped phase-locked loops are in one-to-one correspondence with the more than two frequency dividers, wherein the more than two second loop-shaped phase-locked loops have different frequency configuration coefficients for configuring the frequency of the second target clock signal.

10. The clock circuit of any one of claims 5-9, wherein the frequency of the second target clock signal is determined according to Fout = Fin x N/M, wherein Fout is the frequency of the second target clock signal, fin is the frequency of the third high frequency clock signal, M and N are frequency configuration coefficients of the second annular phase locked loop, N has a value of 1-16, and M has a value of 1-2.

11. The clock circuit of claim 5, wherein a bandwidth of the second annular phase-locked loop is set to one twentieth of a frequency of the third high frequency clock signal to one tenth of the frequency of the third high frequency clock signal.

12. The clock circuit of claim 5, wherein the second input clock signal is provided by an external crystal oscillator.

13. A clock signal generation method, comprising:

receiving a first input clock signal by a first inductance-capacitance type phase-locked loop, and performing frequency multiplication processing on the first input clock signal to generate a first high-frequency clock signal;

the receiving, by the first lc pll, a first input clock signal, and performing frequency multiplication processing on the first input clock signal, to generate a first high-frequency clock signal, including:

receiving and detecting a frequency difference and a phase difference between the first input clock signal and a first internal feedback signal by a first phase frequency discriminator, and generating a first control signal according to the frequency difference and the phase difference between the first input clock signal and the first internal feedback signal;

outputting the first high-frequency clock signal by a first inductance-capacitance type voltage-controlled oscillator according to the first filtering signal;

the first feedback frequency divider carries out frequency division processing on the first high-frequency clock signal to obtain the first internal feedback signal;

Performing frequency multiplication processing on the first high-frequency clock signal by a first annular phase-locked loop to generate a first target clock signal;

the step of multiplying the first high-frequency clock signal by a first annular phase-locked loop to generate a first target clock signal includes:

detecting, by a first automatic frequency calibration module, a frequency difference between the first high frequency clock signal and a second internal feedback signal, and generating a second control signal based on the frequency difference between the first high frequency clock signal and the second internal feedback signal;

detecting, by a second phase frequency detector, a frequency difference and a phase difference between the first high frequency clock signal and the second internal feedback signal, and generating a third control signal based on the frequency difference and the phase difference between the first high frequency clock signal and the second internal feedback signal;

the second amplified signal is acquired by a first voltage control switch, and a corresponding first voltage pulse signal is output;

Outputting, by a first ring voltage controlled oscillator, the first target clock signal in accordance with the second filtered signal and the second control signal;

and the second feedback frequency divider performs frequency division processing on the first target clock signal and outputs the second internal feedback signal.

14. The method of claim 13, wherein the frequency of the first target clock signal is determined according to Fout = Fin, where Fout is the frequency of the first target clock signal, fin is the frequency of the first high-frequency clock signal, M and N are frequency configuration coefficients of the first annular phase-locked loop, N has a value of 1 to 16, and M has a value of 1 to 2.

15. The clock signal generation method of claim 13, wherein the bandwidth of the first annular phase locked loop is set to one twentieth of the frequency of the first high frequency clock signal to one tenth of the frequency of the first high frequency clock signal.

16. The method of generating a clock signal of claim 13, wherein the first input clock signal is provided by an external crystal oscillator.

17. A method of generating a clock signal, comprising:

Receiving a second input clock signal by a second inductance-capacitance type phase-locked loop, and performing frequency multiplication processing on the second input clock signal to generate a second high-frequency clock signal;

the receiving, by the second lc pll, a second input clock signal, and performing frequency multiplication processing on the second input clock signal, to generate a second high frequency clock signal, including:

outputting the second high-frequency clock signal by a second inductance-capacitance type voltage-controlled oscillator according to the third filtering signal;

the third feedback frequency divider is used for carrying out frequency division processing on the second high-frequency clock signal to obtain a third internal feedback signal;

the frequency divider carries out frequency division processing on the second high-frequency clock signal to generate a third high-frequency clock signal;

Performing frequency multiplication processing on the third high-frequency clock signal by a second annular phase-locked loop to generate a second target clock signal;

the step of performing frequency multiplication processing on the third high-frequency clock signal by a second annular phase-locked loop to generate a second target clock signal includes:

detecting, by a second automatic frequency calibration module, a frequency difference between the third high frequency clock signal and a fourth internal feedback signal, and generating a fifth control signal based on the frequency difference between the third high frequency clock signal and the fourth internal feedback signal;

detecting, by a fourth phase frequency detector, a frequency difference and a phase difference between the third high frequency clock signal and the fourth internal feedback signal, and generating a sixth control signal based on the frequency difference and the phase difference between the third high frequency clock signal and the fourth internal feedback signal;

the second voltage pulse signal is subjected to low-pass filtering processing by a fourth loop filter, so that a fourth filtering signal is obtained;

Outputting, by a second ring voltage controlled oscillator, the second target clock signal in accordance with the fifth control signal and the fourth filtered signal;

and the fourth feedback frequency divider performs frequency division processing on the second target clock signal and outputs the fourth internal feedback signal.

18. The method of claim 17, wherein the frequency of the second target clock signal is determined according to Fout = Fin x N/M, wherein Fout is the frequency of the second target clock signal, fin is the frequency of the third high-frequency clock signal, M and N are frequency configuration coefficients of the second annular phase-locked loop, N has a value of 1 to 16, and M has a value of 1 to 2.

19. The method of generating a clock signal according to claim 17, wherein the bandwidth of the second loop-shaped phase locked loop is set to one twentieth of the frequency of the third high frequency clock signal to one tenth of the frequency of the third high frequency clock signal.

20. The method of claim 17, wherein the second input clock signal is provided by an external crystal oscillator.