CN202841098U - High-speed input/output interface and receiving circuit thereof - Google Patents
High-speed input/output interface and receiving circuit thereof Download PDFInfo
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- CN202841098U CN202841098U CN 201220361216 CN201220361216U CN202841098U CN 202841098 U CN202841098 U CN 202841098U CN 201220361216 CN201220361216 CN 201220361216 CN 201220361216 U CN201220361216 U CN 201220361216U CN 202841098 U CN202841098 U CN 202841098U
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Abstract
The utility model discloses a high-speed input/output interface and a receiving circuit thereof. The receiving circuit of the high-speed input/output interface is composed of a data receiving buffer unit, a received data sampling circuit, a clock receiving buffer unit, a clock recovery circuit, and a first phase integrator. The clock recovery circuit comprises a phase-locked loop, a second phase integrator, and a clock sampling circuit; the phase-locked loop generates a local reference clock signal; the second phase integrator obtains a clock sampling clock signal according to the local reference clock signal and a clock signal from the clock receiving buffer unit; and the clock sampling circuit carries out sampling on the clock signal from an input clock buffer unit based on the clock sampling clock signal so as to obtain a recovery clock signal. Therefore, the clock recovery circuit is utilized to carry out clock recovery, so that the recovery clock signal is not relevant to the input clock signal directly; therefore, the effects of jittering and frequency deviation of the input clock signal can be reduced, thereby improving the stability.
Description
Technical field
The utility model relates to the high-speed interface field, relates in particular to a kind of receiving circuit of the high speed input/output interface (I/O) with the forward direction clock.
Background technology
Owing to the impact of the various non-ideal factors such as synchronous between clock jitter, deflection, formation and crosstalk noise, the further raising of parallel transmission speed faces huge challenge.The serial transmission mode becomes the main selection of high speed data transmission system under the deep-submicron gradually.
Fig. 1 shows existing a kind of high speed input/output interface structure with the forward direction clock.As shown in Figure 1, described input/output interface comprises transmitting terminal (or claiming transtation mission circuit) and receiving terminal (or claiming receiving circuit).Described transmitting terminal comprises that sending d type flip flop, data transmission buffer memory, phase-locked loop (PLL) and clock sends buffer memory.Described receiving terminal comprises that data receiver buffer memory, reception d type flip flop, clock receive buffer memory, delay phase-locked loop (DLL) and both phase integrator (PI).
Delay phase-locked loop can recover to be restored clock signal according to input clock signal, but recovered clock signal and input clock signal have a fixing phase difference.Yet because the output signal of delay phase-locked loop is directly related with input signal, the shake of input signal and frequency drift can be directly reflected into the recovered clock signal, thereby have had influence on the performance of receiving terminal.Therefore, wish to propose a kind of improved technical scheme and overcome the problems referred to above.
The utility model content
For problems of the prior art, the utility model proposes a kind of receiving circuit of high speed input/output interface, the impact that it can reduce input jiffer and frequency deviation has strengthened the performance of receiving circuit.
For problems of the prior art, the utility model proposes a kind of high speed input/output interface, the impact that it can reduce input jiffer and frequency deviation has strengthened the performance of receiving circuit.
According to an aspect of the present utility model, the utility model proposes a kind of receiving circuit of high speed input/output interface, it comprises: reception and buffer memory are from the data receiver buffer memory of the data-signal of transtation mission circuit; Obtain exporting the receive data sample circuit of data according to data sampling clock signal to sampling from the data-signal of described data receiver buffer memory; Reception and buffer memory receive buffer memory from the clock of the clock signal of transtation mission circuit; According to the be restored clock recovery circuitry of clock signal of the recovering clock signals that receives buffer memory from described clock, obtain the first both phase integrator of described data sampling clock signal according to described recovered clock signal.Wherein said clock recovery circuitry comprises phase-locked loop, the second both phase integrator and clock sampling circuit, described phase-locked loop produces local reference clock signal, described the second both phase integrator obtains the clock sampling clock signal according to local reference clock signal with from the clock signal that described clock receives buffer memory, and described clock sampling circuit obtains described recovered clock signal based on described clock sampling clock signal to sampling from the clock signal of described input clock buffer memory.
According to an aspect of the present utility model, the utility model proposes a kind of high speed input/output interface, it comprises transtation mission circuit and aforesaid receiving circuit.
Compared with prior art, the clock recovery circuitry that the utility model is adopted phase-locked loop and both phase integrator composition recovers clock, so that the recovered clock signal is not directly related with input clock signal, reduced the shake of input clock signal and the impact of frequency deviation, improved stability.
Description of drawings
Fig. 1 is the topology example figure of the high speed input/output interface of prior art;
Fig. 2 is the high speed input/output interface topology example figure in one embodiment in the utility model;
Fig. 3 is the phase-locked loop structured flowchart in one embodiment in the clock recovery circuitry among Fig. 2;
Fig. 4 is the second both phase integrator structured flowchart in one embodiment in the clock recovery circuitry among Fig. 2;
Fig. 5 is the sequential schematic diagram of each signal of the both phase integrator among Fig. 4.
Embodiment
Below in conjunction with accompanying drawing the utility model is elaborated.
Fig. 2 is the high speed input/output interface topology example figure in one embodiment in the utility model.As shown in Figure 2, described high speed input and output (I/O) interface comprises transtation mission circuit (or claiming transmitting terminal) 100 and the receiving circuit (or claiming receiving terminal) 200 that carries out communication by communication channel 300 and described transtation mission circuit 100.
Described transtation mission circuit 100 comprises a plurality of data transmitting channels and a clock sendaisle, comprises at data transmitting channel sending data sampling circuit 110 and data transmission buffer memory 120, comprises that at the clock sendaisle phase-locked loop 130 and clock send buffer memory 140.Described phase-locked loop 130 obtains sampled clock signal based on the local reference clock signal of transtation mission circuit 100, and described sampled clock signal is sent to receiving circuit 200 via clock transmission buffer memory 140 and communication channel 300.Described data sampling circuit 110 is sampled to input data Data in according to the sampled clock signal of phase-locked loop 130 outputs, and sampled data is sent to receiving circuit 200 via data transmission buffer memory 120 and communication channel 300.
In one embodiment, described transmission data sampling circuit 110 is d type flip flop.
Described receiving circuit 200 comprises data receiving channel and clock receive path of a plurality of correspondences, comprises data receiver buffer memory 210 and receive data sample circuit 220 at data receiving channel.Described data receiver buffer memory 210 receptions and buffer memory are from the data-signal of transtation mission circuit 100.Described receive data sample circuit 220 obtains exporting data Data out according to the data sampling clock signal from the first both phase integrator 230 to sampling from the data-signal of described data receiver buffer memory 210.Comprise that at the clock receive path clock receives buffer memory 240 and clock recovery circuitry 250.240 receptions of described clock reception buffer memory and buffer memory are from the clock signal clk of transtation mission circuit
InDescribed clock recovery circuitry 250 is according to the clock signal clk that receives buffer memory 240 from described clock
InThe recovery clock signal clk that is restored
RecDescribed the first both phase integrator 230 is according to described recovered clock signal CLK
RecObtain described data sampling clock signal.
Wherein said clock recovery circuitry comprises phase-locked loop 251, the second both phase integrator 252 and clock sampling circuit 253.Described phase-locked loop 251 produces local reference clock signal CLK
Loc, described the second both phase integrator 252 is according to local reference clock signal CLK
LocWith the clock signal clk that receives buffer memory 240 from described clock
InObtain the clock sampling clock signal clk
Sc, described clock sampling circuit 253 is based on described clock sampling clock signal clk
ScTo the clock signal clk from described input clock buffer memory 240
InSample and obtain described recovered clock signal CLK
Rec
In one embodiment, described receive data sample circuit 220 is d type flip flop, and described clock sampling circuit 253 also is d type flip flop.
Fig. 3 is phase-locked loop 251 structured flowchart in one embodiment in the clock recovery circuitry 250 among Fig. 2.As shown in Figure 3, described phase-locked loop comprises phase frequency detector 310, charge pump 320, low pass filter 330, voltage controlled oscillator 340 and frequency divider 350.Described phase frequency detector 310 is differentiated local original clock signal CLK
OrigAnd frequency and phase difference between the sub-frequency clock signal that obtains of described frequency divider 350.Described charge pump 320 changes into a voltage signal with described frequency and phase difference.Described low pass filter 330 suppresses the high fdrequency component of described charge pump 320 outputs, and low frequency component is flowed to voltage controlled oscillator 340.Described voltage controlled oscillator 340 produces described local reference clock signal CLK according to the voltage signal of input
Loc, 350 couples of described local reference clock signal CLK of described frequency divider
LocCarry out producing sub-frequency clock signal behind the frequency division.If local reference clock signal CLK
LocHigher, then control described voltage controlled oscillator and reduce frequency, if local reference clock signal CLK
LocOn the low side, then controlling described voltage controlled oscillator increases frequency, final so that local reference clock signal CLK
LocBe locked in the clock signal clk of transtation mission circuit
InSame frequency scope in.In this example, described local reference clock signal CLK
LocTwo clock signals for quadrature.
Fig. 4 is the second both phase integrator structured flowchart in one embodiment in the clock recovery circuitry among Fig. 2.The second both phase integrator 251 comprises phase frequency detector 410, logical circuit 420, digital to analog converter 430 and phase place synthesis module 440.
Described phase frequency detector 410 is differentiated the clock signal clk that receives buffer memory from described clock
InWith local reference clock signal CLK
LocBetween frequency and phase difference.Described logical circuit 420 is calculated the margin of error according to described frequency and phasometer.Described digital to analog converter 430 converts the described margin of error to analog current signal.Described phase place synthesis module 440 produces described clock sampling clock signal clk under the control of described analog current signal
Sc, described clock sampling clock signal clk
ScWith described local reference clock signal CLK
InHave certain phase difference △ A (this phase difference and CLK
InAnd CLK
LocBetween frequency relevant with phase difference), so that described clock sampling clock signal clk
ScWith the described clock signal clk that receives buffer memory from described clock
InBetween have the phase difference of predetermined phase, such as 90 degree, like this clock sampling circuit 253 can be always at optimum sampling point to input clock signal CLK
InSample, clock signal clk finally is restored
RecThis recovered clock signal CLK
RecWith input clock signal CLK
InWith frequently and have a fixed skew, simultaneously and input clock signal CLK
InNon-directly related, effectively reduced the impact of shake and frequency drift.
The utility model adopts the clock signal of phase-locked loop generation and transtation mission circuit with local reference clock signal frequently, described both phase integrator produces the clock sampling clock signal not directly related with the clock signal of transtation mission circuit based on the clock signal of local reference clock signal and transtation mission circuit, described clock sampling circuit is sampled to the clock signal of described transtation mission circuit based on described clock sampling clock signal and is obtained the clock recovery signal not directly related with the clock signal of transtation mission circuit, reduced the directly related property of recovered clock signal with input clock signal, reduce the shake of input clock signal and the impact of frequency deviation, improved stability.
Although described the utility model by embodiment, those of ordinary skills know, the utility model has many distortion and variation and does not break away from spirit of the present utility model, wishes that appended claim comprises these distortion and variation and do not break away from spirit of the present utility model.
Claims (6)
1. the receiving circuit of a high speed input/output interface is characterized in that, it comprises:
Reception and buffer memory are from the data receiver buffer memory of the data-signal of transtation mission circuit;
Obtain exporting the receive data sample circuit of data according to data sampling clock signal to sampling from the data-signal of described data receiver buffer memory;
Reception and buffer memory receive buffer memory from the clock of the clock signal of transtation mission circuit;
According to the be restored clock recovery circuitry of clock signal of the recovering clock signals that receives buffer memory from described clock,
Obtain the first both phase integrator of described data sampling clock signal according to described recovered clock signal,
Wherein said clock recovery circuitry comprises phase-locked loop, the second both phase integrator and clock sampling circuit, described phase-locked loop produces local reference clock signal, described the second both phase integrator obtains the clock sampling clock signal according to local reference clock signal with from the clock signal that described clock receives buffer memory, and described clock sampling circuit obtains described recovered clock signal based on described clock sampling clock signal to sampling from the clock signal of described input clock buffer memory.
2. receiving circuit according to claim 1 is characterized in that, described receive data sample circuit is d type flip flop, and described clock sampling circuit is d type flip flop,
The clock signal of described local reference clock signal and transtation mission circuit is frequency together,
Described clock sampling clock signal and described local reference clock signal have certain phase difference, this phase difference and described local reference clock signal and receive the phase difference of clock signal of buffer memory from described clock relevant.
3. receiving circuit according to claim 2 is characterized in that, described phase-locked loop comprises phase frequency detector, charge pump, low pass filter, voltage controlled oscillator and frequency divider,
Described phase frequency detector is differentiated frequency and the phase difference between the sub-frequency clock signal that local original clock signal and described frequency divider obtain,
Described charge pump changes into a voltage signal with described frequency and phase difference,
Described low pass filter suppresses the high fdrequency component of described charge pump output, and low frequency component is flowed to voltage controlled oscillator,
Described voltage controlled oscillator produces described local reference clock signal according to the voltage signal of input,
Described frequency divider carries out producing sub-frequency clock signal behind the frequency division to described local reference clock signal.
4. receiving circuit according to claim 2 is characterized in that, the second both phase integrator comprises phase frequency detector, logical circuit, digital to analog converter and phase place synthesis module,
Described phase frequency detector discriminating receives the clock signal of buffer memory and frequency and the phase difference between the local reference clock signal from described clock,
Described logical circuit is calculated the margin of error according to described frequency and phasometer;
Described digital to analog converter converts the described margin of error to analog current signal;
Described phase place synthesis module produces described clock sampling clock signal under the control of described analog current signal.
5. receiving circuit according to claim 4, it is characterized in that, described clock sampling clock signal and described local reference clock signal have certain phase difference, so that have the phase difference of predetermined phase between described clock sampling clock signal and the described clock signal from described clock reception buffer memory.
6. high speed input/output interface, it comprises transtation mission circuit and receiving circuit, it is characterized in that, described receiving circuit is the arbitrary described receiving circuit of claim 1-5.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220361216 CN202841098U (en) | 2012-07-25 | 2012-07-25 | High-speed input/output interface and receiving circuit thereof |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220361216 CN202841098U (en) | 2012-07-25 | 2012-07-25 | High-speed input/output interface and receiving circuit thereof |
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| CN202841098U true CN202841098U (en) | 2013-03-27 |
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| CN 201220361216 Expired - Lifetime CN202841098U (en) | 2012-07-25 | 2012-07-25 | High-speed input/output interface and receiving circuit thereof |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102769455A (en) * | 2012-07-25 | 2012-11-07 | 苏州亮智科技有限公司 | High speed input/output interface and receiving circuit thereof |
| CN104734697A (en) * | 2013-11-19 | 2015-06-24 | 英特尔公司 | Clock Calibration Using Asynchronous Digital Sampling |
| CN112241384A (en) * | 2019-07-19 | 2021-01-19 | 上海复旦微电子集团股份有限公司 | Universal high-speed serial differential signal shunt circuit and method |
-
2012
- 2012-07-25 CN CN 201220361216 patent/CN202841098U/en not_active Expired - Lifetime
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102769455A (en) * | 2012-07-25 | 2012-11-07 | 苏州亮智科技有限公司 | High speed input/output interface and receiving circuit thereof |
| CN102769455B (en) * | 2012-07-25 | 2014-08-13 | 苏州亮智科技有限公司 | High speed input/output interface and receiving circuit thereof |
| CN104734697A (en) * | 2013-11-19 | 2015-06-24 | 英特尔公司 | Clock Calibration Using Asynchronous Digital Sampling |
| CN112241384A (en) * | 2019-07-19 | 2021-01-19 | 上海复旦微电子集团股份有限公司 | Universal high-speed serial differential signal shunt circuit and method |
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| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20170306 Address after: Pudong New Area Zhangjiang hi tech road 201203 Shanghai City No. 1158 Zhang No. 2 Building 7 floor Patentee after: BRITE SEMICONDUCTOR (SHANGHAI) Corp. Address before: Suzhou City, Jiangsu province 215021 international science and Technology Park No. 1355 Jinji Lake Avenue Suzhou industrial park two D102-2 Patentee before: SUZHOU LIANGZHI TECHNOLOGY Co.,Ltd. |
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| TR01 | Transfer of patent right | ||
| CP03 | Change of name, title or address |
Address after: 201200 6th floor, building 2, Lide international, 1158 Zhangdong Road, Pudong New Area pilot Free Trade Zone, Shanghai Patentee after: Canxin semiconductor (Shanghai) Co.,Ltd. Address before: 201203 7th floor, building 2, 1158 Zhangdong Road, Zhangjiang hi tech, Pudong New Area, Shanghai Patentee before: BRITE SEMICONDUCTOR (SHANGHAI) Corp. |
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| CP03 | Change of name, title or address | ||
| CX01 | Expiry of patent term |
Granted publication date: 20130327 |
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| CX01 | Expiry of patent term |