CN104410893A - Method for adjusting DDR working frequency through television demodulation SOC - Google Patents
Method for adjusting DDR working frequency through television demodulation SOC Download PDFInfo
- Publication number
- CN104410893A CN104410893A CN201410735837.0A CN201410735837A CN104410893A CN 104410893 A CN104410893 A CN 104410893A CN 201410735837 A CN201410735837 A CN 201410735837A CN 104410893 A CN104410893 A CN 104410893A
- Authority
- CN
- China
- Prior art keywords
- ddr
- frequency
- clock
- demodulation
- frequency range
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
- H04N21/41—Structure of client; Structure of client peripherals
- H04N21/426—Internal components of the client ; Characteristics thereof
- H04N21/42607—Internal components of the client ; Characteristics thereof for processing the incoming bitstream
- H04N21/42615—Internal components of the client ; Characteristics thereof for processing the incoming bitstream involving specific demultiplexing arrangements
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
- H04N21/41—Structure of client; Structure of client peripherals
- H04N21/426—Internal components of the client ; Characteristics thereof
- H04N21/42676—Internal components of the client ; Characteristics thereof for modulating an analogue carrier signal to encode digital information or demodulating it to decode digital information, e.g. ADSL or cable modem
Abstract
The invention relates to a method for adjusting DDR (Double Data Rate SDRAM) working frequency through a television demodulation SOC (System On Chip). When television signals are demodulated, interference caused by DDR action is transmitted to a channel demodulation module to reduce performance of the channel modulation module. The DDR working frequency chip adjusting method disclosed by the invention adopts a clock selector, a control state machine and two DDR clock sources, wherein the control state machine generates optimal selection signals according to a central frequency point F of a frequency band to be demodulated and a safe frequency point distance W; the control state machine controls the clock selector to select one of the two DDR clock sources as a signal output of DDR clocks. According to the method, a clock source selecting function to DDR is added in the television demodulation SOC chip, so that interference signals caused by DDR can be removed from a specific frequency band when a television program transmitted within the specific frequency band is demodulated, so as to reduce input noise of the channel demodulation module and improve properties of the channel demodulation module.
Description
Technical field
The invention belongs to technical field of integrated circuits, relate to a kind of method that TV demodulation SOC adjusts DDR operating frequency.
Background technology
DDR SDRAM (double-speed synchronous DRAM is called for short DDR) is the important peripheral hardware of SOC (System OnChip, on-chip system chip) chip.The operating frequency of ddr interface is high, and operating current is large, can cause higher conducted interference and radiated interference on chip and Circuits System.If the frequency range of the interference that DDR causes is not in the frequency range of the input signal of the sensitive circuit of SOC, usual this interference can not have an impact to the performance of SOC.
TV demodulation SOC refers to the SOC comprising television transmission channel demodulation module.Conventional television channel demodulation module has the channel demodulation module of CATV transmission standard, the channel demodulation module of satellite TV transmissions standard, the channel demodulation module etc. of ground transmission standard.
A kind of TV transmission standards marks off multiple frequency range in the frequency band used.Each band transmissions TV programme.When wanting the TV programme transmitted in certain special frequency channel of demodulation, the Signal transmissions in this frequency range, by the target signal filter outside frequency range, is carried out demodulation process to inside by the incorporating filter of channel demodulation module.
The frequency of the interference signal that DDR causes concentrates on the fundamental frequency of DDR operating frequency with on times frequency.Although the fundamental frequency of DDR operating frequency and frequency multiplication point quantity are seldom, the interval between frequency is very large.If but during the TV programme transmitted in certain special frequency channel of demodulation, a frequency in interference signal is in special frequency channel, then the DDR interference caused that works will be conveyed into channel demodulation inside modules, reduce the performance of channel demodulation module.
Fig. 1 is the signal of interference and frequency range relation.F1 represents a kind of fundamental frequency of DDR operating frequency, and 2F1,3F1,4F1 represent 2 frequencys multiplication, 3 frequencys multiplication, 4 frequencys multiplication of F1 respectively.F2 represents the fundamental frequency of another kind of DDR operating frequency, and 2F2,3F2 represent 2 frequencys multiplication and 3 frequencys multiplication of F2 respectively.A, b, c, d, e, f represent different but adjacent frequency range respectively.When the operating frequency of DDR is F1, a, c, e frequency range is subject to the interference of 2 frequencys multiplication of F1,3 frequencys multiplication and 4 frequencys multiplication respectively.When the operating frequency of DDR is F2, b, e frequency range is subject to 2 frequencys multiplication of F2 and the interference of 3 frequencys multiplication.No matter DDR is operated in F1 or F2, has more frequency range to be subject to the interference of DDR signal.
Patent CN201320003017.3 " the interference apparatus for removing for Signal transmissions machine " can in scheduled transmission frequency, and the frequency of adjustment clock signal, to remove the interference of the signal relevant to clock signal to described scheduled transmission frequency.But this patent only have adjusted the clock frequency of Signal transmissions machine, the interference that the clock for non-signal conveyer causes cannot remove.
Channel demodulation module in TV demodulation SOC is equivalent to the Signal transmissions machine described in patent CN201320003017.3.TV demodulation SOC, except external crystal-controlled oscillation input clock, also has DDR clock, multiple clock such as video output clock.Because video output clock must meet video output standard, cause the frequency of external crystal-controlled oscillation input clock to protect and immobilize, cannot carry out adjusting by the method described in patent CN201320003017.3.The interference of the DDR clock generating in TV demodulation SOC is the important interference that channel demodulation module faces.And DDR clock is separate with the clock of channel demodulation module, the interference of DDR clock generating cannot be reduced by the clock of adjustment channel demodulation module by the method described in patent CN201320003017.3.
Summary of the invention
The object of the invention is for the deficiencies in the prior art, a kind of method that TV demodulation SOC adjusts DDR operating frequency is provided.
The inventive method adopts a clock selector, a state of a control machine and two DDR clock sources.State of a control machine produces optimum selection signal according to the current center frequency point F of the frequency range of demodulation and safe frequency distance W that wants; State of a control machine controls clock selector and selects a clock in two DDR clock sources to export as DDR clock signal; Concrete grammar is:
Using the current center frequency point F of the frequency range of demodulation and safe frequency distance W that wants as two inputs of state of a control machine, state of a control machine calculates according to F and W to be needed the lower frequency Fd of protection and needs the upper frequency Fu that protect, is greater than Fd and the frequency range being less than Fu is the frequency range that needs are protected; Fd=F-W, Fu=F+W;
Select qualified two the DDR clock sources of race, specifically: | n × F1-k × F2| > 2W; Wherein, n × F1 is the frequency multiplication of the operating frequency F1 of a DDR clock source, n=1,2,3 ..., 10; K × F2 is the frequency multiplication of the operating frequency F2 of the 2nd DDR clock source, k=1,2,3 ..., 10;
According to the operating frequency F1 of a DDR clock source, judge F1 frequency multiplication n × F1 (n=1,2,3 ..., 10) whether be positioned at the frequency range needing protection; If have the frequency multiplication being positioned at the frequency range needing protection in ten of F1 frequency multiplication n × F1, then clock selector selects the 2nd DDR clock source to export as DDR clock signal; If ten of F1 frequency multiplication n × F1 are not all in the frequency range needing protection, then clock selector selects a DDR clock source to export as DDR clock signal; According to output DDR clock signal adjustment DDR operating frequency.
The inventive method by increasing clock source selection function to DDR in TV demodulation SOC, when realizing the TV programme of transmission in certain special frequency channel of demodulation, the interference signal caused by DDR moves out of special frequency channel, thus reduce the input noise of channel demodulation module, improve the performance of channel demodulation module.
Accompanying drawing explanation
Fig. 1 is interference and frequency range relation schematic diagram;
Fig. 2 is the structural representation of circuit in the inventive method.
Embodiment
A method for TV demodulation SOC adjustment DDR operating frequency, the method adopts a clock selector, a state of a control machine and two DDR clock sources.State of a control machine produces optimum selection signal according to the current center frequency point F of the frequency range of demodulation and safe frequency distance W that wants; State of a control machine controls clock selector and selects a clock in two DDR clock sources to export as DDR clock signal; Concrete grammar is:
Using the current center frequency point F of the frequency range of demodulation and safe frequency distance W that wants as two inputs of state of a control machine, state of a control machine calculates according to F and W to be needed the lower frequency Fd of protection and needs the upper frequency Fu that protect, is greater than Fd and the frequency range being less than Fu is the frequency range that needs are protected; Fd=F-W, Fu=F+W;
Select qualified two the DDR clock sources of race, specifically: | n × F1-k × F2| > 2W; Wherein, n × F1 is the frequency multiplication of the operating frequency F1 of a DDR clock source, n=1,2,3 ..., 10; K × F2 is the frequency multiplication of the operating frequency F2 of the 2nd DDR clock source, k=1,2,3 ..., 10;
According to the operating frequency F1 of a DDR clock source, judge F1 frequency multiplication n × F1 (n=1,2,3 ..., 10) whether be positioned at the frequency range needing protection; If have the frequency multiplication being positioned at the frequency range needing protection in ten of F1 frequency multiplication n × F1, then clock selector selects the 2nd DDR clock source to export as DDR clock signal; If ten of F1 frequency multiplication n × F1 are not all in the frequency range needing protection, then clock selector selects a DDR clock source to export as DDR clock signal; According to output DDR clock signal adjustment DDR operating frequency.
The structure of circuit of the present invention as shown in Figure 2, comprises a clock selector S, a state of a control machine M, two DDR clock source C1 and C2.Two input end of clock of clock selector S connect DDR clock source C1 and C2 respectively; The output terminal of clock of clock selector S connects the input end of clock of DDR; The selection output of the selection input connection control state machine M of clock selector S.
The current center frequency point F wanting the frequency range of demodulation of center frequency point input input of state of a control machine M; A safe frequency distance input end of state of a control machine M inputs safe frequency distance W; The operating frequency F1 of clock frequency input input an one DDR clock source C1 of state of a control machine M; The input of state of a control machine M inputs actual value by CPU according to SOC present behavior.
Clock selector S has two input end of clock, a selection input and an output; Function is according to selecting the value of input to connect different input end of clock and output.
For Fig. 1, when the frequency range wanting demodulation is b, d, e, selection operating frequency is the work clock of clock as DDR of a DDR clock source C1 of F1; When the frequency range wanting demodulation is a, c, selection operating frequency is the work clock of clock as DDR of the 2nd DDR clock source C2 of F2.Not only select suitable F1 and F2, avoid occurring there is the frequency multiplication of F1 but also have the situation of the frequency multiplication of F2 to occur in frequency range e.
It should be understood that above-mentioned example is just to explanation of the present invention, instead of limitation of the present invention, any innovation and creation do not exceeded in spirit of the present invention, all fall within protection scope of the present invention.
Claims (1)
1. a method for TV demodulation SOC adjustment DDR operating frequency, is characterized in that the method adopts a clock selector, a state of a control machine and two DDR clock sources; State of a control machine produces optimum selection signal according to the current center frequency point F of the frequency range of demodulation and safe frequency distance W that wants; State of a control machine controls clock selector and selects a clock in two DDR clock sources to export as DDR clock signal; Concrete grammar is:
Using the current center frequency point F of the frequency range of demodulation and safe frequency distance W that wants as two inputs of state of a control machine, state of a control machine calculates according to F and W to be needed the lower frequency Fd of protection and needs the upper frequency Fu that protect, is greater than Fd and the frequency range being less than Fu is the frequency range that needs are protected; Fd=F-W, Fu=F+W;
Select qualified two the DDR clock sources of race, specifically: | n × F1-k × F2| > 2W; Wherein, n × F1 is the frequency multiplication of the operating frequency F1 of a DDR clock source, n=1,2,3 ..., 10; K × F2 is the frequency multiplication of the operating frequency F2 of the 2nd DDR clock source, k=1,2,3 ..., 10;
According to the operating frequency F1 of a DDR clock source, judge whether the frequency multiplication n × F1 of F1 is positioned at the frequency range needing protection; If have the frequency multiplication being positioned at the frequency range needing protection in ten of F1 frequency multiplication n × F1, then clock selector selects the 2nd DDR clock source to export as DDR clock signal; If ten of F1 frequency multiplication n × F1 are not all in the frequency range needing protection, then clock selector selects a DDR clock source to export as DDR clock signal;
According to output DDR clock signal adjustment DDR operating frequency.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201410735837.0A CN104410893B (en) | 2014-12-05 | 2014-12-05 | A kind of method that TV demodulation SOC adjusts DDR working frequencies |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201410735837.0A CN104410893B (en) | 2014-12-05 | 2014-12-05 | A kind of method that TV demodulation SOC adjusts DDR working frequencies |
Publications (2)
Publication Number | Publication Date |
---|---|
CN104410893A true CN104410893A (en) | 2015-03-11 |
CN104410893B CN104410893B (en) | 2017-06-23 |
Family
ID=52648477
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201410735837.0A Active CN104410893B (en) | 2014-12-05 | 2014-12-05 | A kind of method that TV demodulation SOC adjusts DDR working frequencies |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN104410893B (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN104918093A (en) * | 2015-05-20 | 2015-09-16 | 深圳创维-Rgb电子有限公司 | Television high-frequency signal anti-interference method and television high-frequency signal anti-interference device |
CN105872535A (en) * | 2016-02-05 | 2016-08-17 | 四川长虹电器股份有限公司 | Processing method for radiated interference radio frequency signals of DDR system of television |
CN112202503A (en) * | 2020-09-22 | 2021-01-08 | 展讯通信(上海)有限公司 | Interference processing method, terminal equipment and computer readable storage medium |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2012103558A1 (en) * | 2011-01-28 | 2012-08-02 | Qualcomm Incorporated | Bus clock frequency scaling for a bus interconnect and related devices, systems, and methods |
CN102834867A (en) * | 2010-06-08 | 2012-12-19 | 拉姆伯斯公司 | Integrated circuit device timing calibration |
CN103117756A (en) * | 2013-01-05 | 2013-05-22 | 北京昆腾微电子有限公司 | Device and method for removing interference in signal transmission machine |
US20140013138A1 (en) * | 2012-07-06 | 2014-01-09 | Kabushiki Kaisha Toshiba | Memory control device, semiconductor device, and system board |
-
2014
- 2014-12-05 CN CN201410735837.0A patent/CN104410893B/en active Active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102834867A (en) * | 2010-06-08 | 2012-12-19 | 拉姆伯斯公司 | Integrated circuit device timing calibration |
WO2012103558A1 (en) * | 2011-01-28 | 2012-08-02 | Qualcomm Incorporated | Bus clock frequency scaling for a bus interconnect and related devices, systems, and methods |
US20140013138A1 (en) * | 2012-07-06 | 2014-01-09 | Kabushiki Kaisha Toshiba | Memory control device, semiconductor device, and system board |
CN103117756A (en) * | 2013-01-05 | 2013-05-22 | 北京昆腾微电子有限公司 | Device and method for removing interference in signal transmission machine |
Non-Patent Citations (1)
Title |
---|
朱士阑: "数字电视接收机中的信号完整性和时序设计", 《中国优秀硕士学位论文全文数据库 信息科技辑》 * |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN104918093A (en) * | 2015-05-20 | 2015-09-16 | 深圳创维-Rgb电子有限公司 | Television high-frequency signal anti-interference method and television high-frequency signal anti-interference device |
CN104918093B (en) * | 2015-05-20 | 2018-09-04 | 深圳创维-Rgb电子有限公司 | High video signal anti-disturbance method and device |
CN105872535A (en) * | 2016-02-05 | 2016-08-17 | 四川长虹电器股份有限公司 | Processing method for radiated interference radio frequency signals of DDR system of television |
CN105872535B (en) * | 2016-02-05 | 2017-11-10 | 四川长虹电器股份有限公司 | A kind of processing method of television set DDR systems radiation interference radiofrequency signal |
CN112202503A (en) * | 2020-09-22 | 2021-01-08 | 展讯通信(上海)有限公司 | Interference processing method, terminal equipment and computer readable storage medium |
Also Published As
Publication number | Publication date |
---|---|
CN104410893B (en) | 2017-06-23 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US10756881B2 (en) | Method and system for operating a communications device that communicates via inductive coupling | |
CN103379643A (en) | Method and device for eliminating interference | |
CN106230446B (en) | A kind of anti-jamming circuit, mobile terminal and the method for inhibiting harmonic wave interference | |
CN104410893A (en) | Method for adjusting DDR working frequency through television demodulation SOC | |
MY174515A (en) | Optical receiver and transceiver using the same | |
WO2011159724A3 (en) | Improved parametric signal processing and emitter systems and related methods | |
EP4293900A3 (en) | Multimode power amplifier module, chip and communication terminal | |
KR20160031234A (en) | Radio frequency processing apparatus and method | |
CN103647564A (en) | Binary channel shortwave signal diversity receiving system and receiving method thereof | |
WO2013188272A3 (en) | Optimizing power in a memory device | |
CN203608188U (en) | Dual-channel shortwave signal diversity receiving system | |
EP2242265A4 (en) | A wireless communication receiver, a wireless communication receiving method and a television receiver | |
CN103812811A (en) | Automatic control apparatus and method of digital signal peak power | |
GB2533752A (en) | Method and apparatus for mitigating radio frequency interference (RFI) in an electrical device | |
JP7111962B2 (en) | Control signal transmission/reception system and control signal transmission/reception method | |
CN104852729A (en) | Circuit and method for suppressing higher harmonic interference of digital clock | |
CN104469920A (en) | BODYSAR control method and system for wireless module | |
CN109738830A (en) | A kind of power sense circuit in radio frequency front end chip | |
EP4258673A3 (en) | Video transmission method, video reception method, video transmission device, and video reception device | |
CN104469206A (en) | Clock signal processing device and television signal generator | |
US9608573B2 (en) | Balanced Doherty power amplifier circuit and radio transmitter | |
CN204217045U (en) | Clock signal processing unit, television signal generator | |
CN104917478A (en) | Filter module based on sensor signal | |
CN203800047U (en) | Distribution structure enabling addition of capacitors in chip | |
CN204119356U (en) | A kind of single output satellite signal high-frequency tuner |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
GR01 | Patent grant | ||
GR01 | Patent grant |