CN104852729A - Circuit and method for suppressing higher harmonic interference of digital clock - Google Patents
Circuit and method for suppressing higher harmonic interference of digital clock Download PDFInfo
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Abstract
The invention discloses a circuit for suppressing higher harmonic interference of a digital clock. The circuit comprises a digital phase-locked loop (PLL) and a digital clock generating circuit connected with the digital PLL. The digital clock generating circuit is used for determining a duty cycle configuration mode according to a target operating frequency range of an analog circuit and an operating clock frequency point of a digital circuit, and converting a high-frequency clock signal into the operating clock of the digital circuit according to the duty cycle configuration mode and the operating clock frequency point of the digital circuit. Correspondingly, the invention also discloses a method for suppressing higher harmonic interference of the digital clock. The circuit and the method may reduce the energy, falling into a sensitive frequency range, of harmonics of the operating clock so as to suppress the higher harmonic interference of the operating clock of the digital circuit.
Description
Technical Field
The invention relates to the technical field of electronics, in particular to a circuit and a method for suppressing higher harmonic interference of a digital clock.
Background
The integration of a single Chip System (SOC) is an important way to realize a low-cost and high-performance System, i.e. a large-scale digital circuit and a high-performance radio frequency analog circuit are integrated On the same silicon substrate. As shown in fig. 1, in the digital-analog hybrid circuit, a digital circuit generates a large amount of digital noise, and the noise may have a certain influence on the performance of the rf analog circuit, as shown in fig. 2, a noise current generated by the digital circuit flipping is transmitted to the rf analog circuit on the same chip through the substrate, which may greatly reduce the performance of the rf analog circuit, and at the same time, the digital circuit flipping may also have a great influence on the rf analog circuit through power coupling.
The technical scheme disclosed by the prior art is as follows: the isolation ring is added to improve the isolation degree, so that the noise amplitude of the noise generated by the interference source and reaching the interfered circuit after the noise is isolated by the propagation path is smaller than the tolerance amplitude of the interfered circuit, namely the formula is satisfied: interference source (dBm) -isolation (dB) < interference receptor index requirement; however, the addition of the isolation ring can only reduce the influence of low-frequency interference signals on the radio frequency analog circuit, and the isolation degree of the isolation ring can be rapidly reduced for high-frequency signals such as higher harmonics of a working clock of a digital circuit;
the second technical scheme disclosed in the prior art is as follows: the clock frequency of the working clock of the digital circuit is adjusted arbitrarily, so that the interference of the working clock and the harmonic wave thereof can avoid the sensitive frequency band range; however, there are dozens of wireless rf bands, and no matter any clock frequency is selected, the harmonic of the digital circuit may fall into the band of a part of the rf band, as shown in fig. 3, so that the method of simply changing the frequency point of the working clock is not sufficient.
Disclosure of Invention
The invention provides a circuit and a method for inhibiting higher harmonic interference of a digital clock, which can reduce the energy of harmonic waves of a working clock falling into a sensitive frequency band, and further inhibit the higher harmonic interference of the working clock of a digital circuit.
The invention provides a circuit for suppressing higher harmonic interference of a digital clock, which comprises:
a digital phase-locked loop for generating a high frequency clock signal;
and the digital clock generating circuit is connected with the digital phase-locked loop and used for determining a duty ratio configuration mode according to a target working frequency band of the analog circuit and a working clock frequency point of the digital circuit and converting the high-frequency clock signal into a working clock of the digital circuit according to the duty ratio configuration mode and the working clock frequency point of the digital circuit.
In a first possible implementation manner of the first aspect, the duty cycle configuration modes include an equal duty cycle configuration mode and a non-equal duty cycle configuration mode;
the digital clock generation circuit is specifically configured to:
if the odd harmonic of the working clock frequency point of the digital circuit is in the target working frequency band of the analog circuit, selecting the unequal duty ratio configuration mode;
and if the even harmonic of the working clock frequency point of the digital circuit is in the target working frequency band of the analog circuit, selecting the equal duty ratio configuration mode.
In a second possible implementation manner of the first aspect, the digital clock generation circuit includes a counter, a duty mode register, a selector, an equal comparator, a greater than or equal to comparator, and an output register, where the duty mode register stores a first configuration value corresponding to an equal duty mode, a second configuration value corresponding to a non-equal duty mode, and a higher division coefficient bit, where:
the control end of the selector is connected with the output end of the duty ratio mode register, the first input end of the selector is accessed to the first configuration value, the second input end of the selector is accessed to the second configuration value, the output end of the selector is connected with the first input end of the equal comparator, the second input end of the equal comparator is connected with the output end of the counter, the output end of the equal comparator is connected with the zero clearing end of the output register,
the first input end of the comparator is connected with the output end of the counter, the second input end of the comparator is connected with the high-order frequency division coefficient, the output end of the comparator is respectively connected with the zero clearing end of the counter and the setting end of the output register,
the input end of the counter and the input end of the output register are connected with a high-frequency clock signal generated by the digital phase-locked loop, and the output end of the output register outputs a working clock of the digital circuit.
With reference to the second possible implementation manner of the first aspect, in a third possible implementation manner, if an odd harmonic of a working clock frequency point of the digital circuit is within a target working frequency band of the analog circuit, the selector controls the output terminal to output the second configuration value, so that a duty ratio of the output working clock is not equal to 50%;
if the even harmonic of the working clock frequency point of the digital circuit is within the target working frequency band of the analog circuit, the selector controls the output end to output the first configuration value, so that the duty ratio of the output working clock is equal to 50%.
With reference to the second possible implementation manner of the first aspect, in a fourth possible implementation manner, when the count value of the counter is equal to the output value of the selector, the equal comparator clears the output register;
and when the count value of the counter is greater than or equal to the high bit of the frequency division coefficient, the greater than or equal to comparator sets the output register and clears the counter.
Accordingly, the second aspect of the present invention also provides a method for suppressing higher harmonic interference of a digital clock, comprising:
generating a high-frequency clock signal through a digital phase-locked loop;
determining a duty ratio configuration mode according to a target working frequency band of the analog circuit and a working clock frequency point of the digital circuit;
and converting the high-frequency clock signal into a working clock of the digital circuit according to the duty ratio configuration mode and the working clock frequency point of the digital circuit.
In a first possible implementation manner of the second aspect, the duty cycle configuration modes include a constant duty cycle configuration mode and a non-constant duty cycle configuration mode;
the determining the duty ratio configuration mode according to the target working frequency band of the analog circuit and the working clock frequency point of the digital circuit comprises the following steps:
if the odd harmonic of the working clock frequency point of the digital circuit is in the target working frequency band of the analog circuit, selecting the unequal duty ratio configuration mode;
and if the even harmonic of the working clock frequency point of the digital circuit is in the target working frequency band of the analog circuit, selecting the equal duty ratio configuration mode.
With reference to the second aspect or the first possible implementation manner of the second aspect, in a second possible implementation manner, the analog circuit includes at least two operating frequency bands;
before determining the duty ratio configuration mode according to the target working frequency band of the analog circuit and the working clock frequency point of the digital circuit, the method further comprises:
detecting the frequency of harmonic waves of a working clock frequency point of the digital circuit in a working frequency band of the analog circuit;
and if the parity of the detected times of the harmonic waves is the same, taking any working frequency band of the analog circuit as the target working frequency band.
With reference to the second possible implementation manner of the second aspect, in a third possible implementation manner, if the number of detected harmonics has different parity, the method further includes:
detecting the energy of each of the harmonics within the operating frequency band of the analog circuit;
and taking the working frequency band of the analog circuit corresponding to the detected harmonic wave with the maximum energy as the target working frequency band.
The invention has the following beneficial effects:
the invention can determine the duty ratio configuration mode according to the target working frequency band of the analog circuit and the working clock frequency point of the digital circuit, converts the high-frequency clock signal into the working clock of the digital circuit according to the duty ratio configuration mode and the working clock frequency point of the digital circuit, and reduces the energy of the harmonic wave of the working clock falling into the sensitive frequency band by controlling the duty ratio of the working clock of the digital circuit, thereby inhibiting the interference of the higher harmonic wave of the working clock of the digital circuit.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to these drawings without creative efforts.
FIG. 1 is a diagram of RF digital-to-analog interference in the prior art;
FIG. 2 is a schematic diagram of interference of a digital circuit with a radio frequency analog circuit according to the prior art;
FIG. 3 is a schematic diagram of a harmonic interference RF band signal of the prior art;
FIG. 4 is a schematic diagram of a circuit for suppressing higher harmonic interference of a digital clock according to the present invention;
FIG. 5 is a schematic diagram of digital power supply noise measurement;
FIG. 6 is a graphical illustration of different harmonics versus duty cycle energy;
FIG. 7 is a schematic diagram of a non-equal duty cycle clock;
FIG. 8 is a schematic diagram of an equal duty cycle clock;
FIG. 9 is a comparative simulation of substrates for different harmonics and duty cycle energies;
fig. 10 is a schematic diagram of a method for suppressing higher harmonic interference of a digital clock according to the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Embodiments of the present invention provide a circuit for suppressing higher harmonic interference of a digital clock, which can reduce energy of a harmonic of a working clock falling into a sensitive frequency band by controlling a duty ratio of the working clock of a digital circuit, and further suppress the higher harmonic interference of the working clock of the digital circuit.
Referring to fig. 4, fig. 4 is a schematic diagram of a circuit for suppressing higher harmonic interference of a digital clock according to an embodiment of the present invention, and the circuit for suppressing higher harmonic interference of a digital clock according to the embodiment of the present invention shown in fig. 4 includes:
a digital phase-locked loop 41 for generating a high-frequency clock signal; wherein,
and the digital clock generating circuit 42 is connected with the digital phase-locked loop and used for determining a duty ratio configuration mode according to a target working frequency band of the analog circuit and a working clock frequency point of the digital circuit and converting the high-frequency clock signal into a working clock of the digital circuit according to the duty ratio configuration mode and the working clock frequency point of the digital circuit.
The duty ratio configuration mode comprises an equal duty ratio configuration mode and a non-equal duty ratio configuration mode, the equal duty ratio configuration mode can enable the duty ratio of the working clock of the digital circuit to be equal to 50%, and the non-equal duty ratio configuration mode can enable the duty ratio of the working clock of the digital circuit to be not equal to 50%; preferably, in the unequal duty ratio configuration mode, the duty ratio of the working clock of the digital circuit is 40% or 40%;
because the working clock of the digital circuit is an approximate square wave signal, through Fourier series expansion, the digital circuit overturns and introduces digital noise at the frequency point of the working clock, and has interference signals with stronger energy at higher harmonic frequency points, as shown in FIG. 4, interference signals exist at harmonics of 2, 3, 4, … … and the like of the working clock of the digital circuit; however, according to the fourier series expansion, as the duty ratio of the operating clock of the digital circuit changes, the frequency spectrum components of different harmonics also change, as shown in fig. 5, the energy of the harmonic of 1 st harmonic and 3 rd harmonic is the largest when the duty ratio is 50%, the energy of the harmonic is smaller when the duty ratio is 40% or 40%, the energy of the harmonic of 2 nd harmonic and 4 th harmonic is the largest when the duty ratio is 50%, the energy of the harmonic is smaller when the duty ratio is 40% or 40%, and the energy of the harmonic of 1 st harmonic when the duty ratio is 50% is greater than the energy of the harmonic of 3 rd harmonic when the duty ratio is 50%, to sum up:
(1) the energy of the odd harmonic is maximum when the duty ratio is 50%, and the energy is smaller when the duty ratio is 40% or 40%;
(2) the even harmonic wave has the minimum energy when the duty ratio is 50 percent, and has larger energy when the duty ratio is 40 percent or 40 percent;
(3) and the harmonic energy is gradually reduced along with the increase of the harmonic times.
The digital clock generation circuit 42 may be specifically configured to:
if the odd harmonic of the working clock frequency point of the digital circuit is in the target working frequency band of the analog circuit, in order to reduce the energy falling into the target working frequency band, controlling the duty ratio of the working clock of the digital circuit not to be equal to 50 percent, namely selecting the unequal duty ratio configuration mode; supposing that the working clock frequency point of the digital circuit is 245.74MHz, the target working frequency band of the analog circuit is 1710-1770 MHz, and since the 7 th harmonic of 245.74MHz is 1720.32MHz and is in the target working frequency band of the analog circuit, the digital clock generating circuit 42 selects an unequal duty cycle configuration mode to suppress the energy of the 7 th harmonic of the working clock frequency point of the digital circuit, thereby reducing the interference of the 7 th harmonic to the target working frequency band of the analog circuit;
if the even harmonic of the working clock frequency point of the digital circuit is in the target working frequency band of the analog circuit, in order to reduce the energy falling into the target working frequency band, controlling the duty ratio of the working clock of the digital circuit to be equal to 50 percent, namely selecting the equal duty ratio configuration mode; supposing that the working clock frequency point of the digital circuit is 245.74MHz, the target working frequency band of the analog circuit is 1920-1980 MHz, and since the 8 th harmonic of 245.74MHz is 1944.08MHz and is in the target working frequency band of the analog circuit, the digital clock generating circuit 42 selects an equal duty ratio configuration mode, suppresses the energy of the 8 th harmonic of the working clock frequency point of the digital circuit, and further reduces the interference of the 8 th harmonic to the target working frequency band of the analog circuit.
The digital clock generating circuit 42 may further include a counter 421, a duty mode register 422, a selector 423, an equal comparator 424, an equal to or greater than comparator 425, and an output register 426, where the duty mode register 422 stores a first configuration value corresponding to an equal duty mode, a second configuration value corresponding to a non-equal duty mode, and a higher division coefficient bit, where:
the control terminal of the selector 423 is connected to the output terminal of the duty mode register 422, the first input terminal of the selector 423 is connected to the first configuration value, the second input terminal of the selector 423 is connected to the second configuration value, the output terminal of the selector 423 is connected to the first input terminal of the equal comparator 424, the second input terminal of the equal comparator 424 is connected to the output terminal of the counter 421, the output terminal of the equal comparator 424 is connected to the clear terminal of the output register 426,
the first input end of the greater than or equal to comparator 425 is connected with the output end of the counter 421, the second input end of the greater than or equal to comparator 425 is connected with the high bit of the frequency division coefficient, the output end of the greater than or equal to comparator 425 is respectively connected with the zero clearing end of the counter 421 and the set end of the output register 426,
the input end of the counter 421 and the input end of the output register 426 are connected to the high-frequency clock signal generated by the digital phase-locked loop 41, and the output end of the output register 426 outputs the working clock of the digital circuit.
The working principle of the digital clock generating circuit 42 is as follows:
if the odd harmonic of the working clock frequency point of the digital circuit is within the target working frequency band of the analog circuit, the selector 423 controls the output end to output the second configuration value, so that the duty ratio of the output working clock is not equal to 50%;
if the even harmonic of the working clock frequency point of the digital circuit is within the target working frequency band of the analog circuit, the selector 423 controls the output end to output the first configuration value, so that the duty ratio of the output working clock is equal to 50%;
when the count value of the counter 421 is equal to the output value of the selector 423, the equal comparator 424 clears the output register 426;
when the count value of the counter 421 is greater than or equal to the high bit of the frequency division coefficient, the greater than or equal to comparator 425 sets the output register 426 and clears the counter 421.
The high frequency clock signal is 2949.12MHz for example, the working clock of the digital circuit is 245.76MHz for example, and the working principle of the digital clock generating circuit 42 is analyzed in detail:
since the operating clock of the digital circuit is the frequency division of the high frequency clock signal by 12, the high order of the frequency division coefficient is 11, the counting range of the counter 421 is 0-11, the first configuration value is 5, and the second configuration value is not equal to 5, the second configuration value in this embodiment takes 3 as an example;
if the odd harmonic of the working clock frequency point of the digital circuit is in the target working frequency band of the analog circuit, the selector 423 selects to output the second configuration value, the output value of the output end of the selector 423 is 3, and when the count value of the counter 421 is equal to 3, the equal comparator 424 clears the output register 426, so that the output register 426 outputs a low level, which is equivalent to generating a falling edge of the working clock of the digital circuit; when the count value of the counter 421 is 11, the comparator 425 sets the output register 426, which is equivalent to generating a rising edge of the operating clock of the digital circuit, and clears the counter 421, which is equivalent to counting from 0 again, and the unequal duty cycle clock diagram is shown in fig. 7, and the duty cycle is equal to 33%;
if the even harmonic of the working clock frequency point of the digital circuit is in the target working frequency band of the analog circuit, the selector 423 selects to output a first configuration value, the output value of the output end of the selector 423 is 5, and when the count value of the counter 421 is equal to 5, the equal comparator 424 clears the output register 426, so that the output register 426 outputs a low level, which is equivalent to generating a falling edge of the working clock of the digital circuit; when the count value of the counter 421 is 11, the comparator 425 sets the output register 426, which is equivalent to generating a rising edge of the operating clock of the digital circuit, and clears the counter 421, which is equivalent to counting from 0 again, and the duty cycle clock diagram is as shown in fig. 8, and the duty cycle thereof is equal to 50%;
as shown in fig. 9, at the 1 st harmonic, when the duty ratio is 50%, the energy is-54.98, and when the duty ratio is 20%, the energy is-58.93, and by controlling the duty ratio of the working clock of the digital signal according to the embodiment of the present invention, the interference can be reduced by 3.95 dB; at the 2 nd harmonic, when the duty ratio is 50%, the energy is-62.06, and when the duty ratio is 20%, the energy is-56.51, and by adopting the embodiment of the invention to control the duty ratio of the working clock of the digital signal, the interference can be reduced by 5.55 dB.
According to the embodiment of the invention, the duty ratio configuration mode is determined according to the target working frequency band of the analog circuit and the working clock frequency point of the digital circuit, the high-frequency clock signal is converted into the working clock of the digital circuit according to the duty ratio configuration mode and the working clock frequency point of the digital circuit, and the energy of the harmonic wave of the working clock falling into the sensitive frequency band is reduced by controlling the duty ratio of the working clock of the digital circuit, so that the interference of the higher harmonic wave of the working clock of the digital circuit is inhibited.
Referring to fig. 10, fig. 10 is a method for suppressing higher harmonic interference of a digital clock according to an embodiment of the present invention, where the method includes:
step S101, generating a high-frequency clock signal through a digital phase-locked loop;
it is understood that if the high frequency clock signal is generated by a digital phase locked loop, it is understood by those skilled in the art and will not be described herein.
Step S102, determining a duty ratio configuration mode according to a target working frequency band of the analog circuit and a working clock frequency point of the digital circuit;
the duty ratio configuration mode comprises an equal duty ratio configuration mode and a non-equal duty ratio configuration mode, and if odd harmonics of a working clock frequency point of the digital circuit are in a target working frequency band of the analog circuit, the non-equal duty ratio configuration mode is selected; and if the even harmonic of the working clock frequency point of the digital circuit is in the target working frequency band of the analog circuit, selecting the equal duty ratio configuration mode.
If the analog circuit only has one working frequency band, the working frequency band is taken as the target working frequency band;
if the analog circuit comprises at least two working frequency bands, detecting the times of harmonic waves of working clock frequency points of the digital circuit in the working frequency bands of the analog circuit, if the parity of the detected times of the harmonic waves is the same, if the detected times of the harmonic waves are all even harmonic waves or all odd harmonic waves, then any of the operating frequency bands of the analog circuit is taken as the target operating frequency band, assuming, the working clock frequency point of the digital circuit is 245.76MHz, the analog circuit comprises two working frequency bands of 1710-1785 MHz and 3600-3800 MHz respectively, the 7 th harmonic of 245.76MHz is 1720.32MHz and is positioned in the 1710-1785 MHz frequency band, the 15 th harmonic of 245.76MHz is 3686.4MHz and is positioned in the 3600-3800 MHz frequency band, the times of the 7 th harmonic and the 15 th harmonic are odd harmonics, therefore, an operating frequency band can be selected from the two operating frequency bands as the target operating frequency band;
if the parity of the detected times of the harmonic is different, such as one is odd harmonic and the other is even harmonic, the energy of each harmonic in the working frequency band of the analog circuit can be further detected, the working frequency band of the analog circuit corresponding to the detected harmonic with the largest energy is taken as the target working frequency band, assuming that the working clock frequency point of the digital circuit is 245.76MHz, the analog circuit comprises two working frequency bands, which are 1710-1785 MHz and 1920-1980 MHz respectively, the 7 th harmonic of 245.76MHz is 1720.32MHz and is in 1710-1785 MHz, the 8 th harmonic of 245.76MHz is 1966.08MHz and is in 1920-1980 frequency band, and the larger the parity of the detected times of the harmonic is, the larger the energy of the 7 th harmonic of 245.76MHz and the energy of the 8 th harmonic are, the larger the influence of the energy on the analog circuit is, so that the working frequency band of the analog circuit corresponding to the harmonic with the largest detected energy is taken as the target working frequency band And assuming that the energy of the 7 th harmonic is greater than the energy of the 8 th harmonic, 1710-1785 MHz is used as the target working frequency band of the analog circuit.
Step S103, converting the high-frequency clock signal into a working clock of the digital circuit according to the duty ratio configuration mode and the working clock frequency point of the digital circuit;
it can be understood that, how to convert the high-frequency clock signal into the working clock of the digital circuit according to the duty cycle configuration mode and the working clock frequency point of the digital circuit may refer to the related description of the digital clock generating circuit 42 in the embodiment described in fig. 4, and details are not repeated here.
It should be noted that, in the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and reference may be made to relevant descriptions of other embodiments for parts that are not described in detail in a certain embodiment. Further, those skilled in the art should also appreciate that the embodiments described in the specification are preferred embodiments and that acts and modules referred to are not necessarily required to practice embodiments of the invention.
The steps in the method of the embodiment of the invention can be sequentially adjusted, combined and deleted according to actual needs.
It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above can be implemented by a computer program, which can be stored in a computer-readable storage medium, and when executed, can include the processes of the embodiments of the methods described above. The storage medium may be a magnetic disk, an optical disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), or the like.
The above disclosure is only for the purpose of illustrating the preferred embodiments of the present invention, and it is therefore to be understood that the invention is not limited by the scope of the appended claims.
Claims (9)
1. A circuit for suppressing higher harmonic interference of a digital clock, comprising:
a digital phase-locked loop for generating a high frequency clock signal;
and the digital clock generating circuit is connected with the digital phase-locked loop and used for determining a duty ratio configuration mode according to a target working frequency band of the analog circuit and a working clock frequency point of the digital circuit and converting the high-frequency clock signal into a working clock of the digital circuit according to the duty ratio configuration mode and the working clock frequency point of the digital circuit.
2. The circuit of claim 1, wherein the duty cycle configuration modes include a constant duty cycle configuration mode and a non-constant duty cycle configuration mode;
the digital clock generation circuit is specifically configured to:
if the odd harmonic of the working clock frequency point of the digital circuit is in the target working frequency band of the analog circuit, selecting the unequal duty ratio configuration mode;
and if the even harmonic of the working clock frequency point of the digital circuit is in the target working frequency band of the analog circuit, selecting the equal duty ratio configuration mode.
3. The circuit of claim 1, wherein the digital clock generation circuit comprises a counter, a duty cycle mode register, a selector, an equal comparator, a greater than or equal to comparator, and an output register, the duty cycle mode register storing a first configuration value corresponding to an equal duty cycle mode, a second configuration value corresponding to a non-equal duty cycle mode, and a division factor high bit, wherein:
the control end of the selector is connected with the output end of the duty ratio mode register, the first input end of the selector is accessed to the first configuration value, the second input end of the selector is accessed to the second configuration value, the output end of the selector is connected with the first input end of the equal comparator, the second input end of the equal comparator is connected with the output end of the counter, the output end of the equal comparator is connected with the zero clearing end of the output register,
the first input end of the comparator is connected with the output end of the counter, the second input end of the comparator is connected with the high-order frequency division coefficient, the output end of the comparator is respectively connected with the zero clearing end of the counter and the setting end of the output register,
the input end of the counter and the input end of the output register are connected with a high-frequency clock signal generated by the digital phase-locked loop, and the output end of the output register outputs a working clock of the digital circuit.
4. The circuit of claim 3,
if the odd harmonic of the working clock frequency point of the digital circuit is in the target working frequency band of the analog circuit, the selector controls the output end to output the second configuration value, so that the duty ratio of the output working clock is not equal to 50%;
if the even harmonic of the working clock frequency point of the digital circuit is within the target working frequency band of the analog circuit, the selector controls the output end to output the first configuration value, so that the duty ratio of the output working clock is equal to 50%.
5. The circuit of claim 3,
when the count value of the counter is equal to the output value of the selector, the equal comparator clears the output register;
and when the count value of the counter is greater than or equal to the high bit of the frequency division coefficient, the greater than or equal to comparator sets the output register and clears the counter.
6. A method of suppressing higher harmonic interference of a digital clock, comprising:
generating a high-frequency clock signal through a digital phase-locked loop;
determining a duty ratio configuration mode according to a target working frequency band of the analog circuit and a working clock frequency point of the digital circuit;
and converting the high-frequency clock signal into a working clock of the digital circuit according to the duty ratio configuration mode and the working clock frequency point of the digital circuit.
7. The method of claim 6, wherein the duty cycle configuration modes comprise a constant duty cycle configuration mode and a non-constant duty cycle configuration mode;
the determining the duty ratio configuration mode according to the target working frequency band of the analog circuit and the working clock frequency point of the digital circuit comprises the following steps:
if the odd harmonic of the working clock frequency point of the digital circuit is in the target working frequency band of the analog circuit, selecting the unequal duty ratio configuration mode;
and if the even harmonic of the working clock frequency point of the digital circuit is in the target working frequency band of the analog circuit, selecting the equal duty ratio configuration mode.
8. The method of any of claims 6-7, wherein the analog circuitry includes at least two operating frequency bands;
before determining the duty ratio configuration mode according to the target working frequency band of the analog circuit and the working clock frequency point of the digital circuit, the method further comprises:
detecting the frequency of harmonic waves of a working clock frequency point of the digital circuit in a working frequency band of the analog circuit;
and if the parity of the detected times of the harmonic waves is the same, taking any working frequency band of the analog circuit as the target working frequency band.
9. The method of claim 8, wherein if the parity of the number of times the harmonic is detected is different, the method further comprises:
detecting the energy of each of the harmonics within the operating frequency band of the analog circuit;
and taking the working frequency band of the analog circuit corresponding to the detected harmonic wave with the maximum energy as the target working frequency band.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
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