CN103414452B - Clock data recovery device and electronic equipment - Google Patents
Clock data recovery device and electronic equipment Download PDFInfo
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- CN103414452B CN103414452B CN201310312229.4A CN201310312229A CN103414452B CN 103414452 B CN103414452 B CN 103414452B CN 201310312229 A CN201310312229 A CN 201310312229A CN 103414452 B CN103414452 B CN 103414452B
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Abstract
The embodiment of the invention discloses a kind of clock data recovery device and be provided with the electronic equipment of this clock data recovery device, belonging to communication technical field.Solve existing clock and data recovery module and there is the technical problem that output jitter is bigger.This clock data recovery device, including clock data recovery unit, numerical control oscillating unit and FIFO unit；Clock data recovery unit, for data input signal being carried out clock and data recovery by the first input clock signal, generates just step clock signal and preliminary data signal；Numerical control oscillating unit is for dividing the second input clock signal with certain divide ratio, generate and send recovered clock signal to outside, also first step clock signal is compared with recovered clock signal, if just step clock signal is advanced or lags behind recovered clock signal, then divide ratio is subtracted 1 accordingly or add 1.The present invention is applied to the process of transceiving data in electronic equipment.
Description
Technical field
The invention belongs to communication technical field, when being specifically related to a kind of clock data recovery device and be provided with this
The electronic equipment of clock Data Recapture Unit.
Background technology
Along with the development of electronic technology, the frame format clock interface of E1 or T1 agreement is the most extensively applied
In various electronic equipments, clock and data recovery module (Clock and Data Recovery, CDR) is it
In an important component part.Existing CDR module has good work under conditions of input non-jitter
Make performance, but when shake occurs in input, the outer time recovered also there will be shake.
As it is shown in figure 1, as a example by the external clock of E1 agreement, existing CDR module mainly includes detection electricity
Road, clock synchronization circuit and data sampling circuit, external clock signal clk1 is 32.768MHz, external data
The frequency of input signal is 2MHz.As outside positive polarity and data input signal rpi, rni of negative polarity and
When detection signal alose inputs CDR, testing circuit 11 is used for receiving and detecting rpi, rni, when detecting
During the rising edge of data input signal, just one synchronization pulse sync of output.In clock synchronization circuit 12
Typically one state machine with 16 states of critical piece, redirect with the frequency cycle of 32.768MHz,
When receiving the sync that testing circuit 11 sends, jump to original state, then when jumping to 9 state,
The rising edge of output recovered clock signal clk_ex.Data sampling circuit 13 generally can use d type flip flop, uses
In recovery data signal rpo according to clk_ex output cathode and negative polarity, rno, namely by rpi and rni
Rpo and rno is exported after being synchronized to the clock zone of clk_ex.
The present inventor finds during realizing the present invention, prior art at least there is problems in that because
Receive after sync jumps to original state at clock synchronization circuit 12, when jumping to 9 state, output
The rising edge of clk_ex, so the rising edge of clk_ex postpones the cycle of 8 32.786MHz all the time than sync,
But when shake occurs in data input signal, the recovered clock signal of output also can produce trembling of formed objects
Dynamic, therefore there is the technical problem that output jitter is bigger.
Summary of the invention
Embodiments provide a kind of clock data recovery device and be provided with this clock data recovery device
Electronic equipment, solve existing clock and data recovery module and there is the technical problem that output jitter is bigger.
For reaching above-mentioned purpose, embodiments of the invention adopt the following technical scheme that
On the one hand, it is provided that a kind of clock data recovery device, shake including clock data recovery unit, numerical control
Swing unit and FIFO unit；
First input clock signal outside clock signal input terminal reception of described clock data recovery unit,
The data input signal outside data signal input reception of described clock data recovery unit, described clock
The clock signal output terminal of data recovery unit connects the first input end of numerical control oscillating unit and described first enters elder generation
Going out the first clock signal input terminal of unit, the data signal output of described clock data recovery unit connects
The data signal input of described FIFO unit；
Second input clock signal outside second input reception of described numerical control oscillating unit, described numerical control
The outfan of oscillating unit connects the second clock signal input part of described FIFO unit and sends to outside
Recovered clock signal；
The data signal output of described FIFO unit sends to outside and recovers data signal；
Described clock data recovery unit is for believing the input of described data by described first input clock signal
Number carry out clock and data recovery, generate just step clock signal and preliminary data signal, and vibrate to described numerical control
Unit and the described just step clock signal of described FIFO unit output, export institute to described FIFO unit
Stating preliminary data signal, wherein, the frequency of described first input clock signal is described just step clock signal
N times of frequency, n is the integer of more than 2；
Described numerical control oscillating unit is for carrying out described second input clock signal point with certain divide ratio
Frequently, generate and send to outside recovered clock signal, also by described just step clock signal and described recovered clock
Signal compares, if described just step clock signal is ahead of described recovered clock signal, then by described point
Frequently coefficient subtracts 1, if described just step clock signal lags behind described recovered clock signal, then by described frequency dividing system
Number adds 1, and wherein, described just step clock signal is equal with the frequency of described recovered clock signal, described second defeated
Enter that the frequency of clock signal is the frequency of described first input clock signal m times, m is the integer of more than 2；
Described FIFO unit is used for receiving described preliminary data signal according to described just step clock signal, and
According to described recovered clock signal to the described recovery data signal of outside transmission.
In the implementation that the first is possible, described numerical control oscillating unit include frequency divider, the first enumerator,
Second enumerator and comparator；
Described frequency divider is for dividing described second input clock signal with certain divide ratio, raw
Cheng Bingxiang is outside sends recovered clock signal；
Described first enumerator is for recording the number of pulses of described just step clock signal；
Described second enumerator is for recording the number of pulses of described recovered clock signal；
Described comparator within each unit interval to described first enumerator and described second enumerator
Count results compares, and regulates the divide ratio in described frequency divider according to comparative result, if described
Described divide ratio more than the count results of described second enumerator, is then subtracted by the count results of the first enumerator
1, if the count results of described first enumerator is less than the count results of described second enumerator, then by described
Divide ratio adds 1.
In conjunction with the implementation that the first is possible, in the implementation that the second is possible, described clock data
Recovery unit includes testing circuit, clock synchronization circuit and data sampling circuit；
Described testing circuit is used for detecting described data input signal, when described data input signal being detected
During rising edge, export a synchronization pulse；
Described clock synchronization circuit, for the frequency with described first input clock signal, follows in n state
Huantiao turns, and when receiving described synchronization pulse, jumps to the original state in described n state,
When the i-th state jumped in described n state, export the rising edge of described just step clock signal, its
In, 1 ＜ i ＜ n；
Described data sampling circuit is for exporting described preliminary data signal according to described just step clock signal.
In conjunction with the implementation that the second is possible, in the implementation that the third is possible, described first input
The frequency of clock signal is 32.768MHz, n=16, i=9.
In conjunction with any one possible implementation above-mentioned, in the 4th kind of possible implementation, described
The frequency of two input clock signals is 131.072MHz, and the initial value of described divide ratio is 64.
On the other hand, additionally provide a kind of electronic equipment, including R-T unit and any of the above-described a kind of realization side
Clock data recovery device described in formula, described clock data recovery device is for the data received and send
Carry out clock and data recovery.
Compared with prior art, technique scheme provided by the present invention has the advantage that numerical control is vibrated
Second input clock signal is divided by unit with certain divide ratio, generates and first step clock signal frequency
The recovered clock signal that rate is equal, and first step clock signal is compared with recovered clock signal, work as number
When advanced or delayed shake occurring according to input signal, the first step clock signal of clock data recovery unit output
Also there will be the shake of formed objects, now divide ratio is carried out subtracting 1 or adding 1 by numerical control oscillating unit accordingly
Adjust, be equivalent to the recovered clock signal of output has been reduced or increased the week of one the second input clock signal
Phase.Because the frequency of the second input clock signal is m times of the frequency of the first input clock signal, first is defeated
Enter that the frequency of clock signal is the frequency of just step clock signal n times, so the frequency of the second input clock signal
Rate is m × n times of the frequency of just step clock signal (data input signal), then adjust institute after divide ratio
Shake size on the recovered clock signal of output is only the cycle of second input clock signal, is data
M × n/mono-of the shake size of input signal, thus enter data into by the way of regulation divide ratio
Shake bigger on signal is shared in multiple recovered clock signal, and therefore FIFO unit is according to this recovery
Clock signal shake in the recovery data signal that outside sends is substantially reduced, and solves existing skill
Art exists the technical problem that output jitter is bigger.
Accompanying drawing explanation
In order to be illustrated more clearly that the embodiment of the present invention or technical scheme of the prior art, below will be to enforcement
In example or description of the prior art, the required accompanying drawing used is briefly described.
Fig. 1 is the schematic diagram of existing clock and data recovery module；
The clock data recovery device that Fig. 2 is provided by embodiments of the invention schematic diagram；
The signal of numerical control oscillating unit in the clock data recovery device that Fig. 3 is provided by embodiments of the invention
Figure.
Detailed description of the invention
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clearly
Chu, complete description.
As in figure 2 it is shown, the clock data recovery device that the embodiment of the present invention is provided, extensive including clock data
Multiple unit 1(Clock and Data Recovery, CDR), numerical control oscillating unit 2(Digitally Controlled
Oscillator, DCO) and FIFO unit 3(First Input First Output, FIFO).
The first input clock signal clk1 outside clock signal input terminal reception of clock data recovery unit 1,
The data input signal outside data signal input reception of clock data recovery unit 1, these data input
Signal specifically includes two paths of data input signal rpi of positive polarity and negative polarity, rni, clock data recovery unit
The clock signal output terminal of 1 connects the first input end and the first of FIFO unit 3 of numerical control oscillating unit 2
Clock signal input terminal, the data signal output of clock data recovery unit 1 connects FIFO unit 3
Data signal input.
The second input clock signal clk2 outside second input reception of numerical control oscillating unit 2, numerical control is vibrated
The outfan of unit 2 connects the second clock signal input part of FIFO unit 3 and sends recovery to outside
Clock signal clk_ex.
The data signal output of FIFO unit 3 sends to outside and recovers data signal, these recovery data
Signal also includes that the two-way of positive polarity and negative polarity recovers data signal rpo, rno.
Clock data recovery unit 1 is for carrying out clock and data recovery by clk1 to rpi and rni, at the beginning of generation
Step clock signal clk_cdr and preliminary data signal, this preliminary data signal also includes positive polarity and negative polarity
Two-way preliminary data signal rp_cdr, rn_cdr, and clock data recovery unit 1 is also to numerical control oscillating unit
2 and FIFO unit 3 export clk_cdr, export rp_cdr and rn_cdr to FIFO unit 3.Its
In, the frequency of clk1 is n times of the frequency of clk_cdr, and n is the integer of more than 2.
Numerical control oscillating unit 2, for dividing clk2 with certain divide ratio a, generates and to outside
Send recovered clock signal clk_ex, be additionally operable to compare clk_cdr with clk_ex.If clk_cdr
It is ahead of clk_ex, then divide ratio is subtracted 1, become a-1；If clk_cdr lags behind clk_ex, then will
Divide ratio adds 1, becomes a+1.Wherein, the frequency of clk_cdr with clk_ex is equal, and the frequency of clk2 is
M times of the frequency of clk1, m is the integer of more than 2.
FIFO unit 3 is for receiving rp_cdr and rn_cdr according to clk_cdr and outside according to clk_ex
Portion sends rpo and rno, exports rpo after rp_cdr and rn_cdr is namely synchronized to the clock zone of clk_ex
And rno.
In the clock data recovery device that the embodiment of the present invention provides, numerical control oscillating unit 2 is with certain frequency dividing
Clk2 is divided by coefficient a, generates the clk_ex equal with clk_cdr frequency, and by clk_cdr with
Clk_ex compares, and when advanced or delayed shake occur in rpi, rni, clock data recovery unit 1 is defeated
The clk_cdr gone out also there will be the shake of formed objects, and now numerical control oscillating unit 2 is corresponding by divide ratio
A carries out subtracting 1 or adding 1 adjustment, is equivalent to the clk_ex of output has been reduced or increased the cycle of one clk2.
Because the frequency of clk2 is m times of the frequency of clk1, the frequency of clk1 is n times of the frequency of clk_cdr,
So the frequency of clk2 is clk_cdr(rpi, rni) m × n times of frequency, then adjust divide ratio a it
Shake size on rear exported clk_ex is only the cycle of a clk2, is the shake size of rpi, rni
M × n/mono-, thus by regulation divide ratio a by the way of shake bigger on rpi, rni is shared
In multiple clk_ex, rpo, rno's that therefore FIFO unit 3 sends to outside according to this clk_ex
On shake be substantially reduced, solve and prior art exist the technical problem that output jitter is bigger.
As it is shown on figure 3, in the embodiment of the present invention, numerical control oscillating unit 2 specifically includes frequency divider 23, first
Enumerator the 21, second enumerator 22 and comparator 24.
Frequency divider 23, for dividing clk2 with certain divide ratio a, generates and sends to outside
clk_ex.Preferably, the frequency of clk2 is 131.072MHz, and the initial value of divide ratio a is 64, then give birth to
The frequency of the clk_ex become is about 2MHz.Certainly, also will using the frequency of clk_ex with clk_cdr equal as
Premise.
First enumerator 21 is for recording the number of pulses of clk_cdr, and the second enumerator 22 is used for recording clk_ex
Number of pulses, the first enumerator 21 and the second enumerator 22 can enter by the way of tracer signal rising edge
Row counting.
Comparator 24 is used within each unit interval the first enumerator 21 and counting of the second enumerator 22
Result compares, such as every 10 clk_cdr(clk_ex) period ratio more once, and according to comparing knot
Divide ratio in fruit regulation frequency divider 23.If the count results of the first enumerator 21 is more than the second counting
The count results of device 22, illustrates that clk_cdr occurs in that advanced shake, then subtracts 1 by divide ratio, become 63；
If the count results of the first enumerator 21 is less than the count results of the second enumerator 22, illustrate that clk_cdr goes out
Show lag jitter, then divide ratio has been added 1, become 65.
Clock data recovery unit 1 in the embodiment of the present invention can use existing clock and data recovery module,
As it is shown in figure 1, include testing circuit 11, clock synchronization circuit 12 and data sampling circuit 13.
Testing circuit 11 is used for detecting rpi and rni, when the rising edge of rpi or rni being detected, exports one
Synchronization pulse sync.
Critical piece in clock synchronization circuit 12 is typically a state machine, is used for the frequency with clk1,
Cycling jump in n state, when receiving sync, jumps to the original state in n state, works as jumping
When going to the i-th state in n state, the rising edge of output clk_cdr, wherein, 1 ＜ i ＜ n.As
One preferred version, the frequency of clk1 generally uses 32.768MHz, and described state machine has 16 shapes
State, when receiving sync, jumps to original state, when jumping to the 9th state, exports clk_cdr
Rising edge, i.e. n=16, i=9.Because the frequency of rpi and rni is 2MHz, and every 16 clk1
Cycle output one clk_cdr, so the frequency of clk_cdr is also 2MHz, equal with the frequency of clk_ex.
Additionally, because the frequency of the clk2 in the present embodiment is 131.072MHz, so the frequency of clk2 is
4 times of the frequency of clk1, i.e. m=4.Certainly, the value of m can also be replaced by the integer range of more than 2
Other numerical value.
Data sampling circuit 13 is for exporting rp_cdr and rn_cdr according to clk_cdr.
In the clock data recovery device that the embodiment of the present invention provides, numerical control oscillating unit 2 is with certain frequency dividing
The clk2 that frequency is 131.072MHz is divided by coefficient 64, and generating frequency is the clk_ex of 2MHz,
And clk_cdr with clk_ex is compared, when there is advanced or delayed shake in rpi, rni, clock
The clk_cdr of data recovery unit 1 output also there will be the shake of formed objects, now numerical control oscillating unit 2
Accordingly divide ratio is changed into 63 or 65, is equivalent to the clk_ex of output has been reduced or increased one clk2
Cycle.Because clk_cdr(rpi, rni) frequency be 2MHz, and institute is defeated after adjusting divide ratio
Shake size on the clk_ex gone out is only the cycle of a clk2, so the shake size on clk_ex is only
/ the 64 of the shake size of rpi, rni, thus by regulation divide ratio by the way of by rpi, rni relatively
Big shake is shared in multiple clk_ex, and therefore FIFO unit 3 sends to outside according to this clk_ex
The upper shake of rpo, rno be substantially reduced, solve that to there is output jitter in prior art bigger
Technical problem.
It addition, because the shake of rpi, rni seldom occurs, so generally it is used for sharing by the most multiple clk_ex
Shake on rpi, rni, for more smooth being split in clk_ex of the shake making rpi, rni, can be right
Clk_ex is grouped, using several for continuous print clk_ex as one group of signal, and only in one group of signal of regulation one
The divide ratio of clk_ex, namely shares the shake of rpi, rni in continuous print many groups signal, and often
In one group of signal, only one of which clk_ex is with shake.Often the quantity of the clk_ex that group signal includes can
It is configured according to practical situations.
The embodiment of the present invention additionally provides a kind of electronic equipment, including in R-T unit and above-described embodiment time
Clock Data Recapture Unit, described clock data recovery device is for carrying out clock number to the data received and send
According to recovery.
The clock data that the electronic equipment provided due to the embodiment of the present invention and the invention described above embodiment are provided
Recovery device has identical technical characteristic, so also can produce identical technique effect, solves identical skill
Art problem.
The above, the only detailed description of the invention of the present invention, but protection scope of the present invention is not limited to
This, any those familiar with the art, in the technical scope that the invention discloses, can readily occur in
Change or replacement, all should contain within protection scope of the present invention.Therefore, protection scope of the present invention
Should be as the criterion with scope of the claims.
Claims (6)
1. a clock data recovery device, it is characterised in that: include that clock data recovery unit, numerical control are shaken
Swing unit and FIFO unit；
First input clock signal outside clock signal input terminal reception of described clock data recovery unit,
The data input signal outside data signal input reception of described clock data recovery unit, described clock
The clock signal output terminal of data recovery unit connects the first input end of numerical control oscillating unit and described first enters elder generation
Going out the first clock signal input terminal of unit, the data signal output of described clock data recovery unit connects
The data signal input of described FIFO unit；
Second input clock signal outside second input reception of described numerical control oscillating unit, described numerical control
The outfan of oscillating unit connects the second clock signal input part of described FIFO unit and sends to outside
Recovered clock signal；
The data signal output of described FIFO unit sends to outside and recovers data signal；
Described clock data recovery unit is for believing the input of described data by described first input clock signal
Number carry out clock and data recovery, generate just step clock signal and preliminary data signal, and vibrate to described numerical control
Unit and the described just step clock signal of described FIFO unit output, export institute to described FIFO unit
Stating preliminary data signal, wherein, the frequency of described first input clock signal is described just step clock signal
N times of frequency, n is the integer of more than 2；
Described numerical control oscillating unit is for carrying out described second input clock signal point with certain divide ratio
Frequently, generate and send to outside recovered clock signal, also by described just step clock signal and described recovered clock
Signal compares, if described just step clock signal is ahead of described recovered clock signal, then by described point
Frequently coefficient subtracts 1, if described just step clock signal lags behind described recovered clock signal, then by described frequency dividing system
Number adds 1, and wherein, described just step clock signal is equal with the frequency of described recovered clock signal, described second defeated
Enter that the frequency of clock signal is the frequency of described first input clock signal m times, m is the integer of more than 2；
Described FIFO unit is used for receiving described preliminary data signal according to described just step clock signal, and
According to described recovered clock signal to the described recovery data signal of outside transmission.
Clock data recovery device the most according to claim 1, it is characterised in that: described numerical control is vibrated
Unit includes frequency divider, the first enumerator, the second enumerator and comparator；
Described frequency divider is for dividing described second input clock signal with certain divide ratio, raw
Cheng Bingxiang is outside sends recovered clock signal；
Described first enumerator is for recording the number of pulses of described just step clock signal；
Described second enumerator is for recording the number of pulses of described recovered clock signal；
Described comparator within each unit interval to described first enumerator and described second enumerator
Count results compares, and regulates the divide ratio in described frequency divider according to comparative result, if described
Described divide ratio more than the count results of described second enumerator, is then subtracted by the count results of the first enumerator
1, if the count results of described first enumerator is less than the count results of described second enumerator, then by described
Divide ratio adds 1.
Clock data recovery device the most according to claim 1, it is characterised in that: described clock data
Recovery unit includes testing circuit, clock synchronization circuit and data sampling circuit；
Described testing circuit is used for detecting described data input signal, when described data input signal being detected
During rising edge, export a synchronization pulse；
Described clock synchronization circuit, for the frequency with described first input clock signal, follows in n state
Huantiao turns, and when receiving described synchronization pulse, jumps to the original state in described n state,
When the i-th state jumped in described n state, export the rising edge of described just step clock signal, its
In, described n be the frequency of described first input clock signal be the multiple of the frequency of described just step clock signal,
1 ＜ i ＜ n；
Described data sampling circuit is for exporting described preliminary data signal according to described just step clock signal.
Clock data recovery device the most according to claim 3, it is characterised in that: described first input
The frequency of clock signal is 32.768MHz, n=16, i=9.
5. according to the clock data recovery device described in any one of Claims 1-4, it is characterised in that: institute
The frequency stating the second input clock signal is 131.072MHz, and the initial value of described divide ratio is 64.
6. an electronic equipment, it is characterised in that: include R-T unit and any one of claim 1 to 5 institute
The clock data recovery device stated, described clock data recovery device is for carrying out the data received and send
Clock and data recovery.
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| CN201310312229.4A CN103414452B (en) | 2013-07-23 | 2013-07-23 | Clock data recovery device and electronic equipment |
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| CN106533433A (en) * | 2015-09-09 | 2017-03-22 | 晨星半导体股份有限公司 | Clock pulse data replying device, clock pulse data replying method and phase detector |
| CN106656168B (en) * | 2016-12-30 | 2020-09-04 | 北京集创北方科技股份有限公司 | Clock data recovery device and method |
| CN112491528A (en) * | 2020-11-20 | 2021-03-12 | 武汉光迅信息技术有限公司 | Method and device for synchronous recovery of communication clock |
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| US7512203B2 (en) * | 2005-03-30 | 2009-03-31 | Silicon Laboratories Inc. | Data cleaning with an asynchronous reference clock |
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| US5982833A (en) * | 1993-08-27 | 1999-11-09 | Vlsi Technology, Inc. | Method and apparatus for attenuating jitter in a digital transmission line |
| US7127022B1 (en) * | 2003-03-21 | 2006-10-24 | Xilinx, Inc. | Clock and data recovery circuits utilizing digital delay lines and digitally controlled oscillators |
| CN1540911A (en) * | 2003-04-25 | 2004-10-27 | 中兴通讯股份有限公司 | Circuit for recovering timing data and implementing method |
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