CN105337591A - Circuit structure and method for realizing clock recovery on the basis of USB device - Google Patents
Circuit structure and method for realizing clock recovery on the basis of USB device Download PDFInfo
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Abstract
The invention relates to a circuit structure and method for realizing clock recovery on the basis of a USB device. The circuit structure comprises a built-in oscillator module for generating oscillation signals; and a digital control logic module which includes a USB clock recovery unit for sampling the oscillation signals of the built-in oscillator and performing the clock recovery and a frequency adjustment unit for adjusting the oscillation frequency of the built-in oscillator according to a comparison result between USB signals and the oscillation signals of the built-in oscillator. By using the circuit structure and method for realizing the clock recovery on the basis of the USB device through such a structure, an accurate system clock can be generated, a frequency tracking feature is exhibited, a USB data transmission frequency is compared with the frequency of the built-in oscillator through adoption of the digital control logic module, the frequency of the built-in oscillator is automatically switched among a low-speed state, a medium-speed state and a high-speed state, the system precision and the stability are guaranteed, the production cost is decreased, and the application scope is wider.
Description
Technical field
The present invention relates to clock recovery field, particularly relate to USB device clock recovery field, specifically refer to a kind of circuit structure and the method that realize clock recovery based on USB device.
Background technology
Prior art mostly is following solution:
(1) circuit external crystal oscillator is adopted to provide accurate clock for circuit;
(2) adopt phase-locked loop pll design, produce the clock signal consistent with serial data frequency and phase place;
(3) adopt delay lock loop DLL design, produce the clock signal consistent with serial data frequency and phase place.
Shortcoming with upper type:
(1) external crystal oscillator, peripheral relative complex, error is comparatively large, and adds cost;
(2) phase-locked loop pll design makes circuit area relatively large, and design overall difficulty is comparatively large, and locking time is longer, to noise-sensitive, there is the problems such as the difference accumulation of error;
(3) delay lock loop DLL designs jitter suppression poor performance, and lock-in range is relatively limited, and power consumption is comparatively large, does not have frequency tracking characteristic.
Summary of the invention
The object of the invention is the shortcoming overcoming above-mentioned prior art, provide and a kind ofly can realize producing accurate system clock, there is frequency tracking characteristic, automatically by the frequency of built-in oscillator in low speed, middling speed with carry out changing, taking into account the precision and stability of system between three states at a high speed, there is the circuit structure and the method that realize clock recovery based on USB device of broader applications scope.
To achieve these goals, the circuit structure realizing clock recovery based on USB device of the present invention has following formation:
Should realize the circuit structure of clock recovery based on USB device, its main feature is, described circuit structure comprises built-in oscillator and digital control logic module, and described built-in oscillator module comprises:
Electric current source generating circuit, in order to produce and to export reference current;
Current mirroring circuit, in order to produce tank circuit current by after described reference current amplification system predetermined current multiplication factor;
Oscillator, the oscillator signal be directly proportional to described tank circuit current frequency in order to generation also exports described digital control logic module to;
Described digital control logic module comprises:
USB clock recovery unit, in order to the oscillator signal of described built-in oscillator module is carried out sampling go forward side by side row clock recover;
Frequency adjustment unit, the systemic presupposition current amplification factor of the current mirroring circuit described in regulating in order to the comparative result of the oscillator signal of the USB synchronization code signal that sends according to main frame and described built-in oscillator module.
Preferably, described electric current source generating circuit comprises interconnective PTAT current source and has the tc compensation resistance of positive temperature coefficient, and described PTAT current source is in order to export reference current to described current mirroring circuit.
Preferably, described current mirroring circuit comprises the first switch, second switch, first NMOS tube, second NMOS tube, 3rd NMOS tube and the 4th NMOS tube, the first described switch is in order to only to disconnect when described frequency adjustment unit provides signal for faster, described second switch is in order to only to disconnect when described frequency adjustment unit provides reduce-speed sign, the first described switch is connected between the first described NMOS tube and the second NMOS tube, described second switch is connected between the 3rd described NMOS tube and the 4th NMOS tube, the first described NMOS tube, second NMOS tube, 3rd NMOS tube is connected with the 4th NMOS tube common gate, the reference current that the described current source circuit described in the second NMOS tube input exports, the 4th described NMOS tube exports tank circuit current to described oscillator.
Preferably, described oscillator is current-steering ring oscillator.
Preferably, described USB clock recovery unit comprises:
Main frame baud rate catching circuits, counted in order to the duration of high-frequency clock to the sample bits of USB interface synchronizing signal exported based on described current-steering ring oscillator;
Pulse counter, the input of this pulse counter is connected with the output of described built-in oscillator module;
Comparator, in order to reach a half of the count value of described main frame baud rate catching circuits when the count value of described pulse counter, exports the reseting controling end of reset signal to described pulse counter;
Clock generation circuit, the first input end of this clock generation circuit is connected with the output of described built-in oscillator module, the reset signal of the comparator output described in the second input input of this clock generation circuit.
More preferably, described frequency adjustment unit comprises:
USB synchronous code testing circuit, in order to detect the USB synchronization code signal that main frame sends;
Oscillator frequency control circuit, in order to send USB synchronization code signal at main frame systemic presupposition control bit during judge to send according to the bit wide count value of described built-in oscillator module accelerate, slow down or speed inhibit signal to described current mirroring circuit.
The invention still further relates to a kind of method being realized clock recovery by described circuit structure based on USB device, it is characterized in that, described method comprises USB clock recovery and built-in oscillator module frequency adjustment, and described USB clock recovery, is specially:
(11) oscillator signal of the USB clock recovery unit described in described built-in oscillator module carry out sampling go forward side by side row clock recover;
Described built-in oscillator module frequency adjustment, comprises the following steps:
(21) the systemic presupposition current amplification factor of the current mirroring circuit described in the comparative result of the oscillator signal of the USB synchronization code signal that the frequency adjustment unit described in sends according to main frame and described built-in oscillator module regulates;
(22) described oscillator is exported to after the reference signal amplification system predetermined current multiplication factor that described electric current source generating circuit exports according to the control signal of described frequency adjustment unit by the current mirroring circuit described in.
Preferably, described frequency adjustment unit comprises USB synchronous code testing circuit and oscillator frequency control circuit, and the systemic presupposition current amplification factor of the current mirroring circuit described in the comparative result of the oscillator signal of the USB synchronization code signal that described frequency adjustment unit sends according to main frame and described built-in oscillator module regulates comprises the following steps:
(211) the oscillator frequency control circuit described in judges the size sending the bit wide count value of the built-in oscillator module during the systemic presupposition control bit of USB synchronous code at main frame, if described bit wide count value is greater than systemic presupposition high level, then continue step (212), if described bit wide count value is less than systemic presupposition low value, then continue step (213), if described bit wide count value is between described systemic presupposition high level and systemic presupposition low value, continue step (214);
(212) the oscillator frequency control circuit described in sends reduce-speed sign to described current mirroring circuit;
(213) the oscillator frequency control circuit described in sends signal for faster to described current mirroring circuit;
(214) the oscillator frequency control circuit transmission frequency inhibit signal described in is to described current mirroring circuit.
More preferably, described current mirroring circuit comprises the first switch, second switch, first NMOS tube, second NMOS tube, 3rd NMOS tube and the 4th NMOS tube, the first described switch is connected between the first described NMOS tube and the second NMOS tube, described second switch is connected between the 3rd described NMOS tube and the 4th NMOS tube, the first described NMOS tube, second NMOS tube, 3rd NMOS tube is connected with the 4th NMOS tube common gate, the reference current that the described current source circuit described in the second NMOS tube input exports, the 4th described NMOS tube exports tank circuit current to described oscillator, the reference signal amplification system predetermined current multiplication factor that described electric current source generating circuit exports according to the control signal of described frequency adjustment unit by described current mirroring circuit, comprise the following steps:
(221) the control signal type of the frequency adjustment unit described in the current mirroring circuit described in judges, if signal for faster, then continue step (222), if reduce-speed sign, then continue step (223), if frequency inhibit signal, then continue step (224);
(222) the first switch described in disconnects and described second switch remains closed;
(223) the first switch described in remains closed and described second switch disconnects;
(224) the first switch described in and second switch all remain closed.
Have employed the circuit structure and the method that realize clock recovery based on USB device in this invention, there is following beneficial effect:
(1) requirement that USB device is higher to Clock Frequency Accuracy is fully met, provide a kind of clock recovery circuitry, accurate system clock can be produced, it is the low-speed USB devices system clock solution of a kind of low cost, high reliability, compared with prior art, reduce and use external crystal oscillator, simplify peripheral circuit, reduce product cost;
(2) owing to not needing loop filtering circuit, make circuit area relatively little, locking time is short, can realize clock recovery in synchronous code;
(3) there is frequency tracking characteristic, adopt digital control logic module, by comparing the frequency of USB data transmission frequency and built-in oscillator, automatically the frequency of built-in oscillator in low speed, middling speed with change between 3 states at a high speed, take into account the precision and stability of system, there is range of application widely.
Accompanying drawing explanation
Fig. 1 is the structural representation realizing the circuit structure of clock recovery based on USB device of the present invention.
Fig. 2 is the structural representation of built-in oscillator module of the present invention.
Fig. 3 is the structural representation of electric current source generating circuit of the present invention.
Fig. 4 is the structural representation of current mirroring circuit of the present invention.
Fig. 5 is the structural representation of current-steering ring oscillator of the present invention.
Fig. 6 is the electrical block diagram of Digital Logic control module of the present invention.
Fig. 7 is the sequential chart that clock generation circuit of the present invention produces.
Embodiment
In order to more clearly describe technology contents of the present invention, conduct further description below in conjunction with specific embodiment.
The present invention primarily of built-in oscillator module and digital control logic module composition, as shown in Figure 1.
Built-in oscillator module for generation of an oscillator signal far above 1.5MHz, as the clock signal of digital control logic module;
First digital control logic module for the 4th, 5 two clock signal samples that (sample bits) duration produces with built-in oscillator module to USB interface synchronizing signal, completes clock recovery; Secondly digital control logic module is also by comparing the frequency of USB data transmission frequency and built-in oscillator, automatically the frequency of built-in oscillator in low speed, middling speed with change between 3 states at a high speed.
Built-in oscillation module is made up of electric current source generating circuit, current mirroring circuit and current-steering ring oscillator three part, as shown in Figure 2.Electric current source generating circuit produces constant reference current source output (Iref); Current mirroring circuit produces tank circuit current (Iosc, Iosc=n × Iref) after reference current is amplified n times, and multiplication constant n is by accelerating, slowing down two signal controlling.
Current source is a PTAT (Proportionaltoabsolutetemperature, absolute temperature) current source, as shown in Figure 3, in order to overcome positive temperature coefficient, have selected the resistance with positive temperature coefficient during circuit design and carry out tc compensation, after compensation, this current source embodies less temperature coefficient, when temperature rises to the process of 120 DEG C from-40 DEG C, the electric current I ref produced fluctuates between 10.8 μ A ~ 12 μ A, changes less than 10%.
Current mirroring circuit structure as shown in Figure 4, to be amplified after certain multiple through current mirror with reference to electric current I ref and is produced output current Iosc, and " acceleration " and " deceleration " that multiplication factor is produced by digital circuit two control signals determine.After circuit reset, " acceleration " and " deceleration " is all invalid, switch S 0 (the first switch) and S1 (second switch) all closed, N0 (the first NMOS tube) and N1 (the second NMOS tube) is in parallel, and N2 (the 3rd NMOS tube) and N3 (the 4th NMOS tube) is in parallel; When control signal " acceleration " is effective, S0 disconnects, and Iref all flows through N1, and the grid voltage of N1 raises, and output current raises, and oscillator frequency also raises; When control signal " deceleration " is effective, S1 disconnects, and do not have electric current between N2 source and drain, Iosc electric current diminishes, and oscillator frequency reduces.
The structure of current-steering ring oscillator as shown in Figure 5.The power supply of figure ring oscillator is provided by inside circuit voltage stabilizing circuit, there is provided operating current to after input current Iosc mirror image inverter at different levels, operating current is large, the time of delay of inverter is just little, otherwise operating current is little, the time of delay of inverter is just large, so the output frequency of this oscillator is proportional to input current Iosc, the value of Iosc is regulated to regulate frequency of oscillation.Oscillation output signal is as the clock signal of digital control logic module.
Digital control logic modular structure as shown in Figure 6, first synchronous code 0000_0001 is sent during each main frame initiating communication, after USB synchronous code testing circuit detects synchronous code, during the synchronous code the 2nd (systemic presupposition control bit) that main frame sends, clock recovery circuitry IRC frequency counts bit wide, if count value is less than 42, IRC is set to low speed, now IRC frequency of oscillation is less than 63MHz, and frequency control circuit sends signal for faster; If count value is greater than 51, IRC is set at a high speed, and now IRC frequency of oscillation is greater than 76MHz, and frequency control circuit sends reduce-speed sign; If count value keeps middling speed between 42 and 51, IRC, now IRC frequency of oscillation is between 63MHz to 76MHz.
The high-frequency clock that main frame baud rate catching circuits oscillator exports counted the duration of the 4th and the 5th, and count value is exactly the multiple of built-in oscillator vibrates frequency and 1/2 main frame baud rate.This count value is removed two and is input to comparator circuit.When the count value of pulse counter reaches 1/2 of main frame baud rate catching circuits output valve, comparator exports reset enable signal pulse counter and resets, so the reset rate of pulse counter is identical with main frame frequency, ensure that the precision sending data baud rate;
6MHzUSB module clock produces principle as shown in Figure 7.Counter is 6 digit counters, and maximum count value is 64 (0x3F).The reset pulse of 1.5MHz resets to this counter.When count value is 0x4,0xD, 0x16 and 0x1F, SYSCK (system clock)) become high level, when count value is 0x8,0x11,0x1A and 0x23, SYSCK becomes low level, is equivalent to the clock of 1.5MHz to carry out 4 frequencys multiplication.In figure, frequency division value is exactly 1/2 of main frame baud rate catching circuits seizure value.The frequency of the output reset pulse of comparator is 1.5MHz, and therefore between twice this counter of 6 is reset, 4 high level pulses appear in SYSCK signal altogether, namely the frequency of SYSCK is 4 times of reset signal, is the signal of a 6MHz.
As from the foregoing, the method realizing clock recovery of the present invention mainly comprises USB clock recovery and built-in oscillator module frequency adjustment, and wherein built-in oscillator module frequency adjustment comprises the following steps:
(21) the systemic presupposition current amplification factor of the current mirroring circuit described in the comparative result of the oscillator signal of the USB synchronization code signal that the frequency adjustment unit described in sends according to main frame and described built-in oscillator module regulates;
(211) the oscillator frequency control circuit described in judges the size sending the bit wide count value of the built-in oscillator module during the systemic presupposition control bit of USB synchronous code at main frame, if described bit wide count value is greater than systemic presupposition high level, then continue step (212), if described bit wide count value is less than systemic presupposition low value, then continue step (213), if described bit wide count value is between described systemic presupposition high level and systemic presupposition low value, continue step (214);
(212) the oscillator frequency control circuit described in sends reduce-speed sign to described current mirroring circuit;
(213) the oscillator frequency control circuit described in sends signal for faster to described current mirroring circuit;
(214) the oscillator frequency control circuit transmission frequency inhibit signal described in is to described current mirroring circuit.
(22) described oscillator is exported to after the reference signal amplification system predetermined current multiplication factor that described electric current source generating circuit exports according to the control signal of described frequency adjustment unit by the current mirroring circuit described in.
(221) the control signal type of the frequency adjustment unit described in the current mirroring circuit described in judges, if signal for faster, then continue step (222), if reduce-speed sign, then continue step (223), if frequency inhibit signal, then continue step (224);
(222) the first switch described in disconnects and described second switch remains closed;
(223) the first switch described in remains closed and described second switch disconnects;
(224) the first switch described in and second switch all remain closed.
Have employed the circuit structure and the method that realize clock recovery based on USB device in this invention, there is following beneficial effect:
(1) requirement that USB device is higher to Clock Frequency Accuracy is fully met, provide a kind of clock recovery circuitry, accurate system clock can be produced, it is the low-speed USB devices system clock solution of a kind of low cost, high reliability, compared with prior art, reduce and use external crystal oscillator, simplify peripheral circuit, reduce product cost;
(2) owing to not needing loop filtering circuit, make circuit area relatively little, locking time is short, can realize clock recovery in synchronous code;
(3) there is frequency tracking characteristic, adopt digital control logic module, by comparing the frequency of USB data transmission frequency and built-in oscillator, automatically the frequency of built-in oscillator in low speed, middling speed with change between 3 states at a high speed, take into account the precision and stability of system, there is range of application widely.
In this description, the present invention is described with reference to its specific embodiment.But, still can make various amendment and conversion obviously and not deviate from the spirit and scope of the present invention.Therefore, specification and accompanying drawing are regarded in an illustrative, rather than a restrictive.
Claims (9)
1. realize a circuit structure for clock recovery based on USB device, it is characterized in that, described circuit structure comprises built-in oscillator and digital control logic module, and described built-in oscillator module comprises:
Electric current source generating circuit, in order to produce and to export reference current;
Current mirroring circuit, in order to produce tank circuit current by after described reference current amplification system predetermined current multiplication factor;
Oscillator, the oscillator signal be directly proportional to described tank circuit current frequency in order to generation also exports described digital control logic module to;
Described digital control logic module comprises:
USB clock recovery unit, in order to the oscillator signal of described built-in oscillator module is carried out sampling go forward side by side row clock recover;
Frequency adjustment unit, the systemic presupposition current amplification factor of the current mirroring circuit described in regulating in order to the comparative result of the oscillator signal of the USB synchronization code signal that sends according to main frame and described built-in oscillator module.
2. the circuit structure realizing clock recovery based on USB device according to claim 1, it is characterized in that, described electric current source generating circuit comprises interconnective PTAT current source and has the tc compensation resistance of positive temperature coefficient, and described PTAT current source is in order to export reference current to described current mirroring circuit.
3. the circuit structure realizing clock recovery based on USB device according to claim 1, it is characterized in that, described current mirroring circuit comprises the first switch, second switch, first NMOS tube, second NMOS tube, 3rd NMOS tube and the 4th NMOS tube, the first described switch is in order to only to disconnect when described frequency adjustment unit provides signal for faster, described second switch is in order to only to disconnect when described frequency adjustment unit provides reduce-speed sign, the first described switch is connected between the first described NMOS tube and the second NMOS tube, described second switch is connected between the 3rd described NMOS tube and the 4th NMOS tube, the first described NMOS tube, second NMOS tube, 3rd NMOS tube is connected with the 4th NMOS tube common gate, the reference current that the described current source circuit described in the second NMOS tube input exports, the 4th described NMOS tube exports tank circuit current to described oscillator.
4. the circuit structure realizing clock recovery based on USB device according to claim 1, is characterized in that, described oscillator is current-steering ring oscillator.
5. the circuit structure realizing clock recovery based on USB device according to claim 1, is characterized in that, described USB clock recovery unit comprises:
Main frame baud rate catching circuits, counted in order to the duration of high-frequency clock to the sample bits of USB interface synchronizing signal exported based on described current-steering ring oscillator;
Pulse counter, the input of this pulse counter is connected with the output of described built-in oscillator module;
Comparator, in order to reach a half of the count value of described main frame baud rate catching circuits when the count value of described pulse counter, exports the reseting controling end of reset signal to described pulse counter;
Clock generation circuit, the first input end of this clock generation circuit is connected with the output of described built-in oscillator module, the reset signal of the comparator output described in the second input input of this clock generation circuit.
6. the circuit structure realizing clock recovery based on USB device according to claim 5, is characterized in that, described frequency adjustment unit comprises:
USB synchronous code testing circuit, in order to detect the USB synchronization code signal that main frame sends;
Oscillator frequency control circuit, in order to send USB synchronization code signal at main frame systemic presupposition control bit during judge to send according to the bit wide count value of described built-in oscillator module accelerate, slow down or speed inhibit signal to described current mirroring circuit.
7. realized a method for clock recovery by circuit structure according to claim 1 based on USB device, it is characterized in that, described method comprises USB clock recovery and built-in oscillator module frequency adjustment, and described USB clock recovery, is specially:
(11) oscillator signal of the USB clock recovery unit described in described built-in oscillator module carry out sampling go forward side by side row clock recover;
Described built-in oscillator module frequency adjustment, comprises the following steps:
(21) the systemic presupposition current amplification factor of the current mirroring circuit described in the comparative result of the oscillator signal of the USB synchronization code signal that the frequency adjustment unit described in sends according to main frame and described built-in oscillator module regulates;
(22) described oscillator is exported to after the reference signal amplification system predetermined current multiplication factor that described electric current source generating circuit exports according to the control signal of described frequency adjustment unit by the current mirroring circuit described in.
8. the method realizing clock recovery based on USB device according to claim 7, it is characterized in that, described frequency adjustment unit comprises USB synchronous code testing circuit and oscillator frequency control circuit, and the systemic presupposition current amplification factor of the current mirroring circuit described in the comparative result of the oscillator signal of the USB synchronization code signal that described frequency adjustment unit sends according to main frame and described built-in oscillator module regulates comprises the following steps:
(211) the oscillator frequency control circuit described in judges the size sending the bit wide count value of the built-in oscillator module during the systemic presupposition control bit of USB synchronous code at main frame, if described bit wide count value is greater than systemic presupposition high level, then continue step (212), if described bit wide count value is less than systemic presupposition low value, then continue step (213), if described bit wide count value is between described systemic presupposition high level and systemic presupposition low value, continue step (214);
(212) the oscillator frequency control circuit described in sends reduce-speed sign to described current mirroring circuit;
(213) the oscillator frequency control circuit described in sends signal for faster to described current mirroring circuit;
(214) the oscillator frequency control circuit transmission frequency inhibit signal described in is to described current mirroring circuit.
9. the method realizing clock recovery based on USB device according to claim 8, it is characterized in that, described current mirroring circuit comprises the first switch, second switch, first NMOS tube, second NMOS tube, 3rd NMOS tube and the 4th NMOS tube, the first described switch is connected between the first described NMOS tube and the second NMOS tube, described second switch is connected between the 3rd described NMOS tube and the 4th NMOS tube, the first described NMOS tube, second NMOS tube, 3rd NMOS tube is connected with the 4th NMOS tube common gate, the reference current that the described current source circuit described in the second NMOS tube input exports, the 4th described NMOS tube exports tank circuit current to described oscillator, the reference signal amplification system predetermined current multiplication factor that described electric current source generating circuit exports according to the control signal of described frequency adjustment unit by described current mirroring circuit, comprise the following steps:
(221) the control signal type of the frequency adjustment unit described in the current mirroring circuit described in judges, if signal for faster, then continue step (222), if reduce-speed sign, then continue step (223), if frequency inhibit signal, then continue step (224);
(222) the first switch described in disconnects and described second switch remains closed;
(223) the first switch described in remains closed and described second switch disconnects;
(224) the first switch described in and second switch all remain closed.
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| CN201410226747.9A CN105337591B (en) | 2014-05-26 | 2014-05-26 | The circuit structure and method of clock recovery are realized based on USB device |
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| CN109450421B (en) * | 2018-12-17 | 2023-09-01 | 上海艾为电子技术股份有限公司 | Analog switch starting circuit and method |
| CN112217510A (en) * | 2019-07-09 | 2021-01-12 | 恩智浦有限公司 | High-precision dual-mode self-excited oscillator |
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| CN105337591B (en) | 2017-12-22 |
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