WO2012126420A2

WO2012126420A2 - Data and clock recovery module and data and clock recovery method

Info

Publication number: WO2012126420A2
Application number: PCT/CN2012/075299
Authority: WO
Inventors: 付生猛; 廖振兴; 余长亮
Original assignee: 华为技术有限公司
Priority date: 2012-05-10
Filing date: 2012-05-10
Publication date: 2012-09-27
Also published as: CN102859927A; WO2012126420A3; CN102859927B

Abstract

The embodiments of the present invention relate to a data and clock recovery module and a data and clock recovery method. The method includes: performing phase adjustment on a clock signal generated on the basis of the reference frequency according to a first control signal, and performing phase adjustment on a data signal according to the first control signal, wherein the phase adjustment direction of the clock signal is contrary to that of the data signal, the frequency of the clock signal is locked onto that of the data signal, and the first control signal is obtained by filtering the phase difference between the adjusted clock signal and the adjusted data signal; and sampling the adjusted data signal using the adjusted clock signal so as to obtain a data signal synchronous with the adjusted clock signal. The embodiments of the present invention reduce the synchronization time of the clock signal and the data signal, and improve the jitter performance.

Description

Data clock recovery module and data clock recovery method

The present invention relates to the field of communications technologies, and in particular, to a data clock recovery module and a data clock recovery method. BACKGROUND OF THE INVENTION Optical access has become a trend of broadband access. Passive Optical Network (PON) is the most important technology for optical access, and its deployment and research have become more and more extensive and in-depth. The PON includes an Optical Line Termination (OLT), an Optical Distribution Node (ODN), and an Optical Network Unit (ONU). Each OLT has a tree structure through an ODN and a plurality of ONUs. The forms are connected together. Because the distance between each ONU and the OLT is different, the data transmitted by each ONU arrives at different stages of the OLT. Therefore, before each ONU communicates with the OLT, it needs to synchronize with the clock of the OLT.

In the prior art, the phase of one of the data signal received by the OLT or the local clock signal of the OLT is kept unchanged, and the phase of the other signal is adjusted until the phase of the data signal and the clock signal are synchronized. However, this method makes the data signal and the clock signal arrive synchronized for a longer time. SUMMARY OF THE INVENTION Embodiments of the present invention provide a data clock recovery module and a data clock recovery method, which are implemented to reduce synchronization time between a clock signal and a data signal.

In one aspect, an embodiment of the present invention provides a data clock recovery module, including: a receiving interface, a clock unit, a first phase adjusting unit, a second phase adjusting unit, a phase detecting unit, and a synchronizer; Generating a clock signal according to a reference frequency, and inputting the clock signal to the first phase adjustment unit, the frequency of the clock signal is locked at a frequency of the data signal; the first phase adjustment unit is configured to The first control signal fed back by the phase detecting unit performs phase adjustment on the clock signal, and inputs the adjusted clock signal to the phase detecting unit and the synchronization respectively The receiving interface is configured to receive a data signal;

The second phase adjustment unit is configured to perform phase adjustment on the data signal according to the first control signal fed back by the phase detecting unit, and input the adjusted data signal to the phase detecting unit and the a synchronizer; the phase adjustment direction of the second phase adjustment unit and the first phase adjustment unit is opposite;

The phase detecting unit is configured to obtain a phase difference value between the adjusted clock signal and the adjusted data signal, and filter the phase difference value to obtain the first control signal, where the first Control signals are respectively fed back to the first phase adjustment unit and the second phase adjustment unit;

The synchronizer is configured to sample the adjusted data signal by using the adjusted clock signal to obtain a data signal synchronized with the adjusted clock signal.

In another aspect, the embodiment of the present invention further provides a data clock recovery method, including: performing phase adjustment on a clock signal generated according to a reference frequency according to a first control signal, and performing phase adjustment on the data signal according to the first control signal. And a phase adjustment direction of the clock signal is opposite to a phase adjustment direction of the data signal; a frequency of the clock signal is locked at a frequency of the data signal; and the first control signal is used by the adjusted clock signal and Obtaining a phase difference of the adjusted data signal after filtering;

And using the adjusted clock signal to sample the adjusted data signal to obtain a data signal synchronized with the adjusted clock signal.

The data clock recovery module and the data clock recovery method provided by the embodiments of the present invention adjust the phase of the phase-advanced signal back to the phase lag signal by separately adjusting the phase of the locally generated clock signal and the received data signal in opposite directions. The phase is pushed out to realize the phase synchronization of the clock signal and the data signal, and the phase adjustment of both phases can reduce the synchronization time of the clock signal and the data signal. BRIEF DESCRIPTION OF THE DRAWINGS In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings to be used in the embodiments or the description of the prior art will be briefly described below, and obviously, in the following description The drawings are only some of the embodiments of the present invention, and those skilled in the art can obtain other drawings based on these drawings without any creative work. 1 is a schematic structural diagram of an embodiment of a data clock recovery module according to the present invention; FIG. 2 is a schematic structural diagram of an embodiment of a clock unit in a data clock recovery module according to the present invention;

3 is a schematic structural diagram of still another embodiment of a data clock recovery module according to the present invention; FIG. 4 is a schematic structural diagram of still another embodiment of a clock unit in a data clock recovery module according to the present invention;

FIG. 5 is a flowchart of an embodiment of a data clock recovery method provided by the present invention. The technical solutions in the embodiments of the present invention are clearly and completely described in the following with reference to the accompanying drawings in the embodiments of the present invention. It is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. example. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative efforts are within the scope of the present invention.

1 is a schematic structural diagram of an embodiment of a data clock recovery module according to the present invention. As shown in FIG. 1, the data clock recovery module includes: a receiving interface 1, a clock unit 2, a first phase adjusting unit 3, and a second phase adjustment. Unit 4, phase detecting unit 5 and synchronizer 6;

a clock unit 2, configured to generate a clock signal according to the reference frequency, and input the clock signal to the first phase adjustment unit 3, the frequency of the clock signal is locked at the frequency of the data signal;

The first phase adjusting unit 3 is configured to perform phase adjustment on the clock signal according to the first control signal fed back by the phase detecting unit 5, and input the adjusted clock signal to the phase detecting unit 5 and the synchronizer 6 respectively;

a receiving interface 1 for receiving a data signal;

a second phase adjustment unit 4, configured to perform phase adjustment on the data signal according to the first control signal fed back by the phase detecting unit 5, and input the adjusted data signal to the phase detecting unit 5 and the synchronizer 6, respectively; The phase adjustment direction of the unit 3 and the first phase adjustment unit 4 is opposite;

The phase detecting unit 5 is configured to obtain a phase difference between the adjusted clock signal and the adjusted data signal, and filter the phase difference to obtain a first control signal, and feedback the first control signal to the first phase adjustment separately Unit 3 and second phase adjustment unit 4;

The synchronizer 6 is configured to use the adjusted clock signal to sample the adjusted data signal. A data signal synchronized with the adjusted clock signal is obtained.

The data clock recovery module (CDR) provided by the embodiment of the present invention may be disposed at the OLT end of the PON network, and used to synchronize data signals received from each ONU end of the PON network with a clock signal generated locally by the CDR. .

The CDR provided by the embodiment of the present invention is based on the principle of push-pull technology. During the phase adjustment process, the phase of the received data signal and the clock signal generated by the CDR are adjusted, and finally The phase at which synchronization is achieved is neither the original phase of the data signal nor the original phase of the clock signal, but rather an intermediate position of the original phase of both the data signal and the clock signal. It can be understood that in achieving the final phase position of synchronization, the original phase of the data signal and the clock signal, one leading, one hysteresis. Therefore, in the process of phase adjustment of the CDR, the phase of the phase leading signal in the original phase of the data signal and the clock signal is pulled back, and the phase of the phase lag signal is pushed out, that is, the data The phase adjustment of the signal and clock signals is reversed.

In the CDR provided by the embodiment of the present invention, a first phase adjustment unit 3 and a second phase adjustment unit 4 are provided, wherein the first phase adjustment unit 3 is configured to generate a clock signal to the clock unit 2. The phase adjustment is performed, and the second phase adjustment unit 4 is configured to perform phase adjustment on the received data signal. The first phase adjustment unit 3 and the second phase adjustment unit 4 can use various devices having a phase adjustment function, such as a Voltage Controlled Delay Line (VCDL).

A phase detecting unit 5 is also provided in the CDR, and the phase detecting unit 5 can use various devices having a phase detecting function, such as a phase detector (PD) or the like. The phase detecting unit 5 is configured to detect the adjusted clock signal of the first phase adjusting unit 3 and the adjusted data signal of the second phase adjusting unit 4, and obtain the phase difference between the adjusted clock signal and the adjusted data signal. The phase difference is filtered to obtain a first control signal, and the first control signal is fed back to the first phase adjustment unit 3 and the second phase adjustment unit 4, respectively. The first control signal may be a current signal or a voltage signal. That is, the first phase adjustment unit 3 and the phase detection unit 5 in the CDR, and the second phase adjustment unit 4 and the phase detection unit 5 form a feedback closed loop, a first phase adjustment unit 3, a second phase adjustment unit 4, and phase detection, respectively. The units 5 jointly form a delay locked loop unit having a push-pull function, so that the first phase adjusting unit 3 and the second phase adjusting unit 4 continuously adjust the clock signal according to the first control signal fed back by the phase detecting unit 5, respectively. And the data signal until the phase detecting unit 5 detects the phase synchronization of the clock signal and the data signal. It can be understood from the description of the principle part of the previous Push-Pull technology that the phase adjustment directions of the first phase adjustment unit 3 and the second phase adjustment unit 4 are opposite to realize synchronizing the data signal and the clock signal to the original phase and clock signal of the data signal. An intermediate phase of the original phase, and specifically which of the clock signal and the data signal is pulled back to the intermediate position, which phase of the signal is pushed to the intermediate position, depending on which of the clock signal and the data signal is ahead of the In the middle position, which signal lags behind the intermediate position. However, it is necessary to ensure that the first control signal fed back to the first phase adjustment unit 3 and the second phase adjustment unit 4 by the phase detecting unit 5 is negative feedback to ensure that the data signal and the clock signal are synchronized to the original phase of the data signal and the original phase of the clock signal. An intermediate phase.

After the phase detecting unit 5 detects that the clock signal adjusted by the first phase adjusting unit 3 is synchronized with the data signal adjusted by the second phase adjusting unit 4, the phase of the data signal received by the receiving interface 1 may change. Therefore, the phase detecting unit 5 can still detect the adjusted clock signal of the first phase adjusting unit 3 and the adjusted data signal of the second phase adjusting unit 4 in real time, and obtain the phase difference between the adjusted clock signal and the adjusted data signal. After the phase difference is filtered, the first control signal is obtained, and the first control signal is fed back to the first phase adjustment unit 3 and the second phase adjustment unit 4, respectively, so that the first phase adjustment unit 3 and the second phase adjustment unit 4 respectively The clock signal and the data signal are adjusted according to the first control signal, so that the phase of the clock signal and the data signal are adjusted in real time, and the clock signal and the data signal are synchronized.

After the phase detecting unit 5 detects that the clock signal after the phase adjustment by the first phase adjusting unit 3 is synchronized with the data signal after the phase adjustment by the second adjusting unit 4, the synchronizer 6 can adjust the adjusted clock signal pair. The data signal is sampled to obtain a data signal synchronized with the adjusted clock signal, and the data signal synchronized with the adjusted clock signal is output.

In the CDR provided by the embodiment of the present invention, the phase of the clock signal is adjusted by the first phase adjusting unit 3, and the phase of the data signal is adjusted by the second phase adjusting unit 4, so that the final phase of the clock signal is original. The phase between the phase and the original phase of the data signal is synchronized. Since the phase adjustment of the first phase adjustment unit 3 and the second phase adjustment unit 4 is synchronized, the phase amplitude of each of the first phase adjustment unit 3 and the second phase adjustment unit 4 is adjusted to adjust only the clock signal and One of the phase amplitudes of a signal in the data signal is adjusted, thus reducing the synchronization time of the clock signal and the data signal. The data clock recovery module provided in this embodiment adjusts the phase of the phase-leading signal by adjusting the phase of the locally generated clock signal and the received data signal in opposite directions, respectively. Pushing out to realize the phase synchronization of the clock signal and the data signal, and simultaneously adjusting the phases of the two can reduce the synchronization time of the clock signal and the data signal. 2 is a schematic structural diagram of an embodiment of a clock unit in a data clock recovery module according to the present invention. As shown in FIG. 2, as a possible implementation manner, the clock unit 2 in the CDR may include: a frequency locker 21 and a voltage Controlled oscillator 22;

The frequency locker 21 is configured to divide a clock signal fed back by the voltage controlled oscillator 22 according to the frequency division coefficient, obtain a frequency difference between the frequency-divided clock signal and the reference frequency, and filter the frequency difference to obtain a second control signal. The second control signal is fed back to the voltage controlled oscillator 22; wherein, the frequency division coefficient can be determined according to the frequency of the data signal; and the second control signal can be a negative feedback signal.

The voltage controlled oscillator 22 is configured to generate a clock signal, input the clock signal to the first phase adjustment unit 3 and the frequency locker 21, and to adjust the frequency of the clock signal according to the second control signal fed back by the frequency locker 21.

In this embodiment, on the basis that the first phase adjusting unit 3, the second phase adjusting unit 4, and the phase detecting unit 5 jointly form a delay locked loop unit having a push-pull function, the clock unit 2 can be replaced by the frequency locker 21. And the voltage controlled oscillator 22 is configured. After the voltage controlled oscillator 22 generates the clock signal, the clock signal can be fed back to the frequency locker 21. The frequency locker 21 can pair the voltage controlled oscillator 22 according to the frequency division coefficient determined by the frequency of the data signal. The feedback clock signal is divided to obtain a frequency difference between the divided clock signal and the reference frequency, and the frequency difference is filtered to obtain a second control signal, and the second control signal is fed back to the voltage controlled oscillator 22, thereby The voltage controlled oscillator 22 can adjust the frequency of the clock signal according to the second control signal.

It can be seen that, in this embodiment, in addition to adjusting the phase of the clock signal by the first phase adjusting unit 3, the clock signal input to the first phase adjusting unit 3 is also used by the voltage controlled oscillator 22. The frequency is adjusted to adjust the frequency of the clock signal input to the first phase adjustment unit 3.

The data clock recovery module provided by the present embodiment adjusts the phase of the locally generated clock signal and the received data signal in opposite directions by using a delay-locked loop unit with a push-pull function to implement a clock signal and a data signal. Phase synchronization, also through the voltage control vibration in the clock unit The sway adjusts the frequency of the clock signal in the input phase adjustment unit to synchronize the frequency of the clock signal with the data signal. Simultaneous adjustment of the two phases can reduce the synchronization time of d, clock signal and data signal, and improve the jitter performance of the data clock recovery module. FIG. 3 is a schematic structural diagram of another embodiment of a data clock recovery module according to the present invention. As shown in FIG. 3, on the basis of the embodiment shown in FIG. 1 , in the CDR provided by the embodiment of the present invention, the clock unit 2 can also be The phase of the clock signal is adjusted according to the first control signal fed back by the phase detecting unit 5.

In this embodiment, on the basis that the first phase adjusting unit 3, the second phase adjusting unit 4 and the phase detecting unit 5 jointly form a delay locked loop unit having a push-pull function, the phase detecting unit 5 can also be adjusted by the pair. The phase difference between the subsequent clock signal and the adjusted data signal is filtered to obtain a first control signal input to the clock unit 2, and the clock unit 2 can adjust the phase of the generated clock signal according to the first control signal. That is, the clock unit 2 can adjust the phase of the clock signal input to the first phase adjustment unit 3 in accordance with the first control signal. 4 is a schematic structural diagram of still another embodiment of a clock unit in a data clock recovery module according to the present invention. As shown in FIG. 4, on the basis of the data clock recovery module shown in FIG. 3, the clock unit 2 may include: a frequency lock. 21 and voltage controlled oscillator 22;

The frequency locker 21 is configured to divide a clock signal fed back by the voltage controlled oscillator 22 according to the frequency division coefficient, obtain a frequency difference between the frequency-divided clock signal and the reference frequency, and filter the frequency difference to obtain a second control signal. The second control signal is fed back to the voltage controlled oscillator 22; the frequency dividing coefficient is determined according to the frequency of the data signal; and the second control signal may be a negative feedback signal.

The voltage controlled oscillator 22 is configured to generate a clock signal, input the clock signal to the first phase adjusting unit 3 and the frequency locker 21; and adjust the frequency of the clock signal according to the second control signal fed back by the frequency locker 21; The phase of the clock signal is adjusted according to the first control signal fed back by the phase detecting unit 5.

The clock unit provided in this embodiment is different from the clock unit provided in the embodiment shown in FIG. 2 in that the voltage controlled oscillator 22 can adjust the frequency of the adjusted clock signal according to the second control signal generated by the frequency locker 21, It is also possible to adjust the phase of the clock signal based on the first control signal fed back by the phase detecting unit 5. Specifically, the first phase adjusting unit 3, the second phase adjusting unit 4, and the phase detecting unit 5 jointly form a delay locked loop unit having a push-pull function, and the phase detecting unit 5, the voltage controlled oscillator 22, and The first phase adjustment unit 3 together constitutes a phase locked loop function unit, in which the phase detection unit 5 feeds back the first control signal to the voltage controlled oscillator 22, thereby causing the voltage controlled oscillator 22 to be locked according to the frequency. While adjusting the frequency of the clock signal, the device 21 can also adjust the phase of the clock signal according to the first control signal.

It should be noted that, because the phase detecting unit 5, the voltage controlled oscillator 22 and the first phase adjusting unit 3 are combined to form a phase locked loop functional unit, the equivalent model of the voltage controlled oscillator 22 is an integral processing, and thus the phase locking is performed. The loop time constant of the ring functional unit is much larger than the loop time constant of the delay locked loop unit, which makes it possible to detect a large phase difference value from the phase detecting unit 5 to the data signal and the clock signal until the data signal and the clock During the phase synchronization of the signal, the delay-locked loop unit with push-pull function adjusts the phase of the data signal and the clock signal. In this process, since the time constant of the voltage controlled oscillator 22 is large, the phase locked loop function unit adjusts the phase of the clock signal slowly, compared to the delay locked loop unit pair clock signal with push-pull function. The phase adjustment can be ignored. Once the data signal and the clock signal are phase-synchronized, the data signal and the clock signal have a small phase difference. In this case, the phase-locked loop function unit can track the smaller phase difference value, thereby enabling the voltage to pass. The controlled oscillator 22 finely adjusts the phase of the clock signal in accordance with the first control signal. Since the low-frequency loop gain of the phase-locked loop functional unit is much larger than the delay-locked loop unit with the push-pull function, after the phase synchronization of the data signal and the clock signal, the phase-locked loop functional unit pairs the clock signal. The phase adjustment plays a leading role, and the phase adjustment after the phase synchronization is obtained is finely adjusted, so that the CDR can be guaranteed to have good jitter performance.

The data clock recovery module provided by the present embodiment can also use the delay-locked loop unit with push-pull function to adjust the phase of the locally generated clock signal and the received data signal in opposite directions. The phase-locked loop function unit fine-tunes the clock signal to realize the phase synchronization of the clock signal and the data signal. The phase adjustment of both phases can reduce the synchronization time of the clock signal and the data signal, and increase the jitter performance of the data clock recovery module. . On the basis of the foregoing embodiments, the embodiment provides a specific structure of the phase detecting unit, and the phase detecting unit may include: a phase detecting subunit and a loop filter; wherein: a phase detecting subunit, configured to detect a phase difference between the adjusted clock signal and the adjusted data signal;

And a loop filter, configured to filter the phase difference signal output by the phase detecting subunit, obtain a first control signal, and input the first control signal to the first phase adjusting unit and the second phase adjusting unit, respectively.

Since the phase difference between the adjusted clock signal and the adjusted data signal detected by the phase detecting subunit usually carries a high frequency signal such as a pulse signal, the first phase adjusting unit and the second phase adjusting unit may affect the clock signal and The accuracy of the phase adjustment of the data signal. Therefore, the phase difference value outputted by the phase detecting subunit can be filtered by the loop filter, the high frequency part of the phase difference value is filtered out to obtain the first control signal, and the low frequency first control signal is input to the first phase respectively. In the adjustment unit and the second phase adjustment unit. Among them, the loop filter can use various existing filters with filtering functions.

Optionally, an amplifier may be disposed in the CDR, and the data signal received by the receiving interface 1 is amplified and shaped, and the amplified and shaped data signal is input to the second phase adjusting unit to enable the first phase adjusting unit and the second phase adjusting unit. The phase adjustment of the clock signal and the data signal is more precise.

The data clock recovery module provided in this embodiment adjusts the phase of the phase-leading signal and pushes out the phase of the phase-lag signal by separately adjusting the phase of the locally generated clock signal and the received data signal in opposite directions. The phase synchronization of the clock signal and the data signal is realized, and the phase adjustment of both phases can reduce the synchronization time of the clock signal and the data signal. After detecting the phase difference between the adjusted clock signal and the adjusted data signal, the filter is used to filter, and the interference signal such as the pulse is removed to obtain the first control signal, thereby improving the phase adjustment of the data signal and the clock signal. degree. In addition, the amplifier amplifies and shapes the data signal to further reduce the interference of the interference signal on the data signal. FIG. 5 is a flowchart of an embodiment of a data clock recovery method according to the present invention. As shown in FIG. 5, the method includes:

S501: Perform phase adjustment on the clock signal generated according to the reference frequency according to the first control signal, and perform phase adjustment on the data signal according to the first control signal; the phase adjustment direction of the clock signal is opposite to the phase adjustment direction of the data signal; The frequency is locked at the frequency of the data signal; the first control signal is filtered by the phase difference between the adjusted clock signal and the adjusted data signal Obtained after the wave;

S502. The adjusted data signal is sampled by the adjusted clock signal to obtain a data signal synchronized with the adjusted clock signal.

The execution body of the above steps is the data clock recovery module CDR, and the data clock recovery module can be set on the OLT in the PON network.

Optionally, the frequency of the clock signal is locked to the frequency of the data signal, and specifically includes: the frequency of the clock signal is adjusted according to the second control signal; and the second control signal is divided by the frequency division signal according to the frequency division coefficient to obtain a frequency division. The frequency difference between the clock signal and the reference frequency is obtained by filtering the frequency difference; the frequency division coefficient is determined according to the frequency of the data signal. The second control signal can be a negative feedback signal.

Optionally, before the CDR performs phase adjustment on the clock signal generated according to the reference frequency according to the first control signal, the CDR may further: adjust a phase of the clock signal according to the first control signal.

Optionally, before the CDR performs phase adjustment on the data signal according to the first control signal, the CDR may further: perform amplification and shaping on the data signal.

The first control signal may be a negative feedback signal.

The execution of the above steps is the data clock recovery module. The specific structure and the process of the data clock recovery method are described in the related embodiments of the data clock recovery module provided by the present invention, and details are not described herein.

The data clock recovery method provided by the embodiment of the present invention adjusts the phase of the phase-leading signal back to the phase lag signal by respectively adjusting the phase of the locally generated clock signal and the data signal received from the optical network unit in opposite directions. The phase is pushed out to realize the phase synchronization of the clock signal and the data signal, and the phase adjustment of both phases can reduce the synchronization time of the clock signal and the data signal.

One of ordinary skill in the art will appreciate that all or a portion of the steps to implement the various method embodiments described above can be accomplished by hardware associated with the program instructions. The aforementioned program can be stored in a computer readable storage medium. The program, when executed, performs the steps including the above-described method embodiments; and the foregoing storage medium includes: a medium that can store program codes, such as a ROM, a RAM, a magnetic disk, or an optical disk.

Finally, it should be noted that the above embodiments are merely illustrative of the technical solutions of the present invention, and are not intended to be limiting thereof; although the present invention has been described in detail with reference to the foregoing embodiments, It should be understood that: the technical solutions described in the foregoing embodiments may be modified, or some of the technical features may be equivalently replaced; and the modifications or substitutions do not deviate from the essence of the corresponding technical solutions. The spirit and scope of the technical programme.

Claims

Rights request

A data clock recovery module, comprising: a receiving interface, a clock unit, a first phase adjusting unit, a second phase adjusting unit, a phase detecting unit, and a synchronizer;

The clock unit is configured to generate a clock signal according to a reference frequency, and input the clock signal to the first phase adjustment unit; a frequency of the clock signal is locked at a frequency of the data signal; the first phase adjustment a unit, configured to perform phase adjustment on the clock signal according to a first control signal fed back by the phase detecting unit, and input the adjusted clock signal to the phase detecting unit and the synchronization, respectively

The receiving interface is configured to receive a data signal;

2. The data clock recovery module according to claim 1, wherein the clock unit comprises: a frequency locker and a voltage controlled oscillator;

The frequency locker is configured to divide a clock signal fed back by the voltage controlled oscillator according to a frequency division coefficient, obtain a frequency difference between the frequency-divided clock signal and the reference frequency, and perform the frequency difference Filtering to obtain a second control signal, and feeding back the second control signal to the voltage controlled oscillator; the frequency dividing coefficient is determined according to a frequency of the data signal;

a voltage controlled oscillator for generating the clock signal, inputting the clock signal to the first phase adjustment unit and the frequency locker; the second control signal for feedback according to the frequency locker Adjust the frequency of the clock signal.

The data clock recovery module according to claim 1, wherein the clock unit is further configured to adjust a phase of the clock signal according to a first control signal fed back by the phase detecting unit. Bit.

The data clock recovery module according to claim 3, wherein the clock unit comprises: a frequency locker and a voltage controlled oscillator;

a voltage controlled oscillator for generating the clock signal, inputting the clock signal to the first phase adjustment unit and the frequency locker; the second control signal for feedback according to the frequency locker Adjusting a frequency of the clock signal; and adjusting a phase of the clock signal according to a first control signal fed back by the phase detecting unit.

The data clock recovery module according to any one of claims 1 to 4, wherein the phase detecting unit comprises: a phase detecting subunit and a loop filter;

The phase detecting subunit is configured to obtain a phase difference between the adjusted clock signal and the adjusted data signal;

The loop filter is configured to filter the phase difference value output by the phase detecting subunit to obtain the first control signal, and input the first control signal to the first phase respectively An adjustment unit and the second phase adjustment unit.

The data clock recovery module according to any one of claims 1 to 5, further comprising:

And an amplifier, configured to perform amplification and shaping on the data signal received by the receiving interface, and input the amplified and shaped data signal into the second phase adjusting unit.

The data clock recovery module according to any one of claims 1 to 6, wherein the first control signal is a negative feedback signal.

8. A data clock recovery method, comprising:

Performing phase adjustment on a clock signal generated according to the reference frequency according to the first control signal, and performing phase adjustment on the data signal according to the first control signal; a phase adjustment direction of the clock signal is opposite to a phase adjustment direction of the data signal The frequency of the clock signal is locked at a frequency of the data signal; the first control signal is obtained by filtering a phase difference between the adjusted clock signal and the adjusted data signal; And using the adjusted clock signal to sample the adjusted data signal to obtain a data signal synchronized with the adjusted clock signal.

The method according to claim 8, wherein the frequency of the clock signal is locked to the frequency of the data signal, and specifically includes:

The frequency of the clock signal is adjusted according to the second control signal; the second control signal is divided by the frequency division coefficient to obtain a frequency difference between the frequency-divided clock signal and the reference frequency, and And obtaining the frequency difference by filtering; the frequency division coefficient is determined according to a frequency of the data signal.

The method according to claim 8 or 9, wherein before the phase adjustment of the clock signal generated according to the reference frequency according to the first control signal, the method further includes:

Adjusting a phase of the clock signal according to the first control signal.

The method according to any one of claims 8 to 10, wherein before the phase adjustment of the data signal according to the first control signal, the method further includes:

Amplifying and shaping the data signal.

The method according to any one of claims 8-11, wherein the first control signal is a negative feedback signal.