WO2018040011A1

WO2018040011A1 - Clock recovery apparatus and clock recovery method

Info

Publication number: WO2018040011A1
Application number: PCT/CN2016/097648
Authority: WO
Inventors: 万文通; 颜敏
Original assignee: 华为技术有限公司
Priority date: 2016-08-31
Filing date: 2016-08-31
Publication date: 2018-03-08
Also published as: CN108886464A; CN108886464B

Abstract

A clock recovery apparatus (300) and a clock recovery method. In the clock recovery apparatus (300), a signal clock compensator (301) is configured to adjust clock phases of a first signal and a second signal in the frequency domain according to a parameter B and a parameter C, and output the first signal and the second signal; a signal adjuster (302) is configured to adjust, according to a parameter A, polarization angles of the first signal and the second signal for which the clock phases have been adjusted, and determine target positive spectrum information and target negative spectrum information; a phase discriminator (303) is configured to determine a clock error signal according to the target positive and negative spectrum information; a loop filter (304) is configured to filter the clock error signal, and further configured to lead out a signal from an integration branch of the loop filter (304) as a monitored signal; an interpolation controller (305) is configured to determine the parameter B according to the filtered clock error signal; and a signal characteristic parameter modifier (306) is configured to determine whether the monitored signal is within a preset fluctuation range, and if not, adjust the parameter A and the parameter C so that the monitored signal is within the preset fluctuation range.

Description

Clock recovery device and method for clock recovery

Technical field

The present application relates to the field of optical communications, and in particular, to a clock recovery device and a method for clock recovery.

Background technique

A coherent optical communication system, which is a kind of optical communication system, refers to a communication system that uses the coherence of light emitted by a laser to realize heterodyne or homodyne detection at the receiving end, called coherent communication, and realizes information transmission by using the coherent communication. It is called a coherent optical communication system. A coherent optical communication system can communicate information by amplitude, frequency, phase, or polarization. In a communication system such as a coherent optical communication system, after receiving the photoelectric conversion, the receiving end needs to perform algorithm processing in the digital domain. The speed at which the receiving end uses the algorithm to process the data and the speed at which the transmitting end transmits the data should be consistent at all times, so that all the transmitted data at the transmitting end can be processed in time, that is, the clock synchronization is maintained. For example, a coherent optical communication system is taken as an example, wherein a logical structure diagram of a coherent optical communication system is shown in FIG. 1: an analog to digital converter (English name: Analog to Digital Converter, abbreviated: ADC) receives an optical signal after conversion. 4 electrical signals, as shown in Figure 1, xi, xq, yi, yq, enter the analog-to-digital converter, analog-to-digital converter combines 4 signals into 2 different polarization (x1, y1 polarization) complex signals, combination The mode is (x1=xi+jxq), (y1=yi+jyq), x1, y1 enter the dispersion estimation and compensation module to complete the elimination of optical dispersion damage, output x2, y2, and then input clock recovery device, clock recovery device output A clock error signal is input to the loop filter. The output of the loop filter controls the voltage controlled oscillator. The voltage controlled oscillator adjusts the sampling phase and frequency of the analog to digital converter to complete the synchronization of the receiving end. That is, only such a signal with the correct phase of the sampling phase can be optimally received by the receiving end. It can be seen that the clock recovery device is an inseparable part of the coherent optical communication system, and its performance directly affects the performance of the entire coherent optical communication system.

That is, in the coherent optical communication system, after receiving the signal collected by the ADC, it is necessary to use the clock recovery device for clock recovery to achieve clock synchronization, which is the primary work of the coherent optical communication system.

However, in coherent optical communication systems, it is usually compensated for polarization mode dispersion (English full name: Polarization Mode Dispersion, abbreviated: PMD), dispersion and laser frequency offset effects. The schematic diagram of the structure of the clock recovery device in the prior art is shown in FIG. 2. In FIG. 2, the signal adjuster adjusts the positive angle of the signals of x and y through the A parameter to achieve the effect of the influence, and finally adjusts the signal through the B parameter. The clock, however, in the prior art clock recovery device, the signal characteristic parameter modifier determines the clock synchronization performance according to the mode size of the complex error signal output by the phase detector, for example, the real part of the output signal is the preset maximum When the value is considered, the clock synchronization performance is considered to be good, that is, the clock recovery device is considered to be optimal at this time; if the real value is in a fluctuation state, the clock synchronization performance is considered to be poor. However, the signal characteristic parameter modifier mainly corrects the PMD effect of the signal by the output A parameter value, so that the real part of the complex signal output by the phase detector is maintained at the maximum preset maximum value. That is, in the prior art, the real part of the phase detector output signal only reflects whether the clock performance is affected by the PMD. When it is affected by the PMD, the real part of the signal output by the phase detector is kept the most preset by adjusting the A parameter. The maximum value, however, in addition to the PMD, the dispersion and laser frequency offset have a great influence on the clock synchronization performance, which will affect the output of the phase detector, thereby affecting the output of the loop filter, and finally the clock recovery device. Adjusting the clock according to the B parameter is also affected, that is, the A value can only reduce the influence of the PMD, but if the signal is also affected by factors such as dispersion, the adjusted clock synchronization result is not the best, that is, in the prior art. The clock recovery device is just monitoring and reducing the impact of this single factor of PMD.

Summary of the invention

The present application provides a clock recovery device and a method for clock recovery. With the clock recovery device of the present application, it is possible to monitor and reduce the influence of factors such as PMD and dispersion.

A first aspect of the present application provides a clock recovery apparatus, including a signal clock compensator, a signal adjuster, a phase detector, a loop filter, an interpolation controller, and a signal characteristic parameter modifier, where The functions of each of the above devices are as follows:

The signal clock compensator is configured to convert the first signal and the second signal input to the signal clock compensator into a signal in a frequency domain form by using a Fourier transform, wherein the first and second signals are optical signals. Signals of different polarization states, then according to the B parameter fed back to the signal clock compensator by the interpolation controller, and the C parameter of the signal characteristic parameter modifier fed back to the signal clock compensator, the converted first signal and the second signal Performing adjustment of the clock phase, and outputting the first signal and the second signal after adjusting the clock phase to the signal adjuster;

The signal adjuster is configured to adjust the polarization angle of the first signal and the second signal after adjusting the clock phase according to the A parameter of the signal characteristic parameter modifier fed back to the signal adjuster, and determine the target positive spectrum information and the target negative spectrum information, Outputting the target positive spectrum information and the target negative spectrum information to the phase detector, wherein the target positive spectrum information includes a polarization-adjusted first signal and a second signal positive spectrum signal, and the target negative spectrum information includes polarization angle adjustment a negative signal of the first signal and the second signal;

a phase detector, configured to determine a clock error signal according to the received target positive spectrum information and the target negative spectrum information, and output the clock error signal to the loop filter;

a loop filter for filtering the clock error signal, and outputting the filtered clock error signal to the interpolation controller, and integrating the signal of the loop filter with the clock error signal as a monitoring signal Output to signal characteristic parameter modifier;

An interpolation controller is configured to determine a B parameter according to the filtered clock error signal, and the signal characteristic parameter modifier is configured to determine whether the monitoring signal is within a preset fluctuation range, and if the signal characteristic parameter modifier determines that the monitoring signal is not in a preset Within the fluctuation range, the A parameter and the C parameter are adjusted so that the monitoring signal is within the preset fluctuation range.

It can be seen from the above technical solution that since the monitoring signal is affected by factors such as PMD and dispersion, the monitoring signal will fluctuate. Therefore, by monitoring the monitoring signal, the A parameter and the C parameter are continuously adjusted, so that the monitoring signal is in the preset fluctuation range. Through the clock recovery device of the present invention, it is possible to monitor and reduce the influence of factors such as PMD and dispersion.

In a possible implementation, the signal adjuster adjusts the polarization angle of the first and second signals after adjusting the clock phase according to the A parameter, and determines the target positive spectrum information and the target negative spectrum information, specifically:

Multiplying the positive spectral signal of the first signal after adjusting the clock signal by Cos(A) to obtain a first positive spectral signal; multiplying the negative spectral signal of the first signal after adjusting the clock signal by Cos(A) to obtain the first a negative spectrum signal; multiplying the positive spectrum signal of the second signal after adjusting the clock signal by Sin(A) to obtain a second positive spectrum signal; multiplying the negative spectrum signal of the second signal after adjusting the clock signal by Sin(A) Obtaining a second negative spectral signal; combining the first positive spectral signal and the second positive spectral signal to obtain target positive spectral information; and combining the first negative spectral signal and the second negative spectral signal to obtain target negative spectral information.

That is, the calculation method of adjusting the polarization angle is given, and the feasibility of the scheme is improved. In the signal conditioner of the prior art, after the received A parameter is taken as a cosine, it is necessary to multiply a complex index as an adjustment parameter, that is, the final adjustment parameter is a plural form, and the signal adjuster in the present application only The received A parameter takes the cosine to ensure that the adjustment parameter is always a real number. It can reduce the computational complexity and reduce the power consumption while satisfying the function of adjusting the polarization angle.

In a possible implementation, the phase detector determines the clock error signal according to the target positive spectrum information and the target negative spectrum information, and specifically may refer to determining the clock error signal according to the target positive spectrum information and the entire spectrum information of the target negative spectrum information.

That is, the phase detector in the present application determines the clock error signal according to the target positive spectrum information and all the spectrum information of the target negative spectrum information, that is, the first signal and the entire spectrum information of the first signal after adjusting the polarization angle to determine the clock error signal, In the prior art, the first signal and the partial spectrum information of the first signal are adjusted by using the polarization angle to determine the clock error signal, because the use of very little spectrum information causes the phase detector to acquire information when there is a frequency offset. The effectiveness is greatly reduced. The phase detector in this application can avoid this situation by using full frequency domain information.

In a possible implementation, the signal characteristic parameter modifier adjusts the A parameter and the C parameter, specifically, the A parameter is adjusted within the first preset adjustment range, and the C parameter is adjusted within the second preset adjustment range.

That is, the adjustment range of the A parameter C parameter can be adjusted according to the actual application situation, that is, the optimal adjustment range can be selected according to the monitoring precision and speed of the actual demand, thereby improving the diversity of the scheme.

In a possible implementation, the clock recovery apparatus may further include a shift register for receiving a parameter determined by the interpolation controller according to the clock error signal, and first inputting to the signal clock compensator according to the D parameter pair The signal and the second signal are shifted.

The second aspect of the present application provides a clock recovery method, which is applied to the clock recovery device in the above first aspect, the clock recovery device includes a signal clock compensator, a signal adjuster, a phase detector, and a ring. The path filter, the interpolation controller, and the signal characteristic parameter modifier. In the clock recovery method, the functions of each device are as follows:

The signal clock compensator converts the first signal and the second signal input to the signal clock compensator into signals in the frequency domain form by using a Fourier transform, wherein the first and second signals are two different polarizations of the optical signal. State signal, which is then fed back to the B parameter of the signal clock compensator according to the interpolation controller. And the signal characteristic parameter modifier feeds back to the C parameter of the signal clock compensator, adjusts the clock phase of the converted first signal and the second signal, and outputs the first signal and the second signal after adjusting the clock phase to The signal adjuster adjusts the polarization angle of the first signal and the second signal after adjusting the clock phase according to the A parameter of the signal characteristic parameter modifier fed back to the signal adjuster, and determines the target positive spectrum information and the target negative spectrum information. And outputting the target positive spectrum information and the target negative spectrum information to the phase detector, wherein the target positive spectrum information includes a polarization signal adjusted first signal and a second signal positive spectrum signal, and the target negative spectrum information includes a polarization angle Adjusting the negative signal of the first signal and the second signal; the phase detector determines the clock error signal according to the received target positive spectrum information and the target negative spectrum information, and outputs the clock error signal to the loop filter a loop filter for filtering the clock error signal and filtering the time The error signal is output to the interpolation controller, and the signal obtained by integrating the branch path of the loop filter with the clock error signal is output as a monitoring signal to the signal characteristic parameter modifier; the interpolation controller determines B according to the filtered clock error signal. Parameter; the signal characteristic parameter modifier determines whether the monitoring signal is within the preset fluctuation range. If the signal characteristic parameter modifier determines that the monitoring signal is not within the preset fluctuation range, then the A parameter and the C parameter are adjusted so that the monitoring signal is preset. Within the range of fluctuations.

In a possible implementation, the signal adjuster adjusts the polarization angle of the first and second signals after adjusting the clock phase according to the A parameter, and determines the target positive spectrum information and the target negative spectrum information, specifically, the clock signal is adjusted. The positive spectrum signal of the first signal is multiplied by Cos(A) to obtain a first positive spectrum signal; the negative spectrum signal of the first signal after adjusting the clock signal is multiplied by Cos(A) to obtain a first negative spectrum signal; Multiplying the positive spectral signal of the second signal after adjusting the clock signal by Sin(A) to obtain a second positive spectral signal; multiplying the negative spectral signal of the second signal after adjusting the clock signal by Sin(A) to obtain a second a negative spectral signal; combining the first positive spectral signal and the second positive spectral signal to obtain target positive spectral information, and combining the first negative spectral information and the second negative spectral information to obtain target negative spectral information.

In a possible implementation, the phase detector determines the clock error signal according to the target positive spectrum information and the entire spectrum information of the target negative spectrum information.

In a possible implementation, the signal characteristic parameter modifier specifically adjusts the A parameter within the first preset adjustment range, and adjusts the C parameter within the second preset adjustment range.

In a possible implementation, the clock recovery device further includes a shift register, the shift register receives a parameter determined by the interpolation controller according to the clock error signal, and inputs the signal according to the D parameter pair The first signal and the second signal of the clock compensator perform a shift operation.

Compared with the prior art, it can be seen from the above technical solutions that in the present application, since the monitoring signal is affected by factors such as PMD and dispersion, the monitoring signal may fluctuate. Therefore, by monitoring the monitoring signal, the A parameter is continuously adjusted. And the C parameter, so that the monitoring signal is within the preset fluctuation range, that is, the clock recovery device of the present invention can monitor and reduce the influence of factors such as PMD and dispersion.

DRAWINGS

1 is a schematic diagram of a logical structure of a conventional coherent optical communication system;

2 is a schematic structural view of a conventional clock recovery device;

3 is a schematic diagram of a logical structure of an embodiment of a clock recovery apparatus according to the present application;

4 is a schematic diagram showing the logical structure of a loop filter in the clock recovery device of the present application;

5 is a schematic diagram showing the logical structure of a signal clock compensator in the clock recovery device of the present application;

6 is a schematic diagram showing the logical structure of a signal adjuster in the clock recovery device of the present application;

7 is a schematic diagram showing the logical structure of a phase detector in a clock recovery device of the present application;

8 is a schematic diagram of a clock error processing accumulation process of the phase detector of the present application;

FIG. 9 is a schematic diagram showing the logical structure of another embodiment of a clock recovery apparatus according to the present application.

detailed description

The embodiment of the present application provides a clock recovery device and a clock recovery method, which can monitor and reduce the influence of factors such as PMD and dispersion.

The technical solutions in the embodiments of the present application are clearly and completely described in the following with reference to the accompanying drawings in the embodiments of the present application. It is an embodiment of the present application, and not all of the embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments of the present application without departing from the inventive scope shall fall within the scope of the application.

The terms "first", "second", "third", "fourth", etc. (if present) in the specification and claims of the present application and the above figures are used to distinguish similar objects without having to use To describe a specific order or order. It is to be understood that the data so used may be interchanged where appropriate so that the embodiments described herein can be implemented in a sequence other than what is illustrated or described herein. In addition, surgery The phrase "comprising" and variations of the invention are intended to cover a non-exclusive inclusion, for example, a process, method, system, product, or device that comprises a series of steps or units is not necessarily limited to those steps or units that are clearly listed. Rather, other steps or units not explicitly listed or inherent to such processes, methods, products, or devices may be included.

Please refer to FIG. 3. FIG. 3 is a schematic diagram of a logical structure of an embodiment of a clock recovery apparatus according to the present application. The clock recovery apparatus 300 includes a signal clock compensator 301, a signal adjuster 302, a phase detector 303, and a loop filter. The logic structure diagram of the loop filter 304 is shown in FIG. 4, and the loop filter 304 is a common loop filter, where Kp and Ki are The coefficients of the loop filter 304. It can be seen from FIG. 4 that the filtered output of the loop filter 304 is the signal output 1, that is, the output signal outputted to the interpolation controller 305. Here, the signal derived from the branch circuit of the loop filter 304 is assumed as the monitoring signal, that is, FIG. The signal output 2 described in the above is shown in Figure 4.

Those skilled in the art will appreciate that the dispersion has characteristics of different phase changes as the frequency changes. When the signal having dispersion enters the phase detector 303, the phase detector 303 superimposes the clock error phase of the signal. After the phase change caused by the dispersion, the signal output from the phase detector is thus subject to fluctuations caused by the dispersion. After passing through the loop filter 304, this fluctuation is also accompanied. Therefore, the dispersion causes the value of the signal output 2 of the loop filter to fluctuate.

In addition, PMD refers to the characteristic that the two polarization states of light have different delays, accompanied by random changes in time. It should be understood that after the phase detector 303 is sent after the signal is affected by the PMD, the output signal of the phase detector 303 is subject to fluctuations caused by different delays between the two polarization states and caused by random variations. That is, the PMD will also cause the value of the output signal 2 of the loop filter 304 to fluctuate.

In addition, in a coherent optical communication system, the laser frequency of the transmitter and the receiver is inconsistent, resulting in demodulation of the signal into heterodyne demodulation, and heterodyne demodulation results in a fixed offset of the signal clock component of the phase detector 303. The fixed offset causes the phase detector 303 output to have phase noise, and the magnitude of the phase noise is related to the magnitude of the specific frequency deviation of the two lasers. The signal with phase noise is input to the loop filter 304, which also affects the output value of the signal output 2 of the loop filter 304, causing it to fluctuate.

That is, as long as the input signal of the phase detector 303 is subjected to the combination of one or more of the above factors, the same result is that the value of the output signal 2 of the loop filter 304 fluctuates. That can pass the loop The change of the signal output 2 of the filter 304 can judge whether the signal clock synchronization performance is normal.

Therefore, the present application proposes a clock recovery device 300 as shown in FIG. 3, which is different from the clock recovery device in the prior art, that is, the clock recovery device shown in FIG. Signal output 2 of filter 304 is used as a feedback adjustment signal characteristic parameter. The signal characteristic parameter modifier 306 controls the operation state of the entire loop by continuously adjusting and outputting the control A parameter and the C parameter, so that the value of the signal output 2 of the loop filter 304 is within the preset fluctuation range, if the loop The value of the signal output 2 of the filter 304 is within the preset fluctuation range, indicating that the clock recovery device 300 has reduced or eliminated the effects of factors such as PMD, dispersion, and the like.

For ease of understanding, the working process of the clock recovery apparatus 300 in this application is specifically described below:

The signal clock compensator 301 is configured to convert the first and second signals outputted to the signal clock compensator into signals in the frequency domain form, and then adjust the clock phase of the first signal according to the B parameter and the C parameter, according to the B parameter and the C After adjusting the clock phase of the second signal, the first signal and the second signal are output;

The first signal and the second signal are signals of two different polarization states of the optical signal, and the B parameter is fed back to the signal clock compensator 301 by the interpolation controller 305, and the C parameter is fed back to the signal by the signal characteristic parameter modifier 306. Clock compensator 301.

That is, the signal clock compensator compensates for the clock offset of the input signal. The purpose of the compensation is to have the signal sampled by a sampler of a fixed sampling multiple.

That is, the signal clock compensator in the present application can convert the time domain discrete signal after the ADC conversion into a frequency domain form signal through a fast Fourier transform (abbreviation: FFT), and then according to the signal. The B parameter fed back by the interpolation controller 305 and the C parameter fed back by the signal characteristic parameter modifier 306 adjust the clock phase of the input signal, and output the signal after the clock phase is adjusted. That is, the purpose of the signal clock compensator 301 is to perform clock offset compensation on the input signal. The purpose of the compensation is to allow the signal to be sampled by a sampler of a fixed sampling multiple.

Please refer to FIG. 5. FIG. 5 is a schematic diagram showing the logical structure of a signal clock compensator in the clock recovery apparatus of the present application, where Exp represents a natural index. For convenience of description, in the present embodiment, it is assumed that the first signal is an X signal and the second signal is a Y signal. In the signal clock compensator 301, the X and Y signals are subjected to FFT, and then multiplied by a phase variable, the phase The variable consists of B and C parameters. B parameter It is used for signal clock adjustment, and the C parameter is mainly to adjust the influence of dispersion. After the signal clock compensator, the sampling rate of the signal is adjusted. At this time, if the transmitting clock of the system transmitter deviates with time, then the signal clock compensator follows the B parameter and the C parameter. , to achieve a fixed sampling rate of the sampling rate of the target. As long as the B parameter and the C parameter satisfy the fixed sampling multiple at this time, the clock synchronization performance can be considered normal, that is, the influence of the clock output of the clock output has been reduced or has been eliminated.

It should be noted that the existing signal clock compensator uses the time domain interpolation filter to complete the clock correction of the input signal, and the time domain interpolation filter selects different number of filter coefficients according to different precision requirements, and the coefficient is directly The chip resources of the signal clock compensator at the time of implementation are determined. For example, suppose the existing signal clock compensator performs time domain interpolation with 8 filter tap coefficients for 100 data points, that is, moving a time phase, then 800 multiplication operations are required. However, in the signal clock compensator of the present application, the signal input to the signal clock compensator is converted into a signal in the form of a frequency domain, and then the clock is corrected. In the frequency domain, only 100 multiplication operations are required. That is, the existing signal clock compensator wastes a large number of multipliers with respect to the signal clock compensator in the present application.

The clock recovery device in the present application is used to take the output signal of the signal clock compensator 301 as a feedback signal, and output it to the signal adjuster 302;

The signal adjuster 302 is configured to adjust the polarization angle of the X and Y signals after adjusting the clock phase according to the A parameter, and determine the target positive spectrum information and the target negative spectrum information.

The A parameter is fed back to the signal adjuster 302 by the signal characteristic parameter modifier 306. The target positive spectrum information includes a positive spectrum signal of the X signal and the Y signal after the polarization angle adjustment, and the target negative spectrum information includes the polarization angle adjustment. Negative spectrum signal of X signal and Y signal.

Preferably, the polarization angle adjustment and the target positive spectrum information and the target negative spectrum information are specifically determined by the manner shown in FIG. 6. Referring to FIG. 6, FIG. 6 is a logic of a signal adjuster in the clock recovery apparatus of the present application. Schematic:

That is, the positive spectrum signal of the X signal after adjusting the clock signal is multiplied by Cos(A) to obtain the first positive spectrum signal; and the negative spectrum signal of the X signal after adjusting the clock signal is multiplied by Cos(A) to obtain the first a negative spectral signal;

Multiplying the positive spectral signal of the Y signal after adjusting the clock signal by Sin(A) to obtain a second positive spectral signal; multiplying the negative spectral signal of the Y signal after adjusting the clock signal by Sin(A) to obtain a second negative frequency Spectral signal

Combining the first positive spectral signal and the second positive spectral signal to obtain target positive spectral information; combining the first negative spectral signal and the second negative spectral signal to obtain target negative spectral information;

Finally, the target positive spectrum information and the target negative spectrum information are output to the phase detector.

In the clock recovery device of the present application, the output signal of the signal clock compensator 301 is taken out as a feedback signal, and is output to the signal adjuster 302, that is, the X signal and the Y signal after adjusting the clock signal can be fed back to the signal adjuster 302. After the signal adjuster 302 receives the X signal and the Y signal after adjusting the clock signal, preferably, the polarization angle can be adjusted by the manner as shown in FIG. 6.

It should be understood that the influence of PMD is mainly reflected in the delay difference between the two polarization states of the X signal and the X signal, and the delay difference causes the X and Y signals to have different phase differences. The way shown in Figure 6 is to adjust the delay difference between the X and Y signals by adjusting the phase difference. This adjustment of the A parameter can compensate for the impact of PMD.

It should be noted that the difference between the signal adjuster in the present application and the existing signal adjuster is that the adjustment parameters are different. Now the technology takes the cosine of the received A parameter and needs to multiply a complex index as the adjustment parameter, that is, finally The adjustment parameter is in the plural form, and the present invention only takes the cosine operation of the received A parameter to ensure that the adjustment parameter is always a real number. The adjustment function can be satisfied while reducing the computational complexity, thereby reducing system power consumption.

It should be noted that, according to the A parameter, the signal adjuster can obtain other adjustment parameters according to the A parameter, in addition to taking the cosine as the adjustment parameter. For example, the signal adjuster takes the received A parameter into a sinusoidal operation, as long as the final decision can be made according to the A parameter. The adjustment of the A parameter can make up for the influence of the PMD, and is not limited herein.

The phase detector 303 is configured to perform phase discrimination on the signal input from the signal adjuster 302 to the phase detector 303 to obtain a clock phase difference;

The phase detector 303, specifically, is configured to perform phase discrimination based on the target positive spectrum information and the partial spectrum information or the entire spectrum information of the target negative spectrum information, and determine a clock error signal, preferably, according to the target positive spectrum information and The entire spectrum information of the target negative spectrum information is phase-detected.

That is, the phase detector 303 mainly performs phase discrimination on the signal input to the phase detector, and may specifically refer to a phase detector based on the Godard algorithm, and may also be a phase detector based on the gardner algorithm, etc., which is not limited herein. , depending on the form of the signal entering the phase detector, but as long as the phase detector 303 is adjusted by the signal The input signal of the whole device 302 can determine the clock error signal. When the signal input to the phase detector 303 is the target positive spectrum signal and the target spectrum signal, preferably, the phase detector can perform phase discrimination based on the target positive spectrum information and the entire spectrum information of the target negative spectrum information to determine the clock. Error signal.

For ease of understanding, the process of determining the clock error signal based on the target spectrum information and the entire spectrum information of the target negative spectrum information is described herein:

Please refer to FIG. 7. FIG. 7 is a schematic diagram of the logic structure of the phase detector in the clock recovery apparatus of the present application. After the target positive spectrum signal and the target negative spectrum signal output from the signal adjuster 302 to the phase detector 303 are spectrally combined, The combined spectrum signal is sequence-expanded, and the imaginary part, that is, the clock error signal is obtained after being accumulated by the clock phase error processing, and the obtained clock error signal is output to the loop filter 304.

It is assumed here that the number of points when the previous signal clock compensator performs fast Fourier transform on the signal is N, then the target positive spectrum information can be assumed to be F(1), F(2), F(3)...F(N). /2), the target negative spectrum signal is F(N/2+1), F(N/2+2), F(N/2+3)...F(N), then the phase detector 303 passes the target positive The spectrum information and the target negative spectrum information are combined and combined into a complete frequency domain signal as F(1), F(2), F(3)...F(N). The longer the extended length is, the more accurate the clock error is estimated, but the more time-consuming the response is. The specific value needs to be a compromise value according to the system, which is not limited here.

For convenience of explanation, it is assumed that the length n to be expanded is 2 (n is an integer of >=1), and the extended sequence is F(N-1), F(N), F(1), F(2). , F(3)...F(N), F(1), F(2). Then, the clock phase error processing is accumulated for the extended sequence, and the specific processing accumulation method is as shown in FIG. 8, that is, the extended sequence is conjugated according to the manner of FIG. 8, and the final accumulated result is taken as the imaginary part. That is, the clock error signal is output to the loop filter 304.

It should be noted that when the extended length n is another value, it can be deduced according to the above description, and details are not described herein again.

The loop filter 304 is configured to filter the clock error signal, and output the filtered clock error signal to the interpolation controller 305, and also use the signal extracted from the product branch path of the loop filter 304 as a monitoring signal. The monitor signal is fed back to the signal characteristic parameter modifier 306.

As shown in FIG. 4, the clock error signal enters the loop filter 304 and is divided into two signals. One signal is multiplied by the coefficient Kp, one is multiplied by Ki, and the shunt multiplied by Ki is accumulated in delay, and accumulated. of The result is added after the result of the Kp path, that is, the filtered clock error signal, that is, the signal output 1 shown in FIG. 4, and the delay accumulation is separately taken out as a monitoring signal, that is, the signal output 2 shown in FIG. .

It should be noted that those skilled in the art can clearly understand that the Kp and Ki coefficients are the coefficients of the loop filter, and the specific coefficients are adjusted according to the condition of the entire loop system, which is not limited herein. I will not go into details.

The interpolation controller 305 is configured to determine a B parameter according to the filtered clock error signal, and output the B parameter to the signal clock compensator 301;

In the present application, the interpolation controller can input the incoming clock error signal for interpolation, thereby determining the B parameter, and then outputting the B parameter to the signal clock compensation compensator 301.

For ease of understanding, the following example illustrates the process of determining the B parameter:

After the interpolation controller 305 receives the clock error signal output by the loop filter, here assumed to be T, the interpolation controller 305 determines whether the T is greater than 1 or less than -1;

If it is greater than 1, the corresponding fractional part is the B parameter. For example, if T=1.1, then B=0.1;

If it is less than -1, the corresponding fractional part is the B parameter. For example, if T=-1.1, then B=-0.1;

If T is between -1 and 1, the corresponding value is the B parameter. For example, if T = 0.5, then B = 0.5, and if T = -0.5, then B = -0.5.

The signal characteristic parameter modifier 306 is configured to determine whether the monitoring signal is within a preset fluctuation range; if it is determined that the monitoring signal is not within the preset fluctuation range, adjusting the A parameter in the first preset adjustment range, in the second preset The C parameter is adjusted within the adjustment range, and the A parameter is fed back to the signal adjuster 302, and the C parameter is fed back to the signal clock compensator 301 so that the monitoring signal is within the preset fluctuation range.

That is, in the present application, after the signal characteristic parameter modifier 306 receives the above-mentioned monitoring signal, that is, the signal output 2 of the loop filter, it is determined whether the monitoring signal is within the preset fluctuation range. It can be seen from the foregoing description that when the monitoring signal generates fluctuation, it is affected by factors such as PMD and dispersion. At this time, the signal characteristic parameter modifier in the present application dynamically adjusts the A parameter and the C parameter to make the last monitoring signal. The output is within the preset fluctuation range, that is, by continuously scanning the A and C parameters to eliminate or reduce the influence of PMD, dispersion and other factors.

Among them, the preset fluctuation range can be configured according to empirical data. For example, the values of the long-term output generally fluctuate within +/- 0.1. At this time, the clock synchronization performance is considered normal. If it is greater than this value, then the A and C parameters are scanned and adjusted to find the A and C parameters to satisfy this 0.1. Requirements.

Preferably, the signal characteristic parameter modifier 306 can further adjust the A parameter within the first preset adjustment range, and adjust the C parameter within the second preset adjustment range, so that the monitoring signal is within the preset fluctuation range, that is, in advance Scan the A and C parameters within the range to eliminate or reduce the effects of PMD, dispersion and other factors.

For ease of understanding, the following examples are also given:

Preferably, it is assumed here that the first preset adjustment range is: -45 to +45, the step degree is 1, the second preset range is 0 to 1, and the step degree is 1, and the specific scanning process is as follows:

a: fixed A parameter, coarsely select A parameter in the first preset adjustment range, for example -45, scan C parameter, C parameter is within the second preset range, step is less than 1 value, for example, C parameter is taken The value can be: 0.1, 0.2...1. At this time, by scanning the C parameter, the output value of the loop filter 304 signal output 2 is stored after each conversion of the C parameter, and the variance is calculated, assuming that the calculated variance is std1.

b: The change A parameter is -44. In step a, the operation of scanning the C parameter is repeated, and the output value of the signal output 2 of the loop filter 304 is also saved, and the variance is calculated and set to std2.

c: After changing all the A parameters, compare all the variances, select the A parameter and the C parameter corresponding to the smallest variance.

Optionally, after completing the above scanning, the signal characteristic parameter modifier further continues to scan on the basis of the above scanning, as shown by d:

d: Determine the second scan range on the A parameter and the C parameter determined in the ac step. For example, if the result of the previous scan is A=15, C=0.3, then the range of the scan can be set to the value of the A parameter. The range is from 10 to 20, and the C parameter ranges from 0.2 to 0.4.

e: The scanning according to step 1 is repeated according to the range set by d, and the change of the signal is always tracked by such scanning.

It should be noted that the scanning range described in the ae step is a preferred scanning scheme, but is not limited to the present application. The signal characteristic parameter modifier 306 can be selected according to the actual application, for example, according to the accuracy and speed of the scanning. , specifically here is not limited.

Optionally, in combination with the clock recovery device embodiment, the clock recovery device of the present application may further include a shift register. Referring to FIG. 9 , FIG. 9 is a schematic diagram of another embodiment of a clock recovery device according to the present application. The recovery device 900 includes a signal clock compensator 901 and a signal adjuster. 902, phase detector 903, loop filter 904, interpolation controller 905, signal characteristic parameter modifier 906, and shift register 907:

The functions of the signal clock compensator 901, the signal adjuster 902, the phase detector 903, the loop filter 904, the interpolation controller 905, and the signal characteristic parameter modifier 906 in the present clock recovery apparatus can be referred to the above embodiments. Description, which will not be described here.

In the clock recovery device 900, in combination with the above embodiment, the interpolation controller 905 determines the B parameter according to the monitoring signal, and the interpolation controller further returns the D parameter to the shift register 907 according to the monitoring signal D parameter. The shift operation of the register 907 according to the D parameter;

For example, in combination with the foregoing embodiment, when it is determined that the monitoring signal is greater than 1, the integer is further taken down according to the monitoring signal, and the obtained integer, that is, the D parameter is sent to the shift register 907 shift signal;

When it is judged that the monitor signal is less than -1, the rounded integer, i.e., the D parameter, is sent to the shift register 907 to shift the signal.

Compared with the prior art, it can be seen from the above technical solution that the clock recovery device in the present application shifts the first signal and the second signal according to the D parameter, and then outputs the signal to the signal clock compensator. Wherein, the D parameter is fed back to the shift register by the interpolation controller; the signal clock compensator performs clock phase adjustment on the first and second signals input to the signal clock compensator according to the B parameter and the C parameter, and outputs the adjusted clock phase. The first and second signals, wherein the first and second signals are signals of two different polarization states of the optical signal, the B parameter is fed back to the signal clock compensator by the interpolation controller, and the C parameter is fed back by the signal characteristic parameter modifier to a signal clock compensator; the signal adjuster adjusts a polarization angle of the first and second signals after adjusting the clock phase according to the A parameter, and outputs the determined target positive spectrum information and the target negative spectrum information to the phase detector, wherein The A parameter is fed back to the signal adjuster by the signal characteristic parameter modifier; the phase detector is based on the target positive spectrum information and the target negative spectrum information. a clock error signal and outputting a clock error signal to the loop filter; the loop filter filters the clock error signal, and outputs the filtered clock error signal to the interpolation controller, from the product branch of the loop filter The extracted signal is used as a monitoring signal, and the monitoring signal is fed back to the signal characteristic parameter modifier; the interpolation controller determines the B parameter and the D parameter according to the filtered timing error signal, and outputs the B parameter to the signal clock compensator, and the D parameter Feedback to the shift register; the signal characteristic parameter modifier determines whether the monitoring signal is within the preset fluctuation range, and if not, dynamically adjusts the A parameter and the C parameter so that the monitoring signal is within the preset fluctuation range. In this application, due to the monitoring signal Influenced by factors such as PMD and dispersion, the monitoring signal may fluctuate. Therefore, by monitoring the monitoring signal, the A parameter and the C parameter are continuously adjusted, so that the monitoring signal is within the preset fluctuation range, that is, by the clock recovery device of the present invention. Monitor and reduce the effects of factors such as PMD and dispersion.

A clock recovery device in the present application has been described above. The following describes a method for clock recovery in the present application. The clock recovery method is applied to the clock recovery device. The method includes:

The shift register performs a shift operation on the first signal and the second signal according to the parameter D, wherein the D parameter and the D parameter are fed back to the shift register by the interpolation controller;

The signal clock compensator adjusts the clock phase of the first and second signals input to the signal clock compensator according to the B parameter and the C parameter, and outputs the first and second signals after adjusting the clock phase, the first and second signals. For the signal of two different polarization states of the optical signal, the B parameter is fed back to the signal clock compensator by the interpolation controller, and the C parameter is fed back to the signal clock compensator by the signal characteristic parameter modifier;

The signal adjuster adjusts the polarization angles of the first and second signals after adjusting the clock phase according to the A parameter, and outputs the determined target positive spectrum information and the target negative spectrum information to the phase detector, wherein the A parameter is determined by the signal characteristic The parameter modifier feeds back to the signal adjuster, and the target positive spectrum information includes a first signal and a second signal positive spectrum signal after the polarization angle adjustment, and the target negative spectrum information includes the first signal and the second signal after the polarization angle adjustment. Negative spectrum signal;

The phase detector determines a clock error signal according to the target positive spectrum information and the target negative spectrum, and outputs the clock error signal to the loop filter;

The loop filter filters the clock error signal, and outputs the filtered clock error signal to the interpolation controller. The signal extracted from the product branch of the loop filter is used as a monitoring signal, and the monitoring signal is fed back to the signal characteristic parameter. modifier;

The interpolation controller determines the B parameter and the D parameter according to the filtered timing error signal, and outputs the B parameter to the signal clock compensator, and feeds the D parameter to the shift register;

The signal characteristic parameter modifier determines whether the monitoring signal is within the preset fluctuation range, and if not, dynamically adjusts the A parameter and the C parameter so that the monitoring signal is within the preset fluctuation range.

It should be noted that, in the method for clock recovery in the present application, the specific steps and implementation details of each device of the clock recovery device can be referred to the corresponding description in the foregoing embodiment of the clock recovery device, and details are not described herein again.

In the several embodiments provided by the present application, it should be understood that the disclosed system, modules and squares The law can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of the modules is only a logical function division. In actual implementation, there may be another division manner, for example, multiple units or components may be combined or Can be integrated into another system, or some features can be ignored or not executed. In addition, the mutual coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interface, device or unit, and may be in an electrical, mechanical or other form.

The units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of the embodiment.

In addition, each functional module in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above integrated unit can be implemented in the form of hardware or in the form of a software functional unit.

The integrated modules, when implemented in the form of software functional units and sold or used as separate products, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present application, in essence or the contribution to the prior art, or all or part of the technical solution may be embodied in the form of a software product stored in a storage medium. A number of instructions are included to cause a computer device (which may be a personal computer, server, or network device, etc.) to perform all or part of the steps of the methods described in various embodiments of the present application. The foregoing storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk, and the like. .

The above embodiments are only used to explain the technical solutions of the present application, and are not limited thereto; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can still The technical solutions described in the embodiments are modified, or the equivalents of the technical features are replaced by the equivalents. The modifications and substitutions of the embodiments do not depart from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

A clock recovery device, comprising:

a signal clock compensator, a signal adjuster, a phase detector, a loop filter, an interpolation controller, and a signal characteristic parameter modifier;

The signal clock compensator is configured to convert the first signal and the second signal input to the signal clock compensator into a signal in a frequency domain form, and pass the converted first signal according to the B parameter and the C parameter pair. And adjusting the clock phase by the second signal, and outputting the first signal and the second signal after adjusting the clock phase to the signal adjuster, where the first and second signals are two different polarization states of the optical signal a signal, the B parameter is fed back to the signal clock compensator by the interpolation controller, and the C parameter is fed back to the signal clock compensator by the signal characteristic parameter modifier;

The signal adjuster is configured to perform polarization angle adjustment on the first signal and the second signal after adjusting a clock phase according to the A parameter, determine target positive spectrum information and target negative spectrum information, and use the target positive spectrum information and Target negative spectrum information is output to the phase detector, the A parameter is fed back to the signal adjuster by the signal characteristic parameter modifier, and the target positive spectrum information includes the first adjusted by the polarization angle a positive spectral signal of the second signal, the target negative spectral information comprising a negative spectral signal of the first signal and the second signal after the polarization angle adjustment;

The phase detector is configured to determine a clock error signal according to the target positive spectrum information and the target negative spectrum information, and output the clock error signal to the loop filter;

The loop filter is configured to filter the clock error signal, output the filtered clock error signal to the interpolation controller, and feed back a monitoring signal to the signal characteristic parameter modifier. The monitoring signal is a signal obtained by integrating the clock error signal by a product branch path of the loop filter;

The interpolation controller is configured to determine the B parameter according to the filtered clock error signal;

The signal characteristic parameter modifier is configured to determine whether the monitoring signal is within a preset fluctuation range, and if not, adjust the A parameter and the C parameter such that the monitoring signal is within the preset fluctuation range.
The clock recovery device according to claim 1, wherein the signal adjuster adjusts the polarization angle of the first and second signals after adjusting the clock phase according to the A parameter. Target positive spectrum information and target negative spectrum information, including:

The signal adjuster multiplies the positive spectral signal of the first signal after adjusting the clock signal by Cos(A) to obtain a first positive spectral signal; multiplying the negative spectral signal of the first signal after adjusting the clock signal Obtaining a first negative spectral signal with Cos(A);

Multiplying the positive spectral signal of the second signal after adjusting the clock signal by Sin(A) to obtain a second positive spectral signal; multiplying the negative spectral signal of the second signal after adjusting the clock signal by Sin(A) Obtaining a second negative spectral signal;

Combining the first positive spectral signal and the second positive spectral signal to obtain the target positive spectral information; combining the first negative spectral signal and the second negative spectral signal to obtain the target negative spectral information.
The clock recovery apparatus according to claim 2, wherein the phase detector determines the clock error signal according to the target positive spectrum information and the target negative spectrum information, including:

The phase detector determines the clock error signal according to the target positive spectrum information and all spectrum information of the target negative spectrum information.
The clock recovery apparatus according to any one of claims 1 to 3, wherein the signal characteristic parameter modifier adjusts the A parameter and the C parameter, including:

The signal characteristic parameter modifier adjusts the A parameter within a first preset adjustment range, and adjusts the C parameter within a second preset adjustment range.
The clock recovery device according to any one of claims 1 to 4, wherein the clock recovery device further comprises:

a shift register for performing a shift operation on the first signal and the second signal input to the signal clock compensator according to a D parameter, the D parameter being fed back to the shift register by the interpolation controller The D parameter is determined by the interpolation controller based on the clock error signal.
A method for clock recovery, characterized in that the method is applied to a clock recovery device comprising a signal clock compensator, a signal adjuster, a phase detector, a loop filter, an interpolation controller, and signal characteristics A parameter modifier, the method comprising:

The signal clock compensator converts the first signal and the second signal input to the signal clock compensator into signals in the frequency domain form, and performs the converted first signal and the second signal according to the B parameter and the C parameter. Adjustment of the clock phase, and adjusting the first signal and the second signal after the clock phase And outputting to the signal adjuster, the first and second signals are signals of two different polarization states of the optical signal, and the B parameter is fed back by the interpolation controller to the signal clock compensator, the C The parameter is fed back to the signal clock compensator by the signal characteristic parameter modifier;

The signal adjuster adjusts the polarization angle of the first signal and the second signal after adjusting the clock phase according to the A parameter, and determines the target positive spectrum information and the target negative spectrum information, and the target positive spectrum information and the target negative spectrum. Information is output to the phase detector, the A parameter is fed back to the signal adjuster by the signal characteristic parameter modifier, and the target positive spectrum information includes the first signal after being adjusted by the polarization angle, a positive spectral signal of the second signal, the target negative spectral information comprising a negative spectral signal of the first signal and the second signal after the polarization angle adjustment;

The phase detector determines a clock error signal according to the target positive spectrum information and the target negative spectrum information, and outputs the clock error signal to the loop filter;

The loop filter filters the clock error signal, outputs the filtered clock error signal to the interpolation controller, and feeds back a monitoring signal to the signal characteristic parameter modifier, the monitoring signal a signal obtained by integrating the clock error signal for a product branch path of the loop filter;

The interpolation controller determines the B parameter according to the filtered timing error signal;

The signal characteristic parameter modifier determines whether the monitoring signal is within a preset fluctuation range, and if not, adjusts the A parameter and the C parameter such that the monitoring signal is within the preset fluctuation range.
The method according to claim 6, wherein the signal adjuster adjusts the polarization angle of the first and second signals after adjusting the clock phase according to the A parameter, and determines the target positive spectrum information and the target negative spectrum information. ,include:

The signal adjuster multiplies the positive spectral signal of the first signal after adjusting the clock signal by Cos(A) to obtain a first positive spectral signal; multiplying the negative spectral signal of the first signal after adjusting the clock signal Obtaining a first negative spectral signal with Cos(A); multiplying a positive spectral signal of the second signal after adjusting the clock signal by Sin(A) to obtain a second positive spectral signal; Multiplying the negative spectral signal of the second signal by Sin(A) to obtain a second negative spectral signal; combining the first positive spectral signal and the second positive spectral signal to obtain the target positive spectral information, the first negative The spectral signal and the second negative spectral signal are combined to obtain the target negative spectral information.
The method according to claim 7, wherein the phase detector determines the clock error signal according to the target positive spectrum information and the target negative spectrum information, including:

The phase detector determines the clock error signal according to the target positive spectrum information and all spectrum information of the target negative spectrum information.
The method according to any one of claims 6-8, wherein the signal characteristic parameter modifier adjusts the A parameter and the C parameter, including:

The signal characteristic parameter modifier adjusts the A parameter within a first preset adjustment range, and adjusts the C parameter within a second preset adjustment range.
The method of any of claims 6-9, wherein the clock recovery device further comprises a shift register, the method further comprising:

The shift register performs a shift operation on the first signal and the second signal input to the signal clock compensator according to a D parameter, and the D parameter is fed back to the shift register by the interpolation controller, The D parameter is determined by the interpolation controller based on the clock error signal.