WO2018040011A1 - Clock recovery apparatus and clock recovery method - Google Patents

Clock recovery apparatus and clock recovery method Download PDF

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Publication number
WO2018040011A1
WO2018040011A1 PCT/CN2016/097648 CN2016097648W WO2018040011A1 WO 2018040011 A1 WO2018040011 A1 WO 2018040011A1 CN 2016097648 W CN2016097648 W CN 2016097648W WO 2018040011 A1 WO2018040011 A1 WO 2018040011A1
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WIPO (PCT)
Prior art keywords
signal
clock
parameter
spectrum information
target
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PCT/CN2016/097648
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French (fr)
Chinese (zh)
Inventor
万文通
颜敏
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华为技术有限公司
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Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to PCT/CN2016/097648 priority Critical patent/WO2018040011A1/en
Priority to CN201680084263.2A priority patent/CN108886464B/en
Publication of WO2018040011A1 publication Critical patent/WO2018040011A1/en

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    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00Arrangements for synchronising receiver with transmitter
    • H04L7/02Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Definitions

  • the present application relates to the field of optical communications, and in particular, to a clock recovery device and a method for clock recovery.
  • a coherent optical communication system which is a kind of optical communication system, refers to a communication system that uses the coherence of light emitted by a laser to realize heterodyne or homodyne detection at the receiving end, called coherent communication, and realizes information transmission by using the coherent communication. It is called a coherent optical communication system.
  • a coherent optical communication system can communicate information by amplitude, frequency, phase, or polarization. In a communication system such as a coherent optical communication system, after receiving the photoelectric conversion, the receiving end needs to perform algorithm processing in the digital domain.
  • the speed at which the receiving end uses the algorithm to process the data and the speed at which the transmitting end transmits the data should be consistent at all times, so that all the transmitted data at the transmitting end can be processed in time, that is, the clock synchronization is maintained.
  • a coherent optical communication system is taken as an example, wherein a logical structure diagram of a coherent optical communication system is shown in FIG. 1: an analog to digital converter (English name: Analog to Digital Converter, abbreviated: ADC) receives an optical signal after conversion.
  • ADC Analog to Digital Converter
  • xi, xq, yi, yq enter the analog-to-digital converter
  • analog-to-digital converter combines 4 signals into 2 different polarization (x1, y1 polarization) complex signals, combination
  • a clock error signal is input to the loop filter.
  • the output of the loop filter controls the voltage controlled oscillator.
  • the voltage controlled oscillator adjusts the sampling phase and frequency of the analog to digital converter to complete the synchronization of the receiving end.
  • the clock recovery device is an inseparable part of the coherent optical communication system, and its performance directly affects the performance of the entire coherent optical communication system.
  • the clock recovery device for clock recovery to achieve clock synchronization, which is the primary work of the coherent optical communication system.
  • FIG. 2 The schematic diagram of the structure of the clock recovery device in the prior art is shown in FIG. 2.
  • the signal adjuster adjusts the positive angle of the signals of x and y through the A parameter to achieve the effect of the influence, and finally adjusts the signal through the B parameter.
  • the signal characteristic parameter modifier determines the clock synchronization performance according to the mode size of the complex error signal output by the phase detector, for example, the real part of the output signal is the preset maximum
  • the clock synchronization performance is considered to be good, that is, the clock recovery device is considered to be optimal at this time; if the real value is in a fluctuation state, the clock synchronization performance is considered to be poor.
  • the signal characteristic parameter modifier mainly corrects the PMD effect of the signal by the output A parameter value, so that the real part of the complex signal output by the phase detector is maintained at the maximum preset maximum value.
  • the real part of the phase detector output signal only reflects whether the clock performance is affected by the PMD.
  • the real part of the signal output by the phase detector is kept the most preset by adjusting the A parameter.
  • the maximum value however, in addition to the PMD, the dispersion and laser frequency offset have a great influence on the clock synchronization performance, which will affect the output of the phase detector, thereby affecting the output of the loop filter, and finally the clock recovery device.
  • Adjusting the clock according to the B parameter is also affected, that is, the A value can only reduce the influence of the PMD, but if the signal is also affected by factors such as dispersion, the adjusted clock synchronization result is not the best, that is, in the prior art.
  • the clock recovery device is just monitoring and reducing the impact of this single factor of PMD.
  • the present application provides a clock recovery device and a method for clock recovery.
  • the clock recovery device of the present application it is possible to monitor and reduce the influence of factors such as PMD and dispersion.
  • a first aspect of the present application provides a clock recovery apparatus, including a signal clock compensator, a signal adjuster, a phase detector, a loop filter, an interpolation controller, and a signal characteristic parameter modifier, where The functions of each of the above devices are as follows:
  • the signal clock compensator is configured to convert the first signal and the second signal input to the signal clock compensator into a signal in a frequency domain form by using a Fourier transform, wherein the first and second signals are optical signals. Signals of different polarization states, then according to the B parameter fed back to the signal clock compensator by the interpolation controller, and the C parameter of the signal characteristic parameter modifier fed back to the signal clock compensator, the converted first signal and the second signal Performing adjustment of the clock phase, and outputting the first signal and the second signal after adjusting the clock phase to the signal adjuster;
  • the signal adjuster is configured to adjust the polarization angle of the first signal and the second signal after adjusting the clock phase according to the A parameter of the signal characteristic parameter modifier fed back to the signal adjuster, and determine the target positive spectrum information and the target negative spectrum information, Outputting the target positive spectrum information and the target negative spectrum information to the phase detector, wherein the target positive spectrum information includes a polarization-adjusted first signal and a second signal positive spectrum signal, and the target negative spectrum information includes polarization angle adjustment a negative signal of the first signal and the second signal;
  • phase detector configured to determine a clock error signal according to the received target positive spectrum information and the target negative spectrum information, and output the clock error signal to the loop filter
  • a loop filter for filtering the clock error signal, and outputting the filtered clock error signal to the interpolation controller, and integrating the signal of the loop filter with the clock error signal as a monitoring signal Output to signal characteristic parameter modifier;
  • An interpolation controller is configured to determine a B parameter according to the filtered clock error signal, and the signal characteristic parameter modifier is configured to determine whether the monitoring signal is within a preset fluctuation range, and if the signal characteristic parameter modifier determines that the monitoring signal is not in a preset Within the fluctuation range, the A parameter and the C parameter are adjusted so that the monitoring signal is within the preset fluctuation range.
  • the monitoring signal since the monitoring signal is affected by factors such as PMD and dispersion, the monitoring signal will fluctuate. Therefore, by monitoring the monitoring signal, the A parameter and the C parameter are continuously adjusted, so that the monitoring signal is in the preset fluctuation range.
  • the clock recovery device of the present invention it is possible to monitor and reduce the influence of factors such as PMD and dispersion.
  • the signal adjuster adjusts the polarization angle of the first and second signals after adjusting the clock phase according to the A parameter, and determines the target positive spectrum information and the target negative spectrum information, specifically:
  • the calculation method of adjusting the polarization angle is given, and the feasibility of the scheme is improved.
  • the signal conditioner of the prior art after the received A parameter is taken as a cosine, it is necessary to multiply a complex index as an adjustment parameter, that is, the final adjustment parameter is a plural form, and the signal adjuster in the present application only
  • the received A parameter takes the cosine to ensure that the adjustment parameter is always a real number. It can reduce the computational complexity and reduce the power consumption while satisfying the function of adjusting the polarization angle.
  • the phase detector determines the clock error signal according to the target positive spectrum information and the target negative spectrum information, and specifically may refer to determining the clock error signal according to the target positive spectrum information and the entire spectrum information of the target negative spectrum information.
  • the phase detector in the present application determines the clock error signal according to the target positive spectrum information and all the spectrum information of the target negative spectrum information, that is, the first signal and the entire spectrum information of the first signal after adjusting the polarization angle to determine the clock error signal,
  • the first signal and the partial spectrum information of the first signal are adjusted by using the polarization angle to determine the clock error signal, because the use of very little spectrum information causes the phase detector to acquire information when there is a frequency offset. The effectiveness is greatly reduced.
  • the phase detector in this application can avoid this situation by using full frequency domain information.
  • the signal characteristic parameter modifier adjusts the A parameter and the C parameter, specifically, the A parameter is adjusted within the first preset adjustment range, and the C parameter is adjusted within the second preset adjustment range.
  • the adjustment range of the A parameter C parameter can be adjusted according to the actual application situation, that is, the optimal adjustment range can be selected according to the monitoring precision and speed of the actual demand, thereby improving the diversity of the scheme.
  • the clock recovery apparatus may further include a shift register for receiving a parameter determined by the interpolation controller according to the clock error signal, and first inputting to the signal clock compensator according to the D parameter pair The signal and the second signal are shifted.
  • the second aspect of the present application provides a clock recovery method, which is applied to the clock recovery device in the above first aspect, the clock recovery device includes a signal clock compensator, a signal adjuster, a phase detector, and a ring.
  • the functions of each device are as follows:
  • the signal clock compensator converts the first signal and the second signal input to the signal clock compensator into signals in the frequency domain form by using a Fourier transform, wherein the first and second signals are two different polarizations of the optical signal.
  • State signal which is then fed back to the B parameter of the signal clock compensator according to the interpolation controller.
  • the signal characteristic parameter modifier feeds back to the C parameter of the signal clock compensator, adjusts the clock phase of the converted first signal and the second signal, and outputs the first signal and the second signal after adjusting the clock phase to
  • the signal adjuster adjusts the polarization angle of the first signal and the second signal after adjusting the clock phase according to the A parameter of the signal characteristic parameter modifier fed back to the signal adjuster, and determines the target positive spectrum information and the target negative spectrum information.
  • the phase detector determines the clock error signal according to the received target positive spectrum information and the target negative spectrum information, and outputs the clock error signal to the loop filter a loop filter for filtering the clock error signal and filtering the time
  • the error signal is output to the interpolation controller, and the signal obtained by integrating the branch path of the loop filter with the clock error signal is output as a monitoring signal to the signal characteristic parameter modifier; the interpolation controller determines B according to the filtered clock error signal.
  • the signal characteristic parameter modifier determines whether the monitoring signal is within the preset fluctuation range. If the signal characteristic parameter modifier determines that the monitoring signal is not within the preset fluctuation range, then the A parameter and the C parameter are adjusted so that the monitoring signal is preset. Within the range of fluctuations.
  • the signal adjuster adjusts the polarization angle of the first and second signals after adjusting the clock phase according to the A parameter, and determines the target positive spectrum information and the target negative spectrum information, specifically, the clock signal is adjusted.
  • the positive spectrum signal of the first signal is multiplied by Cos(A) to obtain a first positive spectrum signal
  • the negative spectrum signal of the first signal after adjusting the clock signal is multiplied by Cos(A) to obtain a first negative spectrum signal
  • combining the first positive spectral signal and the second positive spectral signal to obtain target positive spectral information
  • combining the first negative spectral information and the second negative spectral information to obtain target negative spectral information is adjusted.
  • the phase detector determines the clock error signal according to the target positive spectrum information and the entire spectrum information of the target negative spectrum information.
  • the signal characteristic parameter modifier specifically adjusts the A parameter within the first preset adjustment range, and adjusts the C parameter within the second preset adjustment range.
  • the clock recovery device further includes a shift register, the shift register receives a parameter determined by the interpolation controller according to the clock error signal, and inputs the signal according to the D parameter pair The first signal and the second signal of the clock compensator perform a shift operation.
  • the monitoring signal since the monitoring signal is affected by factors such as PMD and dispersion, the monitoring signal may fluctuate. Therefore, by monitoring the monitoring signal, the A parameter is continuously adjusted. And the C parameter, so that the monitoring signal is within the preset fluctuation range, that is, the clock recovery device of the present invention can monitor and reduce the influence of factors such as PMD and dispersion.
  • FIG. 1 is a schematic diagram of a logical structure of a conventional coherent optical communication system
  • FIG. 2 is a schematic structural view of a conventional clock recovery device
  • FIG. 3 is a schematic diagram of a logical structure of an embodiment of a clock recovery apparatus according to the present application.
  • FIG. 4 is a schematic diagram showing the logical structure of a loop filter in the clock recovery device of the present application.
  • FIG. 5 is a schematic diagram showing the logical structure of a signal clock compensator in the clock recovery device of the present application
  • FIG. 6 is a schematic diagram showing the logical structure of a signal adjuster in the clock recovery device of the present application.
  • FIG. 7 is a schematic diagram showing the logical structure of a phase detector in a clock recovery device of the present application.
  • FIG. 8 is a schematic diagram of a clock error processing accumulation process of the phase detector of the present application.
  • FIG. 9 is a schematic diagram showing the logical structure of another embodiment of a clock recovery apparatus according to the present application.
  • the embodiment of the present application provides a clock recovery device and a clock recovery method, which can monitor and reduce the influence of factors such as PMD and dispersion.
  • FIG. 3 is a schematic diagram of a logical structure of an embodiment of a clock recovery apparatus according to the present application.
  • the clock recovery apparatus 300 includes a signal clock compensator 301, a signal adjuster 302, a phase detector 303, and a loop filter.
  • the logic structure diagram of the loop filter 304 is shown in FIG. 4, and the loop filter 304 is a common loop filter, where Kp and Ki are The coefficients of the loop filter 304.
  • the filtered output of the loop filter 304 is the signal output 1, that is, the output signal outputted to the interpolation controller 305.
  • the signal derived from the branch circuit of the loop filter 304 is assumed as the monitoring signal, that is, FIG.
  • the signal output 2 described in the above is shown in Figure 4.
  • the dispersion has characteristics of different phase changes as the frequency changes.
  • the phase detector 303 superimposes the clock error phase of the signal.
  • the signal output from the phase detector is thus subject to fluctuations caused by the dispersion.
  • this fluctuation is also accompanied. Therefore, the dispersion causes the value of the signal output 2 of the loop filter to fluctuate.
  • PMD refers to the characteristic that the two polarization states of light have different delays, accompanied by random changes in time. It should be understood that after the phase detector 303 is sent after the signal is affected by the PMD, the output signal of the phase detector 303 is subject to fluctuations caused by different delays between the two polarization states and caused by random variations. That is, the PMD will also cause the value of the output signal 2 of the loop filter 304 to fluctuate.
  • the laser frequency of the transmitter and the receiver is inconsistent, resulting in demodulation of the signal into heterodyne demodulation, and heterodyne demodulation results in a fixed offset of the signal clock component of the phase detector 303.
  • the fixed offset causes the phase detector 303 output to have phase noise, and the magnitude of the phase noise is related to the magnitude of the specific frequency deviation of the two lasers.
  • the signal with phase noise is input to the loop filter 304, which also affects the output value of the signal output 2 of the loop filter 304, causing it to fluctuate.
  • the same result is that the value of the output signal 2 of the loop filter 304 fluctuates. That can pass the loop
  • the change of the signal output 2 of the filter 304 can judge whether the signal clock synchronization performance is normal.
  • the present application proposes a clock recovery device 300 as shown in FIG. 3, which is different from the clock recovery device in the prior art, that is, the clock recovery device shown in FIG.
  • Signal output 2 of filter 304 is used as a feedback adjustment signal characteristic parameter.
  • the signal characteristic parameter modifier 306 controls the operation state of the entire loop by continuously adjusting and outputting the control A parameter and the C parameter, so that the value of the signal output 2 of the loop filter 304 is within the preset fluctuation range, if the loop The value of the signal output 2 of the filter 304 is within the preset fluctuation range, indicating that the clock recovery device 300 has reduced or eliminated the effects of factors such as PMD, dispersion, and the like.
  • the signal clock compensator 301 is configured to convert the first and second signals outputted to the signal clock compensator into signals in the frequency domain form, and then adjust the clock phase of the first signal according to the B parameter and the C parameter, according to the B parameter and the C After adjusting the clock phase of the second signal, the first signal and the second signal are output;
  • the first signal and the second signal are signals of two different polarization states of the optical signal, and the B parameter is fed back to the signal clock compensator 301 by the interpolation controller 305, and the C parameter is fed back to the signal by the signal characteristic parameter modifier 306.
  • Clock compensator 301 is
  • the signal clock compensator compensates for the clock offset of the input signal.
  • the purpose of the compensation is to have the signal sampled by a sampler of a fixed sampling multiple.
  • the signal clock compensator in the present application can convert the time domain discrete signal after the ADC conversion into a frequency domain form signal through a fast Fourier transform (abbreviation: FFT), and then according to the signal.
  • FFT fast Fourier transform
  • the B parameter fed back by the interpolation controller 305 and the C parameter fed back by the signal characteristic parameter modifier 306 adjust the clock phase of the input signal, and output the signal after the clock phase is adjusted.
  • the purpose of the signal clock compensator 301 is to perform clock offset compensation on the input signal. The purpose of the compensation is to allow the signal to be sampled by a sampler of a fixed sampling multiple.
  • FIG. 5 is a schematic diagram showing the logical structure of a signal clock compensator in the clock recovery apparatus of the present application, where Exp represents a natural index.
  • the first signal is an X signal and the second signal is a Y signal.
  • the signal clock compensator 301 the X and Y signals are subjected to FFT, and then multiplied by a phase variable, the phase The variable consists of B and C parameters.
  • B parameter It is used for signal clock adjustment
  • the C parameter is mainly to adjust the influence of dispersion.
  • the sampling rate of the signal is adjusted.
  • the signal clock compensator follows the B parameter and the C parameter. , to achieve a fixed sampling rate of the sampling rate of the target.
  • the clock synchronization performance can be considered normal, that is, the influence of the clock output of the clock output has been reduced or has been eliminated.
  • the existing signal clock compensator uses the time domain interpolation filter to complete the clock correction of the input signal, and the time domain interpolation filter selects different number of filter coefficients according to different precision requirements, and the coefficient is directly
  • the chip resources of the signal clock compensator at the time of implementation are determined. For example, suppose the existing signal clock compensator performs time domain interpolation with 8 filter tap coefficients for 100 data points, that is, moving a time phase, then 800 multiplication operations are required. However, in the signal clock compensator of the present application, the signal input to the signal clock compensator is converted into a signal in the form of a frequency domain, and then the clock is corrected. In the frequency domain, only 100 multiplication operations are required. That is, the existing signal clock compensator wastes a large number of multipliers with respect to the signal clock compensator in the present application.
  • the clock recovery device in the present application is used to take the output signal of the signal clock compensator 301 as a feedback signal, and output it to the signal adjuster 302;
  • the signal adjuster 302 is configured to adjust the polarization angle of the X and Y signals after adjusting the clock phase according to the A parameter, and determine the target positive spectrum information and the target negative spectrum information.
  • the A parameter is fed back to the signal adjuster 302 by the signal characteristic parameter modifier 306.
  • the target positive spectrum information includes a positive spectrum signal of the X signal and the Y signal after the polarization angle adjustment, and the target negative spectrum information includes the polarization angle adjustment. Negative spectrum signal of X signal and Y signal.
  • FIG. 6 is a logic of a signal adjuster in the clock recovery apparatus of the present application. Schematic:
  • the positive spectrum signal of the X signal after adjusting the clock signal is multiplied by Cos(A) to obtain the first positive spectrum signal
  • the negative spectrum signal of the X signal after adjusting the clock signal is multiplied by Cos(A) to obtain the first a negative spectral signal
  • the target positive spectrum information and the target negative spectrum information are output to the phase detector.
  • the output signal of the signal clock compensator 301 is taken out as a feedback signal, and is output to the signal adjuster 302, that is, the X signal and the Y signal after adjusting the clock signal can be fed back to the signal adjuster 302.
  • the signal adjuster 302 receives the X signal and the Y signal after adjusting the clock signal, preferably, the polarization angle can be adjusted by the manner as shown in FIG. 6.
  • the difference between the signal adjuster in the present application and the existing signal adjuster is that the adjustment parameters are different.
  • the technology takes the cosine of the received A parameter and needs to multiply a complex index as the adjustment parameter, that is, finally
  • the adjustment parameter is in the plural form, and the present invention only takes the cosine operation of the received A parameter to ensure that the adjustment parameter is always a real number.
  • the adjustment function can be satisfied while reducing the computational complexity, thereby reducing system power consumption.
  • the signal adjuster can obtain other adjustment parameters according to the A parameter, in addition to taking the cosine as the adjustment parameter.
  • the signal adjuster takes the received A parameter into a sinusoidal operation, as long as the final decision can be made according to the A parameter.
  • the adjustment of the A parameter can make up for the influence of the PMD, and is not limited herein.
  • the phase detector 303 is configured to perform phase discrimination on the signal input from the signal adjuster 302 to the phase detector 303 to obtain a clock phase difference;
  • the phase detector 303 is configured to perform phase discrimination based on the target positive spectrum information and the partial spectrum information or the entire spectrum information of the target negative spectrum information, and determine a clock error signal, preferably, according to the target positive spectrum information and The entire spectrum information of the target negative spectrum information is phase-detected.
  • the phase detector 303 mainly performs phase discrimination on the signal input to the phase detector, and may specifically refer to a phase detector based on the Godard algorithm, and may also be a phase detector based on the gardner algorithm, etc., which is not limited herein. , depending on the form of the signal entering the phase detector, but as long as the phase detector 303 is adjusted by the signal
  • the input signal of the whole device 302 can determine the clock error signal.
  • the phase detector can perform phase discrimination based on the target positive spectrum information and the entire spectrum information of the target negative spectrum information to determine the clock. Error signal.
  • FIG. 7 is a schematic diagram of the logic structure of the phase detector in the clock recovery apparatus of the present application. After the target positive spectrum signal and the target negative spectrum signal output from the signal adjuster 302 to the phase detector 303 are spectrally combined, The combined spectrum signal is sequence-expanded, and the imaginary part, that is, the clock error signal is obtained after being accumulated by the clock phase error processing, and the obtained clock error signal is output to the loop filter 304.
  • the target positive spectrum information can be assumed to be F(1), F(2), F(3)...F(N). /2
  • the target negative spectrum signal is F(N/2+1), F(N/2+2), F(N/2+3)...F(N)
  • the phase detector 303 passes the target positive
  • the spectrum information and the target negative spectrum information are combined and combined into a complete frequency domain signal as F(1), F(2), F(3)...F(N).
  • the specific value needs to be a compromise value according to the system, which is not limited here.
  • the extended sequence is F(N-1), F(N), F(1), F(2). , F(3)...F(N), F(1), F(2).
  • the clock phase error processing is accumulated for the extended sequence, and the specific processing accumulation method is as shown in FIG. 8, that is, the extended sequence is conjugated according to the manner of FIG. 8, and the final accumulated result is taken as the imaginary part. That is, the clock error signal is output to the loop filter 304.
  • the loop filter 304 is configured to filter the clock error signal, and output the filtered clock error signal to the interpolation controller 305, and also use the signal extracted from the product branch path of the loop filter 304 as a monitoring signal.
  • the monitor signal is fed back to the signal characteristic parameter modifier 306.
  • the clock error signal enters the loop filter 304 and is divided into two signals.
  • One signal is multiplied by the coefficient Kp, one is multiplied by Ki, and the shunt multiplied by Ki is accumulated in delay, and accumulated. of The result is added after the result of the Kp path, that is, the filtered clock error signal, that is, the signal output 1 shown in FIG. 4, and the delay accumulation is separately taken out as a monitoring signal, that is, the signal output 2 shown in FIG. .
  • Kp and Ki coefficients are the coefficients of the loop filter, and the specific coefficients are adjusted according to the condition of the entire loop system, which is not limited herein. I will not go into details.
  • the interpolation controller 305 is configured to determine a B parameter according to the filtered clock error signal, and output the B parameter to the signal clock compensator 301;
  • the interpolation controller can input the incoming clock error signal for interpolation, thereby determining the B parameter, and then outputting the B parameter to the signal clock compensation compensator 301.
  • the interpolation controller 305 After the interpolation controller 305 receives the clock error signal output by the loop filter, here assumed to be T, the interpolation controller 305 determines whether the T is greater than 1 or less than -1;
  • the signal characteristic parameter modifier 306 is configured to determine whether the monitoring signal is within a preset fluctuation range; if it is determined that the monitoring signal is not within the preset fluctuation range, adjusting the A parameter in the first preset adjustment range, in the second preset
  • the C parameter is adjusted within the adjustment range, and the A parameter is fed back to the signal adjuster 302, and the C parameter is fed back to the signal clock compensator 301 so that the monitoring signal is within the preset fluctuation range.
  • the signal characteristic parameter modifier 306 receives the above-mentioned monitoring signal, that is, the signal output 2 of the loop filter, it is determined whether the monitoring signal is within the preset fluctuation range. It can be seen from the foregoing description that when the monitoring signal generates fluctuation, it is affected by factors such as PMD and dispersion. At this time, the signal characteristic parameter modifier in the present application dynamically adjusts the A parameter and the C parameter to make the last monitoring signal. The output is within the preset fluctuation range, that is, by continuously scanning the A and C parameters to eliminate or reduce the influence of PMD, dispersion and other factors.
  • the preset fluctuation range can be configured according to empirical data. For example, the values of the long-term output generally fluctuate within +/- 0.1. At this time, the clock synchronization performance is considered normal. If it is greater than this value, then the A and C parameters are scanned and adjusted to find the A and C parameters to satisfy this 0.1. Requirements.
  • the signal characteristic parameter modifier 306 can further adjust the A parameter within the first preset adjustment range, and adjust the C parameter within the second preset adjustment range, so that the monitoring signal is within the preset fluctuation range, that is, in advance Scan the A and C parameters within the range to eliminate or reduce the effects of PMD, dispersion and other factors.
  • the first preset adjustment range is: -45 to +45
  • the step degree is 1
  • the second preset range is 0 to 1
  • the step degree is 1
  • the specific scanning process is as follows:
  • a parameter coarsely select A parameter in the first preset adjustment range, for example -45, scan C parameter, C parameter is within the second preset range, step is less than 1 value, for example, C parameter is taken
  • the value can be: 0.1, 0.2...1.
  • step b The change A parameter is -44.
  • step a the operation of scanning the C parameter is repeated, and the output value of the signal output 2 of the loop filter 304 is also saved, and the variance is calculated and set to std2.
  • the signal characteristic parameter modifier further continues to scan on the basis of the above scanning, as shown by d:
  • step 1 The scanning according to step 1 is repeated according to the range set by d, and the change of the signal is always tracked by such scanning.
  • the scanning range described in the ae step is a preferred scanning scheme, but is not limited to the present application.
  • the signal characteristic parameter modifier 306 can be selected according to the actual application, for example, according to the accuracy and speed of the scanning. , specifically here is not limited.
  • the clock recovery device of the present application may further include a shift register.
  • FIG. 9 is a schematic diagram of another embodiment of a clock recovery device according to the present application.
  • the recovery device 900 includes a signal clock compensator 901 and a signal adjuster. 902, phase detector 903, loop filter 904, interpolation controller 905, signal characteristic parameter modifier 906, and shift register 907:
  • the functions of the signal clock compensator 901, the signal adjuster 902, the phase detector 903, the loop filter 904, the interpolation controller 905, and the signal characteristic parameter modifier 906 in the present clock recovery apparatus can be referred to the above embodiments. Description, which will not be described here.
  • the interpolation controller 905 determines the B parameter according to the monitoring signal, and the interpolation controller further returns the D parameter to the shift register 907 according to the monitoring signal D parameter.
  • the integer when it is determined that the monitoring signal is greater than 1, the integer is further taken down according to the monitoring signal, and the obtained integer, that is, the D parameter is sent to the shift register 907 shift signal;
  • the rounded integer i.e., the D parameter, is sent to the shift register 907 to shift the signal.
  • the clock recovery device in the present application shifts the first signal and the second signal according to the D parameter, and then outputs the signal to the signal clock compensator.
  • the D parameter is fed back to the shift register by the interpolation controller; the signal clock compensator performs clock phase adjustment on the first and second signals input to the signal clock compensator according to the B parameter and the C parameter, and outputs the adjusted clock phase.
  • the first and second signals wherein the first and second signals are signals of two different polarization states of the optical signal, the B parameter is fed back to the signal clock compensator by the interpolation controller, and the C parameter is fed back by the signal characteristic parameter modifier to a signal clock compensator; the signal adjuster adjusts a polarization angle of the first and second signals after adjusting the clock phase according to the A parameter, and outputs the determined target positive spectrum information and the target negative spectrum information to the phase detector, wherein The A parameter is fed back to the signal adjuster by the signal characteristic parameter modifier; the phase detector is based on the target positive spectrum information and the target negative spectrum information.
  • the loop filter filters the clock error signal, and outputs the filtered clock error signal to the interpolation controller, from the product branch of the loop filter
  • the extracted signal is used as a monitoring signal, and the monitoring signal is fed back to the signal characteristic parameter modifier;
  • the interpolation controller determines the B parameter and the D parameter according to the filtered timing error signal, and outputs the B parameter to the signal clock compensator, and the D parameter Feedback to the shift register;
  • the signal characteristic parameter modifier determines whether the monitoring signal is within the preset fluctuation range, and if not, dynamically adjusts the A parameter and the C parameter so that the monitoring signal is within the preset fluctuation range.
  • the monitoring signal may fluctuate. Therefore, by monitoring the monitoring signal, the A parameter and the C parameter are continuously adjusted, so that the monitoring signal is within the preset fluctuation range, that is, by the clock recovery device of the present invention. Monitor and reduce the effects of factors such as PMD and dispersion.
  • a clock recovery device in the present application has been described above.
  • the following describes a method for clock recovery in the present application.
  • the clock recovery method is applied to the clock recovery device.
  • the method includes:
  • the shift register performs a shift operation on the first signal and the second signal according to the parameter D, wherein the D parameter and the D parameter are fed back to the shift register by the interpolation controller;
  • the signal clock compensator adjusts the clock phase of the first and second signals input to the signal clock compensator according to the B parameter and the C parameter, and outputs the first and second signals after adjusting the clock phase, the first and second signals.
  • the B parameter is fed back to the signal clock compensator by the interpolation controller
  • the C parameter is fed back to the signal clock compensator by the signal characteristic parameter modifier
  • the signal adjuster adjusts the polarization angles of the first and second signals after adjusting the clock phase according to the A parameter, and outputs the determined target positive spectrum information and the target negative spectrum information to the phase detector, wherein the A parameter is determined by the signal characteristic
  • the parameter modifier feeds back to the signal adjuster, and the target positive spectrum information includes a first signal and a second signal positive spectrum signal after the polarization angle adjustment, and the target negative spectrum information includes the first signal and the second signal after the polarization angle adjustment.
  • the phase detector determines a clock error signal according to the target positive spectrum information and the target negative spectrum, and outputs the clock error signal to the loop filter;
  • the loop filter filters the clock error signal, and outputs the filtered clock error signal to the interpolation controller.
  • the signal extracted from the product branch of the loop filter is used as a monitoring signal, and the monitoring signal is fed back to the signal characteristic parameter. modifier;
  • the interpolation controller determines the B parameter and the D parameter according to the filtered timing error signal, and outputs the B parameter to the signal clock compensator, and feeds the D parameter to the shift register;
  • the signal characteristic parameter modifier determines whether the monitoring signal is within the preset fluctuation range, and if not, dynamically adjusts the A parameter and the C parameter so that the monitoring signal is within the preset fluctuation range.
  • the disclosed system, modules and squares The law can be implemented in other ways.
  • the device embodiments described above are merely illustrative.
  • the division of the modules is only a logical function division.
  • there may be another division manner for example, multiple units or components may be combined or Can be integrated into another system, or some features can be ignored or not executed.
  • the mutual coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interface, device or unit, and may be in an electrical, mechanical or other form.
  • the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of the embodiment.
  • each functional module in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.
  • the above integrated unit can be implemented in the form of hardware or in the form of a software functional unit.
  • the integrated modules when implemented in the form of software functional units and sold or used as separate products, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present application, in essence or the contribution to the prior art, or all or part of the technical solution may be embodied in the form of a software product stored in a storage medium.
  • a number of instructions are included to cause a computer device (which may be a personal computer, server, or network device, etc.) to perform all or part of the steps of the methods described in various embodiments of the present application.
  • the foregoing storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk, and the like. .

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Abstract

A clock recovery apparatus (300) and a clock recovery method. In the clock recovery apparatus (300), a signal clock compensator (301) is configured to adjust clock phases of a first signal and a second signal in the frequency domain according to a parameter B and a parameter C, and output the first signal and the second signal; a signal adjuster (302) is configured to adjust, according to a parameter A, polarization angles of the first signal and the second signal for which the clock phases have been adjusted, and determine target positive spectrum information and target negative spectrum information; a phase discriminator (303) is configured to determine a clock error signal according to the target positive and negative spectrum information; a loop filter (304) is configured to filter the clock error signal, and further configured to lead out a signal from an integration branch of the loop filter (304) as a monitored signal; an interpolation controller (305) is configured to determine the parameter B according to the filtered clock error signal; and a signal characteristic parameter modifier (306) is configured to determine whether the monitored signal is within a preset fluctuation range, and if not, adjust the parameter A and the parameter C so that the monitored signal is within the preset fluctuation range.

Description

一种时钟恢复装置以及时钟恢复的方法Clock recovery device and method for clock recovery 技术领域Technical field
本申请涉及光通信领域,尤其涉及到一种时钟恢复装置以及时钟恢复的方法。The present application relates to the field of optical communications, and in particular, to a clock recovery device and a method for clock recovery.
背景技术Background technique
相干光通信系统,为光通信系统的一种,指利用激光器发出的光的相干性,在接收端实现外差或零差检测,称为相干通信,而利用该相干通信实现信息传送的通信系统称为相干光通信系统。相干光通信系统可以通过振幅、频率、相位或偏振态来传递信息。在相干光通信系统等通信系统中,接收端在进行完光电转换后,需要进行数字域的算法处理。接收端利用算法处理数据的速度与发送端发射数据的速度应该时时刻刻保持一致,这样才能保障发送端所有发射的数据都及时的得到处理,即保持时钟同步。例如,以相干光通信系统为例,其中,相干光通信系统的一个逻辑结构示意图如图1所示:模拟数字转换器(英文全称:Analog to Digital Converter,缩写:ADC)接收光信号转换后的4路电信号,如图1所示的xi,xq,yi,yq,进入模拟数字转换器,模拟数字转换器把4路信号组合成2路不同偏振(x1、y1偏振)的复数信号,组合方式为(x1=xi+jxq),(y1=yi+jyq),x1、y1进入色散估计与补偿模块完成了光色散损伤的消除,输出x2、y2,接着输入时钟恢复装置,时钟恢复装置输出一个时钟误差信号,该时钟误差信号输入到环路滤波器,环路滤波器的输出控制压控振荡器,压控振荡器调节模拟数字转换器的采样相位与频率,从而完成接收端的同步。即只有这种采样相位调整正确的信号才能最优地被接收端接收。可见时钟恢复装置是相干光通信系统中一个不可分割的部分,其性能直接影响整个相干光通信系统的性能。A coherent optical communication system, which is a kind of optical communication system, refers to a communication system that uses the coherence of light emitted by a laser to realize heterodyne or homodyne detection at the receiving end, called coherent communication, and realizes information transmission by using the coherent communication. It is called a coherent optical communication system. A coherent optical communication system can communicate information by amplitude, frequency, phase, or polarization. In a communication system such as a coherent optical communication system, after receiving the photoelectric conversion, the receiving end needs to perform algorithm processing in the digital domain. The speed at which the receiving end uses the algorithm to process the data and the speed at which the transmitting end transmits the data should be consistent at all times, so that all the transmitted data at the transmitting end can be processed in time, that is, the clock synchronization is maintained. For example, a coherent optical communication system is taken as an example, wherein a logical structure diagram of a coherent optical communication system is shown in FIG. 1: an analog to digital converter (English name: Analog to Digital Converter, abbreviated: ADC) receives an optical signal after conversion. 4 electrical signals, as shown in Figure 1, xi, xq, yi, yq, enter the analog-to-digital converter, analog-to-digital converter combines 4 signals into 2 different polarization (x1, y1 polarization) complex signals, combination The mode is (x1=xi+jxq), (y1=yi+jyq), x1, y1 enter the dispersion estimation and compensation module to complete the elimination of optical dispersion damage, output x2, y2, and then input clock recovery device, clock recovery device output A clock error signal is input to the loop filter. The output of the loop filter controls the voltage controlled oscillator. The voltage controlled oscillator adjusts the sampling phase and frequency of the analog to digital converter to complete the synchronization of the receiving end. That is, only such a signal with the correct phase of the sampling phase can be optimally received by the receiving end. It can be seen that the clock recovery device is an inseparable part of the coherent optical communication system, and its performance directly affects the performance of the entire coherent optical communication system.
即相干光通信系统中,在接收到ADC采集到的信号后,需要利用时钟恢复装置进行时钟恢复,达到时钟同步,时钟同步是相干光通信系统首要完成的工作。That is, in the coherent optical communication system, after receiving the signal collected by the ADC, it is necessary to use the clock recovery device for clock recovery to achieve clock synchronization, which is the primary work of the coherent optical communication system.
然而,在相干光通信系统中,通常会受到补偿偏振模色散(英文全称: Polarization Mode Dispersion,缩写:PMD),色散以及激光器频率偏移等影响。现有技术中的时钟恢复装置结构示意图如图2所示,在图2中,信号调整器通过A参数调整x,y两路信号的偏正角度,达到影响的作用,最终通过B参数调整信号的时钟,然而,现有技术中的时钟恢复装置中,信号特性参数修改器根据鉴相器输出的复数误差信号的模的大小来判断时钟同步性能,比如输出的信号的实部为预设最大值时,则认为时钟同步性能好,即认为这个时候时钟恢复装置工作于最佳;如果该实部值处于波动状态,则认为时钟同步性能差。但是信号特性参数修改器主要是通过输出的A参数值纠正信号的PMD影响,使鉴相器输出的复数信号的实部保持最预置最大值。即现有技术中,鉴相器输出信号的实部只是反映时钟性能有无受到PMD的影响,当受到PMD影响时,则通过调节A参数使得鉴相器输出的信号的实部保持最预置最大值,然而,除了PMD外,色散以及激光器频率偏移等对时钟同步性能的影响也很大,其会对鉴相器的输出产生影响,进而影响环路滤波器的输出,最终时钟恢复装置根据B参数调整时钟也受到了影响,即通过A值只能减少PMD的影响,但若信号还受色散等因素影响时,此时调整的时钟同步结果并不是最好的,即现有技术中的时钟恢复装置只是监控,并减少PMD这单一因素的影响。However, in coherent optical communication systems, it is usually compensated for polarization mode dispersion (English full name: Polarization Mode Dispersion, abbreviated: PMD), dispersion and laser frequency offset effects. The schematic diagram of the structure of the clock recovery device in the prior art is shown in FIG. 2. In FIG. 2, the signal adjuster adjusts the positive angle of the signals of x and y through the A parameter to achieve the effect of the influence, and finally adjusts the signal through the B parameter. The clock, however, in the prior art clock recovery device, the signal characteristic parameter modifier determines the clock synchronization performance according to the mode size of the complex error signal output by the phase detector, for example, the real part of the output signal is the preset maximum When the value is considered, the clock synchronization performance is considered to be good, that is, the clock recovery device is considered to be optimal at this time; if the real value is in a fluctuation state, the clock synchronization performance is considered to be poor. However, the signal characteristic parameter modifier mainly corrects the PMD effect of the signal by the output A parameter value, so that the real part of the complex signal output by the phase detector is maintained at the maximum preset maximum value. That is, in the prior art, the real part of the phase detector output signal only reflects whether the clock performance is affected by the PMD. When it is affected by the PMD, the real part of the signal output by the phase detector is kept the most preset by adjusting the A parameter. The maximum value, however, in addition to the PMD, the dispersion and laser frequency offset have a great influence on the clock synchronization performance, which will affect the output of the phase detector, thereby affecting the output of the loop filter, and finally the clock recovery device. Adjusting the clock according to the B parameter is also affected, that is, the A value can only reduce the influence of the PMD, but if the signal is also affected by factors such as dispersion, the adjusted clock synchronization result is not the best, that is, in the prior art. The clock recovery device is just monitoring and reducing the impact of this single factor of PMD.
发明内容Summary of the invention
本申请提供了一种时钟恢复装置以及时钟恢复的方法,通过本申请的时钟恢复装置,可以监控,并减少PMD、色散等因素影响。The present application provides a clock recovery device and a method for clock recovery. With the clock recovery device of the present application, it is possible to monitor and reduce the influence of factors such as PMD and dispersion.
本申请第一方面提供了一种时钟恢复装置,该时钟恢复装置中,包括信号时钟补偿器、信号调整器、鉴相器、环路滤波器、插值控制器以及信号特性参数修改器,其中,上述各个器件的功能如下描述所示:A first aspect of the present application provides a clock recovery apparatus, including a signal clock compensator, a signal adjuster, a phase detector, a loop filter, an interpolation controller, and a signal characteristic parameter modifier, where The functions of each of the above devices are as follows:
其中,信号时钟补偿器,用于利用傅里叶变换,将输入至信号时钟补偿器的第一信号、第二信号转换为频域形式的信号,其中,第一、第二信号为光信号两个不同偏振态的信号,接着根据插值控制器反馈至信号时钟补偿器的B参数,以及信号特性参数修改器反馈至信号时钟补偿器的C参数,对经过转换后的第一信号、第二信号进行时钟相位的调整,并将调整时钟相位后的第一信号、第二信号输出至信号调整器; The signal clock compensator is configured to convert the first signal and the second signal input to the signal clock compensator into a signal in a frequency domain form by using a Fourier transform, wherein the first and second signals are optical signals. Signals of different polarization states, then according to the B parameter fed back to the signal clock compensator by the interpolation controller, and the C parameter of the signal characteristic parameter modifier fed back to the signal clock compensator, the converted first signal and the second signal Performing adjustment of the clock phase, and outputting the first signal and the second signal after adjusting the clock phase to the signal adjuster;
信号调整器,用于根据信号特性参数修改器反馈至信号调整器的A参数对调整时钟相位后的第一信号、第二信号进行偏振角度调整,并确定目标正频谱信息以及目标负频谱信息,将目标正频谱信息以及目标负频谱信息输出至鉴相器,其中,目标正频谱信息包括经过偏振角度调整后的第一信号、第二信号的正频谱信号,目标负频谱信息包括经过偏振角度调整后的第一信号、第二信号的负频谱信号;The signal adjuster is configured to adjust the polarization angle of the first signal and the second signal after adjusting the clock phase according to the A parameter of the signal characteristic parameter modifier fed back to the signal adjuster, and determine the target positive spectrum information and the target negative spectrum information, Outputting the target positive spectrum information and the target negative spectrum information to the phase detector, wherein the target positive spectrum information includes a polarization-adjusted first signal and a second signal positive spectrum signal, and the target negative spectrum information includes polarization angle adjustment a negative signal of the first signal and the second signal;
鉴相器,用于根据接收到的目标正频谱信息以及目标负频谱信息确定时钟误差信号,并将所述时钟误差信号输出至所述环路滤波器;a phase detector, configured to determine a clock error signal according to the received target positive spectrum information and the target negative spectrum information, and output the clock error signal to the loop filter;
环路滤波器,用于对时钟误差信号进行滤波,并将滤波后的时钟误差信号输出至插值控制器,并将环路滤波器的积分支路对时钟误差信号进行积分后的信号作为监控信号输出至信号特性参数修改器;a loop filter for filtering the clock error signal, and outputting the filtered clock error signal to the interpolation controller, and integrating the signal of the loop filter with the clock error signal as a monitoring signal Output to signal characteristic parameter modifier;
插值控制器,用于根据滤波后的时钟误差信号确定B参数,信号特性参数修改器,用于判断监控信号是否在预置波动范围内,若信号特性参数修改器确定监控信号并不是在预置波动范围内,则调整A参数以及C参数,使得监控信号在预置波动范围内。An interpolation controller is configured to determine a B parameter according to the filtered clock error signal, and the signal characteristic parameter modifier is configured to determine whether the monitoring signal is within a preset fluctuation range, and if the signal characteristic parameter modifier determines that the monitoring signal is not in a preset Within the fluctuation range, the A parameter and the C parameter are adjusted so that the monitoring signal is within the preset fluctuation range.
由以上技术方案可以看出,由于监控信号受到PMD、色散等因素的影响会导致监控信号产生波动,因此通过监控该监控信号,不断的调整A参数以及C参数,使得监控信号在预置波动范围内,即通过本发明时钟恢复装置,可以监控并减少PMD、色散等因素影响。It can be seen from the above technical solution that since the monitoring signal is affected by factors such as PMD and dispersion, the monitoring signal will fluctuate. Therefore, by monitoring the monitoring signal, the A parameter and the C parameter are continuously adjusted, so that the monitoring signal is in the preset fluctuation range. Through the clock recovery device of the present invention, it is possible to monitor and reduce the influence of factors such as PMD and dispersion.
在一种可能的实现中,信号调整器根据A参数对调整时钟相位后的所述第一、第二信号进行偏振角度调整,确定目标正频谱信息以及目标负频谱信息,具体是指:In a possible implementation, the signal adjuster adjusts the polarization angle of the first and second signals after adjusting the clock phase according to the A parameter, and determines the target positive spectrum information and the target negative spectrum information, specifically:
将调整时钟信号后的第一信号的正频谱信号乘以Cos(A),获得第一正频谱信号;将调整时钟信号后的第一信号的负频谱信号乘以Cos(A),获得第一负频谱信号;将调整时钟信号后的第二信号的正频谱信号乘以Sin(A),获得第二正频谱信号;将调整时钟信号后的第二信号的负频谱信号乘以Sin(A),获得第二负频谱信号;将第一正频谱信号以及第二正频谱信号合并得到目标正频谱信息;将第一负频谱信号以及第二负频谱信号合并得到目标负频谱信息。Multiplying the positive spectral signal of the first signal after adjusting the clock signal by Cos(A) to obtain a first positive spectral signal; multiplying the negative spectral signal of the first signal after adjusting the clock signal by Cos(A) to obtain the first a negative spectrum signal; multiplying the positive spectrum signal of the second signal after adjusting the clock signal by Sin(A) to obtain a second positive spectrum signal; multiplying the negative spectrum signal of the second signal after adjusting the clock signal by Sin(A) Obtaining a second negative spectral signal; combining the first positive spectral signal and the second positive spectral signal to obtain target positive spectral information; and combining the first negative spectral signal and the second negative spectral signal to obtain target negative spectral information.
即给出了具体调整偏振角度的计算方式,提高了方案的可实施性,另外, 在现有技术中的信号调整器中,是把接收到的A参数取余弦后需要再乘一个复指数作为调节参数,即最终的调节参数为复数形式,而本申请中的信号调整器只把接收到的A参数取余弦保证了调节参数始终是实数。可以在满足调整偏振角度功能的同时也减少了计算复杂度,进而减少功耗。That is, the calculation method of adjusting the polarization angle is given, and the feasibility of the scheme is improved. In the signal conditioner of the prior art, after the received A parameter is taken as a cosine, it is necessary to multiply a complex index as an adjustment parameter, that is, the final adjustment parameter is a plural form, and the signal adjuster in the present application only The received A parameter takes the cosine to ensure that the adjustment parameter is always a real number. It can reduce the computational complexity and reduce the power consumption while satisfying the function of adjusting the polarization angle.
在一种可能的实现中,鉴相器根据目标正频谱信息以及目标负频谱信息确定时钟误差信号,具体可以是指根据目标正频谱信息以及目标负频谱信息的全部频谱信息确定时钟误差信号。In a possible implementation, the phase detector determines the clock error signal according to the target positive spectrum information and the target negative spectrum information, and specifically may refer to determining the clock error signal according to the target positive spectrum information and the entire spectrum information of the target negative spectrum information.
即本申请中的鉴相器是根据目标正频谱信息以及目标负频谱信息的全部频谱信息确定时钟误差信号,即调整偏振角度后第一信号以及第一信号的全部频谱信息来确定时钟误差信号,而现有技术中则是利用调整偏振角度后第一信号以及第一信号的部分频谱信息来确定时钟误差信号,正因为用了很少频谱信息导致在有频率偏移的时候鉴相器获取信息的有效性大大降低。本申请中的鉴相器用了全频域信息就可以规避了这个情况发生。That is, the phase detector in the present application determines the clock error signal according to the target positive spectrum information and all the spectrum information of the target negative spectrum information, that is, the first signal and the entire spectrum information of the first signal after adjusting the polarization angle to determine the clock error signal, In the prior art, the first signal and the partial spectrum information of the first signal are adjusted by using the polarization angle to determine the clock error signal, because the use of very little spectrum information causes the phase detector to acquire information when there is a frequency offset. The effectiveness is greatly reduced. The phase detector in this application can avoid this situation by using full frequency domain information.
在一种可能的实现中,信号特性参数修改器调整A参数以及C参数,具体可以是在第一预置调整范围内调整A参数,在第二预置调整范围内调整C参数。In a possible implementation, the signal characteristic parameter modifier adjusts the A parameter and the C parameter, specifically, the A parameter is adjusted within the first preset adjustment range, and the C parameter is adjusted within the second preset adjustment range.
即可以根据实际应用情况来调整A参数C参数的调整范围,即可以根据实际需求的监控精度以及速度来折中选取最优的调整范围,提高了方案的多样性。That is, the adjustment range of the A parameter C parameter can be adjusted according to the actual application situation, that is, the optimal adjustment range can be selected according to the monitoring precision and speed of the actual demand, thereby improving the diversity of the scheme.
在一种可能的实现中,该时钟恢复装置还可以包括移位寄存器,该移位寄存器用于接收插值控制器根据时钟误差信号确定的参数,根据D参数对输入至信号时钟补偿器的第一信号以及第二信号进行移位操作。In a possible implementation, the clock recovery apparatus may further include a shift register for receiving a parameter determined by the interpolation controller according to the clock error signal, and first inputting to the signal clock compensator according to the D parameter pair The signal and the second signal are shifted.
本申请第二方面提供了一种时钟恢复的方法,该时钟恢复的方法应用于上述第一方面中的时钟恢复装置,该时钟恢复装置包括信号时钟补偿器、信号调整器、鉴相器、环路滤波器、插值控制器以及信号特性参数修改器,该时钟恢复方法中,各个器件的功能如下描述:The second aspect of the present application provides a clock recovery method, which is applied to the clock recovery device in the above first aspect, the clock recovery device includes a signal clock compensator, a signal adjuster, a phase detector, and a ring. The path filter, the interpolation controller, and the signal characteristic parameter modifier. In the clock recovery method, the functions of each device are as follows:
其中,信号时钟补偿器利用傅里叶变换,将输入至信号时钟补偿器的第一信号、第二信号转换为频域形式的信号,其中,第一、第二信号为光信号两个不同偏振态的信号,接着根据插值控制器反馈至信号时钟补偿器的B参数, 以及信号特性参数修改器反馈至信号时钟补偿器的C参数,对经过转换后的第一信号、第二信号进行时钟相位的调整,并将调整时钟相位后的第一信号、第二信号输出至信号调整器;信号调整器根据信号特性参数修改器反馈至信号调整器的A参数对调整时钟相位后的第一信号、第二信号进行偏振角度调整,并确定目标正频谱信息以及目标负频谱信息,将目标正频谱信息以及目标负频谱信息输出至鉴相器,其中,目标正频谱信息包括经过偏振角度调整后的第一信号、第二信号的正频谱信号,目标负频谱信息包括经过偏振角度调整后的第一信号、第二信号的负频谱信号;鉴相器根据接收到的目标正频谱信息以及目标负频谱信息确定时钟误差信号,并将所述时钟误差信号输出至所述环路滤波器;环路滤波器,用于对时钟误差信号进行滤波,并将滤波后的时钟误差信号输出至插值控制器,并将环路滤波器的积分支路对时钟误差信号进行积分后的信号作为监控信号输出至信号特性参数修改器;插值控制器根据滤波后的时钟误差信号确定B参数;信号特性参数修改器判断监控信号是否在预置波动范围内,若信号特性参数修改器确定监控信号并不是在预置波动范围内,则调整A参数以及C参数,使得监控信号在预置波动范围内。The signal clock compensator converts the first signal and the second signal input to the signal clock compensator into signals in the frequency domain form by using a Fourier transform, wherein the first and second signals are two different polarizations of the optical signal. State signal, which is then fed back to the B parameter of the signal clock compensator according to the interpolation controller. And the signal characteristic parameter modifier feeds back to the C parameter of the signal clock compensator, adjusts the clock phase of the converted first signal and the second signal, and outputs the first signal and the second signal after adjusting the clock phase to The signal adjuster adjusts the polarization angle of the first signal and the second signal after adjusting the clock phase according to the A parameter of the signal characteristic parameter modifier fed back to the signal adjuster, and determines the target positive spectrum information and the target negative spectrum information. And outputting the target positive spectrum information and the target negative spectrum information to the phase detector, wherein the target positive spectrum information includes a polarization signal adjusted first signal and a second signal positive spectrum signal, and the target negative spectrum information includes a polarization angle Adjusting the negative signal of the first signal and the second signal; the phase detector determines the clock error signal according to the received target positive spectrum information and the target negative spectrum information, and outputs the clock error signal to the loop filter a loop filter for filtering the clock error signal and filtering the time The error signal is output to the interpolation controller, and the signal obtained by integrating the branch path of the loop filter with the clock error signal is output as a monitoring signal to the signal characteristic parameter modifier; the interpolation controller determines B according to the filtered clock error signal. Parameter; the signal characteristic parameter modifier determines whether the monitoring signal is within the preset fluctuation range. If the signal characteristic parameter modifier determines that the monitoring signal is not within the preset fluctuation range, then the A parameter and the C parameter are adjusted so that the monitoring signal is preset. Within the range of fluctuations.
在一种可能的实现中,信号调整器根据A参数对调整时钟相位后的所述第一、第二信号进行偏振角度调整,确定目标正频谱信息以及目标负频谱信息,具体是将调整时钟信号后的第一信号的正频谱信号乘以Cos(A),获得第一正频谱信号;将调整时钟信号后的第一信号的负频谱信号乘以Cos(A),获得第一负频谱信号;将调整时钟信号后的第二信号的正频谱信号乘以Sin(A),获得第二正频谱信号;将调整时钟信号后的第二信号的负频谱信号乘以Sin(A),获得第二负频谱信号;将第一正频谱信号以及第二正频谱信号合并得到目标正频谱信息,将第一负频谱信息以及第二负频谱信息合并得到目标负频谱信息。In a possible implementation, the signal adjuster adjusts the polarization angle of the first and second signals after adjusting the clock phase according to the A parameter, and determines the target positive spectrum information and the target negative spectrum information, specifically, the clock signal is adjusted. The positive spectrum signal of the first signal is multiplied by Cos(A) to obtain a first positive spectrum signal; the negative spectrum signal of the first signal after adjusting the clock signal is multiplied by Cos(A) to obtain a first negative spectrum signal; Multiplying the positive spectral signal of the second signal after adjusting the clock signal by Sin(A) to obtain a second positive spectral signal; multiplying the negative spectral signal of the second signal after adjusting the clock signal by Sin(A) to obtain a second a negative spectral signal; combining the first positive spectral signal and the second positive spectral signal to obtain target positive spectral information, and combining the first negative spectral information and the second negative spectral information to obtain target negative spectral information.
在一种可能的实现中,鉴相器具体根据目标正频谱信息以及目标负频谱信息的全部频谱信息确定时钟误差信号。In a possible implementation, the phase detector determines the clock error signal according to the target positive spectrum information and the entire spectrum information of the target negative spectrum information.
在一种可能的实现中,信号特性参数修改器,具体在第一预置调整范围内调整A参数,在第二预置调整范围内调整C参数。In a possible implementation, the signal characteristic parameter modifier specifically adjusts the A parameter within the first preset adjustment range, and adjusts the C parameter within the second preset adjustment range.
在一种可能的实现中,该时钟恢复装置还包括移位寄存器,该该移位寄存器接收插值控制器根据时钟误差信号确定的参数,根据D参数对输入至信号 时钟补偿器的第一信号以及第二信号进行移位操作。In a possible implementation, the clock recovery device further includes a shift register, the shift register receives a parameter determined by the interpolation controller according to the clock error signal, and inputs the signal according to the D parameter pair The first signal and the second signal of the clock compensator perform a shift operation.
相较于现有技术,从以上技术方案可以看出,在本申请中,由于监控信号受到PMD、色散等因素的影响会导致监控信号产生波动,因此通过监控该监控信号,不断的调整A参数以及C参数,使得监控信号在预置波动范围内,即通过本发明时钟恢复装置,可以监控并减少PMD、色散等因素影响。Compared with the prior art, it can be seen from the above technical solutions that in the present application, since the monitoring signal is affected by factors such as PMD and dispersion, the monitoring signal may fluctuate. Therefore, by monitoring the monitoring signal, the A parameter is continuously adjusted. And the C parameter, so that the monitoring signal is within the preset fluctuation range, that is, the clock recovery device of the present invention can monitor and reduce the influence of factors such as PMD and dispersion.
附图说明DRAWINGS
图1为现有的相干光通信系统一个逻辑结构示意图;1 is a schematic diagram of a logical structure of a conventional coherent optical communication system;
图2为现有的时钟恢复装置结构示意图;2 is a schematic structural view of a conventional clock recovery device;
图3为本申请一种时钟恢复装置一个实施例的逻辑结构示意图;3 is a schematic diagram of a logical structure of an embodiment of a clock recovery apparatus according to the present application;
图4为本申请的时钟恢复装置中环路滤波器的逻辑结构示意图;4 is a schematic diagram showing the logical structure of a loop filter in the clock recovery device of the present application;
图5为本申请的时钟恢复装置中信号时钟补偿器的逻辑结构示意图;5 is a schematic diagram showing the logical structure of a signal clock compensator in the clock recovery device of the present application;
图6为本申请的时钟恢复装置中信号调整器的逻辑结构示意图;6 is a schematic diagram showing the logical structure of a signal adjuster in the clock recovery device of the present application;
图7为本申请的时钟恢复装置中鉴相器的逻辑结构示意图;7 is a schematic diagram showing the logical structure of a phase detector in a clock recovery device of the present application;
图8为本申请的鉴相器的时钟误差处理累加过程示意图;8 is a schematic diagram of a clock error processing accumulation process of the phase detector of the present application;
图9为本申请一种时钟恢复装置另一实施例的逻辑结构示意图。FIG. 9 is a schematic diagram showing the logical structure of another embodiment of a clock recovery apparatus according to the present application.
具体实施方式detailed description
本申请实施例提供了一种时钟恢复装置以及时钟恢复的方法,可以监控,减少PMD、色散等因素影响。The embodiment of the present application provides a clock recovery device and a clock recovery method, which can monitor and reduce the influence of factors such as PMD and dispersion.
为了使本技术领域的人员更好地理解本申请方案,下面将结合本申请实施例中的附图,对本申请实施例中的技术方案进行清楚、完整地描述,显然,所描述的实施例仅仅是本申请一部分的实施例,而不是全部的实施例。基于本申请中的实施例,本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例,都应当属于本申请保护的范围。The technical solutions in the embodiments of the present application are clearly and completely described in the following with reference to the accompanying drawings in the embodiments of the present application. It is an embodiment of the present application, and not all of the embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments of the present application without departing from the inventive scope shall fall within the scope of the application.
本申请的说明书和权利要求书及上述附图中的术语“第一”、“第二”、“第三”、“第四”等(如果存在)是用于区别类似的对象,而不必用于描述特定的顺序或先后次序。应该理解这样使用的数据在适当情况下可以互换,以便这里描述的实施例能够以除了在这里图示或描述的内容以外的顺序实施。此外,术 语“包括”和以及他们的任何变形,意图在于覆盖不排他的包含,例如,包含了一系列步骤或单元的过程、方法、系统、产品或设备不必限于清楚地列出的那些步骤或单元,而是可包括没有清楚地列出的或对于这些过程、方法、产品或设备固有的其它步骤或单元。The terms "first", "second", "third", "fourth", etc. (if present) in the specification and claims of the present application and the above figures are used to distinguish similar objects without having to use To describe a specific order or order. It is to be understood that the data so used may be interchanged where appropriate so that the embodiments described herein can be implemented in a sequence other than what is illustrated or described herein. In addition, surgery The phrase "comprising" and variations of the invention are intended to cover a non-exclusive inclusion, for example, a process, method, system, product, or device that comprises a series of steps or units is not necessarily limited to those steps or units that are clearly listed. Rather, other steps or units not explicitly listed or inherent to such processes, methods, products, or devices may be included.
请参阅图3,图3为本申请中一种时钟恢复装置一个实施例的逻辑结构示意图,该时钟恢复装置300中包括信号时钟补偿器301、信号调整器302、鉴相器303、环路滤波器304、插值控制器305以及信号特性参数修改器306、其中,环路滤波器304的逻辑结构图如图4所示,环路滤波器304为常见的环路滤波器,其中Kp以及Ki为环路滤波器304的系数。由图4可知环路滤波器304滤波后的输出为信号输出1,即输出至插值控制器305的输出信号,这里假设从环路滤波器304积分支路引出的信号作为监控信号,即图4中所述的信号输出2,其具体位置如图4所示。Please refer to FIG. 3. FIG. 3 is a schematic diagram of a logical structure of an embodiment of a clock recovery apparatus according to the present application. The clock recovery apparatus 300 includes a signal clock compensator 301, a signal adjuster 302, a phase detector 303, and a loop filter. The logic structure diagram of the loop filter 304 is shown in FIG. 4, and the loop filter 304 is a common loop filter, where Kp and Ki are The coefficients of the loop filter 304. It can be seen from FIG. 4 that the filtered output of the loop filter 304 is the signal output 1, that is, the output signal outputted to the interpolation controller 305. Here, the signal derived from the branch circuit of the loop filter 304 is assumed as the monitoring signal, that is, FIG. The signal output 2 described in the above is shown in Figure 4.
本领域技术人员可以知道,色散具有随着频率变化而有不同的相位变化的特性,当具有色散的信号进去到鉴相器303后,鉴相器303对信号进行时钟误差相位的提取时叠加了因为色散造成的相位变化后,鉴相器输出的信号因此受到了色散这个因素造成的波动。经过环路滤波器304后,同样伴随着这个波动。所以色散会导致环路滤波器的信号输出2的值产生波动。Those skilled in the art will appreciate that the dispersion has characteristics of different phase changes as the frequency changes. When the signal having dispersion enters the phase detector 303, the phase detector 303 superimposes the clock error phase of the signal. After the phase change caused by the dispersion, the signal output from the phase detector is thus subject to fluctuations caused by the dispersion. After passing through the loop filter 304, this fluctuation is also accompanied. Therefore, the dispersion causes the value of the signal output 2 of the loop filter to fluctuate.
另外,PMD是指光的两个偏振态信号之间具有不同的延时,并伴随作时间随机变化的特性。应理解,当信号受到PMD影响后送入的鉴相器303后,鉴相器303输出信号会受到两个偏振态信号之间不同延时且随机变化原因造成的波动。即同样会PMD会导致环路滤波器304的输出信号2的值产生波动。In addition, PMD refers to the characteristic that the two polarization states of light have different delays, accompanied by random changes in time. It should be understood that after the phase detector 303 is sent after the signal is affected by the PMD, the output signal of the phase detector 303 is subject to fluctuations caused by different delays between the two polarization states and caused by random variations. That is, the PMD will also cause the value of the output signal 2 of the loop filter 304 to fluctuate.
另外,在相干光通信系统中,发射机与接收机的激光器频率不一致导致信号解调为外差解调,外差解调导致进行鉴相器303的信号时钟分量有一个固定的偏移量,固定的偏移量造成鉴相器303输出带有相位噪声,相位噪声的大小与收发两个激光器具体的频率偏差的大小有关系。带有相位噪声的信号输入到环路滤波器304,同样也影响了环路滤波器304的信号输出2的输出值,造成其波动。In addition, in a coherent optical communication system, the laser frequency of the transmitter and the receiver is inconsistent, resulting in demodulation of the signal into heterodyne demodulation, and heterodyne demodulation results in a fixed offset of the signal clock component of the phase detector 303. The fixed offset causes the phase detector 303 output to have phase noise, and the magnitude of the phase noise is related to the magnitude of the specific frequency deviation of the two lasers. The signal with phase noise is input to the loop filter 304, which also affects the output value of the signal output 2 of the loop filter 304, causing it to fluctuate.
即只要鉴相器303的输入信号受到上面的一种或是多种因素的组合都造成相同的结果就是环路滤波器304输出信号2的值产生波动。即可以通过环路 滤波器304信号输出2的变化就可以判断信号时钟同步性能是否正常。That is, as long as the input signal of the phase detector 303 is subjected to the combination of one or more of the above factors, the same result is that the value of the output signal 2 of the loop filter 304 fluctuates. That can pass the loop The change of the signal output 2 of the filter 304 can judge whether the signal clock synchronization performance is normal.
因此,本申请提出了如图3所示连接关系的时钟恢复装置300,其与现有技术中的时钟恢复装置,即图2所示的时钟恢复装置,不同之处主要体现在本利用环路滤波器304的信号输出2作为反馈调节信号特性参数。信号特性参数修改器306通过不断调整以及输出控制A参数以及C参数,进而进行控制整个环路的工作状态,使得环路滤波器304的信号输出2的值在预置波动范围内,若环路滤波器304的信号输出2的值在预置波动范围内,说明此时时钟恢复装置300已经减少或者消除了PMD、色散等因素的影响。Therefore, the present application proposes a clock recovery device 300 as shown in FIG. 3, which is different from the clock recovery device in the prior art, that is, the clock recovery device shown in FIG. Signal output 2 of filter 304 is used as a feedback adjustment signal characteristic parameter. The signal characteristic parameter modifier 306 controls the operation state of the entire loop by continuously adjusting and outputting the control A parameter and the C parameter, so that the value of the signal output 2 of the loop filter 304 is within the preset fluctuation range, if the loop The value of the signal output 2 of the filter 304 is within the preset fluctuation range, indicating that the clock recovery device 300 has reduced or eliminated the effects of factors such as PMD, dispersion, and the like.
为了便于理解,下面对本申请中的时钟恢复装置300的工作过程进行具体的描述:For ease of understanding, the working process of the clock recovery apparatus 300 in this application is specifically described below:
信号时钟补偿器301,用于将输出至信号时钟补偿器的第一、第二信号转换为频域形式的信号,再根据B参数以及C参数调整第一信号的时钟相位,根据B参数以及C参数调整第二信号的时钟相位后,再输出第一信号以及第二信号;The signal clock compensator 301 is configured to convert the first and second signals outputted to the signal clock compensator into signals in the frequency domain form, and then adjust the clock phase of the first signal according to the B parameter and the C parameter, according to the B parameter and the C After adjusting the clock phase of the second signal, the first signal and the second signal are output;
其中,第一信号以及第二信号为光信号的两个不同偏振态的信号,B参数由插值控制器305反馈至所述信号时钟补偿器301,C参数由信号特性参数修改器306反馈至信号时钟补偿器301。The first signal and the second signal are signals of two different polarization states of the optical signal, and the B parameter is fed back to the signal clock compensator 301 by the interpolation controller 305, and the C parameter is fed back to the signal by the signal characteristic parameter modifier 306. Clock compensator 301.
即,信号时钟补偿器就会对输入信号进行时钟偏差补偿,补偿的目的是让信号被一个固定采样倍数的采样器采样。That is, the signal clock compensator compensates for the clock offset of the input signal. The purpose of the compensation is to have the signal sampled by a sampler of a fixed sampling multiple.
即本申请中的信号时钟补偿器,可以将经过ADC转换后的时域离散信号,经过快速傅立叶变换(英文全称:Fast Fourier Transform,缩写:FFT),转换为频域形式的信号后,再根据插值控制器305反馈过来的B参数以及信号特性参数修改器306反馈过来的C参数调整输入信号的时钟相位,并输出调整了时钟相位后的信号。即信号时钟补偿器301的目的是对输入信号进行时钟偏差补偿,补偿的目的是让信号被一个固定采样倍数的采样器采样。That is, the signal clock compensator in the present application can convert the time domain discrete signal after the ADC conversion into a frequency domain form signal through a fast Fourier transform (abbreviation: FFT), and then according to the signal. The B parameter fed back by the interpolation controller 305 and the C parameter fed back by the signal characteristic parameter modifier 306 adjust the clock phase of the input signal, and output the signal after the clock phase is adjusted. That is, the purpose of the signal clock compensator 301 is to perform clock offset compensation on the input signal. The purpose of the compensation is to allow the signal to be sampled by a sampler of a fixed sampling multiple.
请参阅图5,图5为本申请的时钟恢复装置中的信号时钟补偿器的逻辑结构示意图,其中,Exp表示自然指数。为了便于描述,在本实施例中,假设第一信号为X信号,第二信号为Y信号,在信号时钟补偿器301里,X、Y信号经过FFT后,再乘以一个相位变量,该相位变量由B、C参数组成。B参数 是信号时钟调节用,C参数主要是调整色散的影响。经过了信号时钟补偿器后,信号的采样率就调整完成,此时,若系统发射端发射时钟随着时间有偏差,那么这个是信号时钟补偿器则根据B参数以及C参数跟随着一起偏移,来达到固定采样倍数的采样率的目标的。只要此时的B参数以及C参数满足固定采样倍数就可以认为时钟同步性能正常,也就是说,此时时钟输出的信号时钟受到的影响已经减少,或者已经被消除。Please refer to FIG. 5. FIG. 5 is a schematic diagram showing the logical structure of a signal clock compensator in the clock recovery apparatus of the present application, where Exp represents a natural index. For convenience of description, in the present embodiment, it is assumed that the first signal is an X signal and the second signal is a Y signal. In the signal clock compensator 301, the X and Y signals are subjected to FFT, and then multiplied by a phase variable, the phase The variable consists of B and C parameters. B parameter It is used for signal clock adjustment, and the C parameter is mainly to adjust the influence of dispersion. After the signal clock compensator, the sampling rate of the signal is adjusted. At this time, if the transmitting clock of the system transmitter deviates with time, then the signal clock compensator follows the B parameter and the C parameter. , to achieve a fixed sampling rate of the sampling rate of the target. As long as the B parameter and the C parameter satisfy the fixed sampling multiple at this time, the clock synchronization performance can be considered normal, that is, the influence of the clock output of the clock output has been reduced or has been eliminated.
需要说明的是,现有的信号时钟补偿器是利用时域插值滤波器完成输入信号的时钟纠正,时域插值滤波器根据精度要求的不同选择不同个数的滤波器系数,而系数的多少直接决定了实现时信号时钟补偿器的芯片资源。例如:假设现有的信号时钟补偿器进行时域插值用8个滤波器抽头系数对100个数据点,就是移动一个时间相位,则需要就是800个乘法操作。但是在本申请中的信号时钟补偿器中,将输入至信号时钟补偿器的信号转换为频域形式的信号后再进行时钟的纠正,其在频域实现则只需要进行100个乘法操作。即现有的信号时钟补偿器相对于本申请中的信号时钟补偿器浪费了大量的乘法器。It should be noted that the existing signal clock compensator uses the time domain interpolation filter to complete the clock correction of the input signal, and the time domain interpolation filter selects different number of filter coefficients according to different precision requirements, and the coefficient is directly The chip resources of the signal clock compensator at the time of implementation are determined. For example, suppose the existing signal clock compensator performs time domain interpolation with 8 filter tap coefficients for 100 data points, that is, moving a time phase, then 800 multiplication operations are required. However, in the signal clock compensator of the present application, the signal input to the signal clock compensator is converted into a signal in the form of a frequency domain, and then the clock is corrected. In the frequency domain, only 100 multiplication operations are required. That is, the existing signal clock compensator wastes a large number of multipliers with respect to the signal clock compensator in the present application.
本申请中的时钟恢复装置,用于引出信号时钟补偿器301的输出信号作为反馈信号,将其输出至信号调整器302;The clock recovery device in the present application is used to take the output signal of the signal clock compensator 301 as a feedback signal, and output it to the signal adjuster 302;
信号调整器302,用于根据A参数对调整时钟相位后的X、Y信号的进行偏振角度调整并确定目标正频谱信息以及目标负频谱信息。The signal adjuster 302 is configured to adjust the polarization angle of the X and Y signals after adjusting the clock phase according to the A parameter, and determine the target positive spectrum information and the target negative spectrum information.
其中,A参数由信号特性参数修改器306反馈至信号调整器302,目标正频谱信息包括经过偏振角度调整后的X信号、Y信号的正频谱信号,目标负频谱信息包括经过偏振角度调整后的X信号、Y信号的负频谱信号。The A parameter is fed back to the signal adjuster 302 by the signal characteristic parameter modifier 306. The target positive spectrum information includes a positive spectrum signal of the X signal and the Y signal after the polarization angle adjustment, and the target negative spectrum information includes the polarization angle adjustment. Negative spectrum signal of X signal and Y signal.
优选地,具体可以通过图6所示的方式进行偏振角度调整并确定目标正频谱信息以及目标负频谱信息,请参阅图6,图6为本申请中的时钟恢复装置中的信号调整器的逻辑结构示意图:Preferably, the polarization angle adjustment and the target positive spectrum information and the target negative spectrum information are specifically determined by the manner shown in FIG. 6. Referring to FIG. 6, FIG. 6 is a logic of a signal adjuster in the clock recovery apparatus of the present application. Schematic:
即用于将调整时钟信号后的X信号的正频谱信号乘以Cos(A),获得第一正频谱信号;将调整时钟信号后的X信号的负频谱信号乘以Cos(A),获得第一负频谱信号;That is, the positive spectrum signal of the X signal after adjusting the clock signal is multiplied by Cos(A) to obtain the first positive spectrum signal; and the negative spectrum signal of the X signal after adjusting the clock signal is multiplied by Cos(A) to obtain the first a negative spectral signal;
将调整时钟信号后的Y信号的正频谱信号乘以Sin(A),获得第二正频谱信号;将调整时钟信号后的Y信号的负频谱信号乘以Sin(A),获得第二负频 谱信号;Multiplying the positive spectral signal of the Y signal after adjusting the clock signal by Sin(A) to obtain a second positive spectral signal; multiplying the negative spectral signal of the Y signal after adjusting the clock signal by Sin(A) to obtain a second negative frequency Spectral signal
将第一正频谱信号以及第二正频谱信号合并得到目标正频谱信息;将第一负频谱信号以及第二负频谱信号合并得到目标负频谱信息;Combining the first positive spectral signal and the second positive spectral signal to obtain target positive spectral information; combining the first negative spectral signal and the second negative spectral signal to obtain target negative spectral information;
最后将目标正频谱信息以及目标负频谱信息输出至鉴相器。Finally, the target positive spectrum information and the target negative spectrum information are output to the phase detector.
本申请中的时钟恢复装置中,引出信号时钟补偿器301的输出信号作为反馈信号,将其输出至信号调整器302,即可以将调整时钟信号后的X信号以及Y信号反馈至信号调整器302,信号调整器302接收了调整时钟信号后X信号以及Y信号后,优选地,可以通过如图6所示的方式调整偏振角度。In the clock recovery device of the present application, the output signal of the signal clock compensator 301 is taken out as a feedback signal, and is output to the signal adjuster 302, that is, the X signal and the Y signal after adjusting the clock signal can be fed back to the signal adjuster 302. After the signal adjuster 302 receives the X signal and the Y signal after adjusting the clock signal, preferably, the polarization angle can be adjusted by the manner as shown in FIG. 6.
应理解,PMD的影响主要体现在X信号与X信号两路偏振态的时延差,那么时延差造成X、Y两路信号有不同相位差。通过图6所示方式就是通过调节相位差的方式调节了X、Y两路信号的时延差。这样A参数的调节就可以弥补PMD带来的影响。It should be understood that the influence of PMD is mainly reflected in the delay difference between the two polarization states of the X signal and the X signal, and the delay difference causes the X and Y signals to have different phase differences. The way shown in Figure 6 is to adjust the delay difference between the X and Y signals by adjusting the phase difference. This adjustment of the A parameter can compensate for the impact of PMD.
需要说明的是,本申请中的信号调整器与现有的信号调整器的不同在于调整参数的不同,现在技术把接收到的A参数取余弦后需要再乘一个复指数作为调节参数,即最终的调节参数为复数形式,而本发明只把接收到的A参数取余弦操作保证了调节参数始终是实数。可以在满足调整功能同时也减少了计算复杂度,进而减少系统功耗。It should be noted that the difference between the signal adjuster in the present application and the existing signal adjuster is that the adjustment parameters are different. Now the technology takes the cosine of the received A parameter and needs to multiply a complex index as the adjustment parameter, that is, finally The adjustment parameter is in the plural form, and the present invention only takes the cosine operation of the received A parameter to ensure that the adjustment parameter is always a real number. The adjustment function can be satisfied while reducing the computational complexity, thereby reducing system power consumption.
需要说明的是,信号调整器根据A参数除了通过取余弦作为调节参数外,还可以根据A参数获得其他调节参数,例如,信号调整器将接收到的A参数取正弦操作,只要使得最终可以根据A参数的调节弥补PMD带来的影响即可,具体此处不做限定。It should be noted that, according to the A parameter, the signal adjuster can obtain other adjustment parameters according to the A parameter, in addition to taking the cosine as the adjustment parameter. For example, the signal adjuster takes the received A parameter into a sinusoidal operation, as long as the final decision can be made according to the A parameter. The adjustment of the A parameter can make up for the influence of the PMD, and is not limited herein.
鉴相器303,用于将从信号调整器302输入至鉴相器303的信号进行鉴相,获得时钟相位差;The phase detector 303 is configured to perform phase discrimination on the signal input from the signal adjuster 302 to the phase detector 303 to obtain a clock phase difference;
鉴相器303,具体地,用于根据上述目标正频谱信息以及目标负频谱信息的部分频谱信息或者全部频谱信息进行鉴相,确定时钟误差信号,优选地,用于根据上述目标正频谱信息以及目标负频谱信息的全部频谱信息进行鉴相。The phase detector 303, specifically, is configured to perform phase discrimination based on the target positive spectrum information and the partial spectrum information or the entire spectrum information of the target negative spectrum information, and determine a clock error signal, preferably, according to the target positive spectrum information and The entire spectrum information of the target negative spectrum information is phase-detected.
即鉴相器303主要对输入至鉴相器的信号进行鉴相,其中,具体可以是指基于Godard算法的鉴相器,还可以是基于gardner算法的鉴相器等,具体此处不做限定,取决于进入鉴相器的信号形式,但只要使得鉴相器303通过信号调 整器302的输入信号确定时钟误差信号即可。当信号调整器输入鉴相器303的信号为上述目标正频谱信号以及目标频谱信号时,优选地,鉴相器可以根据目标正频谱信息以及目标负频谱信息的全部频谱信息进行鉴相,确定时钟误差信号。That is, the phase detector 303 mainly performs phase discrimination on the signal input to the phase detector, and may specifically refer to a phase detector based on the Godard algorithm, and may also be a phase detector based on the gardner algorithm, etc., which is not limited herein. , depending on the form of the signal entering the phase detector, but as long as the phase detector 303 is adjusted by the signal The input signal of the whole device 302 can determine the clock error signal. When the signal input to the phase detector 303 is the target positive spectrum signal and the target spectrum signal, preferably, the phase detector can perform phase discrimination based on the target positive spectrum information and the entire spectrum information of the target negative spectrum information to determine the clock. Error signal.
为了便于理解,这里以根据目标正频谱信息以及目标负频谱信息的全部频谱信息确定时钟误差信号过程进行描述:For ease of understanding, the process of determining the clock error signal based on the target spectrum information and the entire spectrum information of the target negative spectrum information is described herein:
请参阅图7,图7为本申请的时钟恢复装置中鉴相器的逻辑结构示意图,从信号调整器302输出至鉴相器303的目标正频谱信号以及目标负频谱信号经过频谱合并后,再对合并后的频谱信号进行序列扩展,经过时钟相位误差处理累加后求得虚部,即时钟误差信号,再将求得的时钟误差信号输出至环路滤波器304。Please refer to FIG. 7. FIG. 7 is a schematic diagram of the logic structure of the phase detector in the clock recovery apparatus of the present application. After the target positive spectrum signal and the target negative spectrum signal output from the signal adjuster 302 to the phase detector 303 are spectrally combined, The combined spectrum signal is sequence-expanded, and the imaginary part, that is, the clock error signal is obtained after being accumulated by the clock phase error processing, and the obtained clock error signal is output to the loop filter 304.
这里假设是前面的信号时钟补偿器对信号做快速傅里叶变换时的点数为N,则可以相应假设目标正频谱信息为F(1)、F(2)、F(3)…F(N/2),目标负频谱信号为F(N/2+1)、F(N/2+2)、F(N/2+3)…F(N),则鉴相器303通过将目标正频谱信息以及目标负频谱信息进行合并,合并为一个完整的频域信号为F(1)、F(2)、F(3)…F(N)。其中被扩展的长度越长,时钟误差估计越准确但是耗时越多响应则越慢,具体需要可以根据系统取一个折中的值,具体此处不做限定。It is assumed here that the number of points when the previous signal clock compensator performs fast Fourier transform on the signal is N, then the target positive spectrum information can be assumed to be F(1), F(2), F(3)...F(N). /2), the target negative spectrum signal is F(N/2+1), F(N/2+2), F(N/2+3)...F(N), then the phase detector 303 passes the target positive The spectrum information and the target negative spectrum information are combined and combined into a complete frequency domain signal as F(1), F(2), F(3)...F(N). The longer the extended length is, the more accurate the clock error is estimated, but the more time-consuming the response is. The specific value needs to be a compromise value according to the system, which is not limited here.
这里为了说明方便,设被扩展的长度n为2(n为>=1的整数),则扩展后的序列为F(N-1)、F(N)、F(1)、F(2)、F(3)…F(N)、F(1)、F(2)。之后对扩展后的序列进行时钟相位误差处理累加,具体的处理累加方式如按照图8所示,即按照图8的方式对扩展后的序列进行共轭运算,并将最终的累加结果取虚部,即时钟误差信号输出到环路滤波器304。For convenience of explanation, it is assumed that the length n to be expanded is 2 (n is an integer of >=1), and the extended sequence is F(N-1), F(N), F(1), F(2). , F(3)...F(N), F(1), F(2). Then, the clock phase error processing is accumulated for the extended sequence, and the specific processing accumulation method is as shown in FIG. 8, that is, the extended sequence is conjugated according to the manner of FIG. 8, and the final accumulated result is taken as the imaginary part. That is, the clock error signal is output to the loop filter 304.
这里需要说明的是,扩展长度n为其他值时,可以根据上述的描述以此类推,具体此处不再赘述。It should be noted that when the extended length n is another value, it can be deduced according to the above description, and details are not described herein again.
环路滤波器304,用于对时钟误差信号进行滤波,并将滤波后的时钟误差信号输出至插值控制器305,还用于从环路滤波器304的积分支路引出的信号作为监控信号,将监控信号反馈至信号特性参数修改器306。The loop filter 304 is configured to filter the clock error signal, and output the filtered clock error signal to the interpolation controller 305, and also use the signal extracted from the product branch path of the loop filter 304 as a monitoring signal. The monitor signal is fed back to the signal characteristic parameter modifier 306.
如图4所示,时钟误差信号进入环路滤波器304里分为两路信号,一路信号与系数Kp相乘,一路与Ki相乘,与Ki相乘的分路在延时累积,累积后的 结果与Kp路的结果相加后输出,即滤波后的时钟误差信号,即图4中所示的信号输出1,延时累积又单独引出作为监控信号,即图4中所示的信号输出2。As shown in FIG. 4, the clock error signal enters the loop filter 304 and is divided into two signals. One signal is multiplied by the coefficient Kp, one is multiplied by Ki, and the shunt multiplied by Ki is accumulated in delay, and accumulated. of The result is added after the result of the Kp path, that is, the filtered clock error signal, that is, the signal output 1 shown in FIG. 4, and the delay accumulation is separately taken out as a monitoring signal, that is, the signal output 2 shown in FIG. .
这里需要说明的是,本领域技术人员可以清楚知道,Kp以及Ki系数为环路滤波器的系数,其具体的系数根据整个环路系统的情况来折中选取调节,具体此处不做限定,也不再赘述。It should be noted that those skilled in the art can clearly understand that the Kp and Ki coefficients are the coefficients of the loop filter, and the specific coefficients are adjusted according to the condition of the entire loop system, which is not limited herein. I will not go into details.
插值控制器305,用于根据滤波后的时钟误差信号确定B参数,并将B参数输出至信号时钟补偿器301;The interpolation controller 305 is configured to determine a B parameter according to the filtered clock error signal, and output the B parameter to the signal clock compensator 301;
本申请中,插值控制器可以输入进来的时钟误差信号做插值运算,从而确定B参,再将B参数输出至信号时钟补补偿器301。In the present application, the interpolation controller can input the incoming clock error signal for interpolation, thereby determining the B parameter, and then outputting the B parameter to the signal clock compensation compensator 301.
为了便于理解,下面举例对确定B参数的过程进行说明:For ease of understanding, the following example illustrates the process of determining the B parameter:
插值控制器305接收到环路滤波器输出的时钟误差信号后,这里假设为T,插值控制器305判断该T是否大于1或是小于-1;After the interpolation controller 305 receives the clock error signal output by the loop filter, here assumed to be T, the interpolation controller 305 determines whether the T is greater than 1 or less than -1;
若大于1,则对应小数部分即是B参数,例如,若T=1.1,则B=0.1;If it is greater than 1, the corresponding fractional part is the B parameter. For example, if T=1.1, then B=0.1;
若小于-1,同理对应小数部分即是B参数,例如,若T=-1.1,则B=-0.1;If it is less than -1, the corresponding fractional part is the B parameter. For example, if T=-1.1, then B=-0.1;
若T介于-1与1之间,则对应的值为B参数,例如,若T=0.5,则B=0.5,;若T=-0.5,则B=-0.5。If T is between -1 and 1, the corresponding value is the B parameter. For example, if T = 0.5, then B = 0.5, and if T = -0.5, then B = -0.5.
信号特性参数修改器306,用于判断监控信号是否在预置波动范围内;若判断监控信号并不在预置波动范围内,则在第一预置调整范围内调整A参数,在第二预置调整范围内调整C参数,并将A参数反馈至信号调整器302,将C参数反馈至信号时钟补偿器301,使得监控信号在预置波动范围内。The signal characteristic parameter modifier 306 is configured to determine whether the monitoring signal is within a preset fluctuation range; if it is determined that the monitoring signal is not within the preset fluctuation range, adjusting the A parameter in the first preset adjustment range, in the second preset The C parameter is adjusted within the adjustment range, and the A parameter is fed back to the signal adjuster 302, and the C parameter is fed back to the signal clock compensator 301 so that the monitoring signal is within the preset fluctuation range.
即本申请中,信号特性参数修改器306接收到上述监控信号后,即环路滤波器的信号输出2时,会判断该监控信号是否在预置波动范围内。由前述描述可知,当监控信号产生波动时,说明受到PMD、色散等因素的影响,此时,本申请中的信号特性参数修改器,通过动态调整A参数以及C参数,使得最后的监控信号的输出在预置波动范围内,即通过不断扫描A、C参数,达到消除或减少PMD、色散等因素的影响。That is, in the present application, after the signal characteristic parameter modifier 306 receives the above-mentioned monitoring signal, that is, the signal output 2 of the loop filter, it is determined whether the monitoring signal is within the preset fluctuation range. It can be seen from the foregoing description that when the monitoring signal generates fluctuation, it is affected by factors such as PMD and dispersion. At this time, the signal characteristic parameter modifier in the present application dynamically adjusts the A parameter and the C parameter to make the last monitoring signal. The output is within the preset fluctuation range, that is, by continuously scanning the A and C parameters to eliminate or reduce the influence of PMD, dispersion and other factors.
其中,预置波动范围可以根据经验数据进行配置,例如,一般长期输出的数值都是在+/-0.1以内波动。这个时候就认为时钟同步性能正常。如果大于这个值,那么通过A、C参数的扫描并调整最后找到A、C参数来满足这个0.1 的要求。Among them, the preset fluctuation range can be configured according to empirical data. For example, the values of the long-term output generally fluctuate within +/- 0.1. At this time, the clock synchronization performance is considered normal. If it is greater than this value, then the A and C parameters are scanned and adjusted to find the A and C parameters to satisfy this 0.1. Requirements.
其中,优选地,信号特性参数修改器306可以再在第一预置调整范围内调整A参数,在第二预置调整范围内调整C参数,使得监控信号在预置波动范围内,即在预置的范围内扫描A、C参数,达到消除或减少PMD、色散等因素的影响。Preferably, the signal characteristic parameter modifier 306 can further adjust the A parameter within the first preset adjustment range, and adjust the C parameter within the second preset adjustment range, so that the monitoring signal is within the preset fluctuation range, that is, in advance Scan the A and C parameters within the range to eliminate or reduce the effects of PMD, dispersion and other factors.
为了便于理解,下面同样举例来进行说明:For ease of understanding, the following examples are also given:
优选地,这里假设第一预置调整范围为:-45到+45,步进度为1,第二预置范围为0到1,步进度为1,其具体的扫描流程如下:Preferably, it is assumed here that the first preset adjustment range is: -45 to +45, the step degree is 1, the second preset range is 0 to 1, and the step degree is 1, and the specific scanning process is as follows:
a:固定A参数,在第一预置调整范围内粗选A参数,例如-45,扫描C参数,C参数为第二预置范围内,步进为小于1的值,例如C参数的取值可以是:0.1,0.2…1。此时,通过扫描C参数,保存每次变换C参数后,环路滤波器304信号输出2的输出值,计算其方差,假设计算得到的方差为std1。a: fixed A parameter, coarsely select A parameter in the first preset adjustment range, for example -45, scan C parameter, C parameter is within the second preset range, step is less than 1 value, for example, C parameter is taken The value can be: 0.1, 0.2...1. At this time, by scanning the C parameter, the output value of the loop filter 304 signal output 2 is stored after each conversion of the C parameter, and the variance is calculated, assuming that the calculated variance is std1.
b:变化A参数为-44,重复步骤a中,扫描C参数的操作,同样保存环路滤波器304信号输出2的输出值,计算其方差,设为std2。b: The change A parameter is -44. In step a, the operation of scanning the C parameter is repeated, and the output value of the signal output 2 of the loop filter 304 is also saved, and the variance is calculated and set to std2.
c:变化完所有A参数后,对比所有的方差,选取最小的方差对应的A参数以及C参数。c: After changing all the A parameters, compare all the variances, select the A parameter and the C parameter corresponding to the smallest variance.
可选地,当完成上述扫描后,信号特性参数修改器还继续在上述扫描的基础上继续扫描,如d所示:Optionally, after completing the above scanning, the signal characteristic parameter modifier further continues to scan on the basis of the above scanning, as shown by d:
d:在a-c步骤确定的A参数以及C参数上确定第二次扫描范围,例如,若前面扫描的结果是A=15,C=0.3,那么本次扫描的范围可以设定为A参数取值范围为10到20,C参数的取值范围为0.2到0.4。d: Determine the second scan range on the A parameter and the C parameter determined in the ac step. For example, if the result of the previous scan is A=15, C=0.3, then the range of the scan can be set to the value of the A parameter. The range is from 10 to 20, and the C parameter ranges from 0.2 to 0.4.
e:根据d设定的范围重复按照步骤1的方式扫描,一直通过这种扫描的方式来跟踪信号的变化。e: The scanning according to step 1 is repeated according to the range set by d, and the change of the signal is always tracked by such scanning.
这里需要说明的是,上述a-e步骤描述的扫描范围为优选地扫描方案,但并不对本申请构成限定,信号特性参数修改器306可以根据实际的应用情况,例如根据扫描的精度以及速度折中选取,具体此处不做限定。It should be noted that the scanning range described in the ae step is a preferred scanning scheme, but is not limited to the present application. The signal characteristic parameter modifier 306 can be selected according to the actual application, for example, according to the accuracy and speed of the scanning. , specifically here is not limited.
可选地,结合上述时钟恢复装置实施例,本申请的时钟恢复装置,还可以进一步包括移位寄存器,具体参阅图9,图9为本申请一种时钟恢复装置另一实施例示意图,该时钟恢复装置900中包括信号时钟补偿器901、信号调整器 902、鉴相器903、环路滤波器904、插值控制器905、信号特性参数修改器906以及移位寄存器907:Optionally, in combination with the clock recovery device embodiment, the clock recovery device of the present application may further include a shift register. Referring to FIG. 9 , FIG. 9 is a schematic diagram of another embodiment of a clock recovery device according to the present application. The recovery device 900 includes a signal clock compensator 901 and a signal adjuster. 902, phase detector 903, loop filter 904, interpolation controller 905, signal characteristic parameter modifier 906, and shift register 907:
其中,信号时钟补偿器901、信号调整器902、鉴相器903、环路滤波器904、插值控制器905、信号特性参数修改器906在本时钟恢复装置的作用以及功能可以参阅上述实施例的描述,具体此处不再赘述。The functions of the signal clock compensator 901, the signal adjuster 902, the phase detector 903, the loop filter 904, the interpolation controller 905, and the signal characteristic parameter modifier 906 in the present clock recovery apparatus can be referred to the above embodiments. Description, which will not be described here.
其中,在时钟恢复装置900中,结合上述实施例,插值控制器905除了根据监控信号确定B参数外,插值控制器还根据监控信号D参数,并将D参数反馈至移位寄存器907,移位寄存器907根据D参数进行的移位操作;In the clock recovery device 900, in combination with the above embodiment, the interpolation controller 905 determines the B parameter according to the monitoring signal, and the interpolation controller further returns the D parameter to the shift register 907 according to the monitoring signal D parameter. The shift operation of the register 907 according to the D parameter;
例如,结合上述实施例,当判断监控信号大于1时,还再根据监控信号向下取整数,把取得的整数,即D参数送入到移位寄存器907移位信号;For example, in combination with the foregoing embodiment, when it is determined that the monitoring signal is greater than 1, the integer is further taken down according to the monitoring signal, and the obtained integer, that is, the D parameter is sent to the shift register 907 shift signal;
当判断监控信号小于-1,那么把向上取整的整数,即D参数再送到移位寄存器907去移位信号。When it is judged that the monitor signal is less than -1, the rounded integer, i.e., the D parameter, is sent to the shift register 907 to shift the signal.
相较于现有技术,从以上技术方案可以看出,本申请中的时钟恢复装置,移位寄存器根据D参数对第一信号以及第二信号进行移位操作后,输出至信号时钟补偿器,其中,D参数由插值控制器反馈至移位寄存器;信号时钟补偿器根据B参数以及C参数对输入至信号时钟补偿器的第一、第二信号进行时钟相位的调整,并输出调整时钟相位后的第一、第二信号,其中,第一、第二信号为光信号两个不同偏振态的信号,B参数由插值控制器反馈至信号时钟补偿器,C参数由信号特性参数修改器反馈至信号时钟补偿器;信号调整器根据A参数对调整时钟相位后的第一、第二信号进行偏振角度的调整,并将确定的目标正频谱信息以及目标负频谱信息输出至鉴相器,其中,A参数由信号特性参数修改器反馈至信号调整器;鉴相器根据目标正频谱信息以及目标负频谱信息确定时钟误差信号,并将时钟误差信号输出至环路滤波器;环路滤波器对时钟误差信号进行滤波,并将滤波后的时钟误差信号输出至插值控制器,从环路滤波器的积分支路引出的信号作为监控信号,并将监控信号反馈至信号特性参数修改器;插值控制器根据滤波后的定时误差信号确定B参数以及D参数,并将B参数输出至信号时钟补偿器,将D参数反馈至移位寄存器;信号特性参数修改器判断监控信号是否在预置波动范围内,若否,则动态调整A参数以及C参数,使得监控信号在预置波动范围内。即本申请中,由于监控信号 受到PMD、色散等因素的影响会导致监控信号产生波动,因此通过监控该监控信号,不断的调整A参数以及C参数,使得监控信号在预置波动范围内,即通过本发明时钟恢复装置,可以监控,并减少PMD、色散等因素影响。Compared with the prior art, it can be seen from the above technical solution that the clock recovery device in the present application shifts the first signal and the second signal according to the D parameter, and then outputs the signal to the signal clock compensator. Wherein, the D parameter is fed back to the shift register by the interpolation controller; the signal clock compensator performs clock phase adjustment on the first and second signals input to the signal clock compensator according to the B parameter and the C parameter, and outputs the adjusted clock phase. The first and second signals, wherein the first and second signals are signals of two different polarization states of the optical signal, the B parameter is fed back to the signal clock compensator by the interpolation controller, and the C parameter is fed back by the signal characteristic parameter modifier to a signal clock compensator; the signal adjuster adjusts a polarization angle of the first and second signals after adjusting the clock phase according to the A parameter, and outputs the determined target positive spectrum information and the target negative spectrum information to the phase detector, wherein The A parameter is fed back to the signal adjuster by the signal characteristic parameter modifier; the phase detector is based on the target positive spectrum information and the target negative spectrum information. a clock error signal and outputting a clock error signal to the loop filter; the loop filter filters the clock error signal, and outputs the filtered clock error signal to the interpolation controller, from the product branch of the loop filter The extracted signal is used as a monitoring signal, and the monitoring signal is fed back to the signal characteristic parameter modifier; the interpolation controller determines the B parameter and the D parameter according to the filtered timing error signal, and outputs the B parameter to the signal clock compensator, and the D parameter Feedback to the shift register; the signal characteristic parameter modifier determines whether the monitoring signal is within the preset fluctuation range, and if not, dynamically adjusts the A parameter and the C parameter so that the monitoring signal is within the preset fluctuation range. In this application, due to the monitoring signal Influenced by factors such as PMD and dispersion, the monitoring signal may fluctuate. Therefore, by monitoring the monitoring signal, the A parameter and the C parameter are continuously adjusted, so that the monitoring signal is within the preset fluctuation range, that is, by the clock recovery device of the present invention. Monitor and reduce the effects of factors such as PMD and dispersion.
上面对本申请中一种时钟恢复装置进行了描述,下面对本申请一种时钟恢复的方法进行描述,该时钟恢复方法应用于上述时钟恢复装置,该方法包括:A clock recovery device in the present application has been described above. The following describes a method for clock recovery in the present application. The clock recovery method is applied to the clock recovery device. The method includes:
移位寄存器根据参数D对第一信号以及第二信号进行移位操作,其中,该D参数,D参数由插值控制器反馈至移位寄存器;The shift register performs a shift operation on the first signal and the second signal according to the parameter D, wherein the D parameter and the D parameter are fed back to the shift register by the interpolation controller;
信号时钟补偿器根据B参数以及C参数对输入至信号时钟补偿器的第一、第二信号进行时钟相位的调整,并输出调整时钟相位后的第一、第二信号,第一、第二信号为光信号两个不同偏振态的信号,B参数由插值控制器反馈至信号时钟补偿器,C参数由信号特性参数修改器反馈至信号时钟补偿器;The signal clock compensator adjusts the clock phase of the first and second signals input to the signal clock compensator according to the B parameter and the C parameter, and outputs the first and second signals after adjusting the clock phase, the first and second signals. For the signal of two different polarization states of the optical signal, the B parameter is fed back to the signal clock compensator by the interpolation controller, and the C parameter is fed back to the signal clock compensator by the signal characteristic parameter modifier;
信号调整器根据A参数对调整时钟相位后的第一、第二信号进行偏振角度的调整,并将确定的目标正频谱信息以及目标负频谱信息输出至鉴相器,其中,A参数由信号特性参数修改器反馈至信号调整器,目标正频谱信息包括经过偏振角度调整后的第一信号、第二信号的正频谱信号,目标负频谱信息包括经过偏振角度调整后的第一信号、第二信号的负频谱信号;The signal adjuster adjusts the polarization angles of the first and second signals after adjusting the clock phase according to the A parameter, and outputs the determined target positive spectrum information and the target negative spectrum information to the phase detector, wherein the A parameter is determined by the signal characteristic The parameter modifier feeds back to the signal adjuster, and the target positive spectrum information includes a first signal and a second signal positive spectrum signal after the polarization angle adjustment, and the target negative spectrum information includes the first signal and the second signal after the polarization angle adjustment. Negative spectrum signal;
鉴相器根据目标正频谱信息以及目标负频谱确定时钟误差信号,并将时钟误差信号输出至环路滤波器;The phase detector determines a clock error signal according to the target positive spectrum information and the target negative spectrum, and outputs the clock error signal to the loop filter;
环路滤波器对时钟误差信号进行滤波,并将滤波后的时钟误差信号输出至插值控制器,从环路滤波器的积分支路引出的信号作为监控信号,并将监控信号反馈至信号特性参数修改器;The loop filter filters the clock error signal, and outputs the filtered clock error signal to the interpolation controller. The signal extracted from the product branch of the loop filter is used as a monitoring signal, and the monitoring signal is fed back to the signal characteristic parameter. modifier;
插值控制器根据滤波后的定时误差信号确定B参数以及D参数,并将B参数输出至信号时钟补偿器,将D参数反馈至移位寄存器;The interpolation controller determines the B parameter and the D parameter according to the filtered timing error signal, and outputs the B parameter to the signal clock compensator, and feeds the D parameter to the shift register;
信号特性参数修改器判断监控信号是否在预置波动范围内,若否,则动态调整A参数以及C参数,使得监控信号在预置波动范围内。The signal characteristic parameter modifier determines whether the monitoring signal is within the preset fluctuation range, and if not, dynamically adjusts the A parameter and the C parameter so that the monitoring signal is within the preset fluctuation range.
需要说明的是,本申请中的时钟恢复的方法中,时钟恢复装置各个器件的具体步骤以及实现细节可以参阅上述时钟恢复装置实施例中对应的描述,具体此处不再赘述。It should be noted that, in the method for clock recovery in the present application, the specific steps and implementation details of each device of the clock recovery device can be referred to the corresponding description in the foregoing embodiment of the clock recovery device, and details are not described herein again.
在本申请所提供的几个实施例中,应该理解到,所揭露的系统,模块和方 法,可以通过其它的方式实现。例如,以上所描述的装置实施例仅仅是示意性的,例如,所述模块的划分,仅仅为一种逻辑功能划分,实际实现时可以有另外的划分方式,例如多个单元或组件可以结合或者可以集成到另一个系统,或一些特征可以忽略,或不执行。另一点,所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口,装置或单元的间接耦合或通信连接,可以是电性,机械或其它的形式。In the several embodiments provided by the present application, it should be understood that the disclosed system, modules and squares The law can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of the modules is only a logical function division. In actual implementation, there may be another division manner, for example, multiple units or components may be combined or Can be integrated into another system, or some features can be ignored or not executed. In addition, the mutual coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interface, device or unit, and may be in an electrical, mechanical or other form.
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的,作为单元显示的部件可以是或者也可以不是物理单元,即可以位于一个地方,或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。The units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of the embodiment.
另外,在本申请各个实施例中的各功能模块可以集成在一个处理单元中,也可以是各个单元单独物理存在,也可以两个或两个以上单元集成在一个单元中。上述集成的单元既可以采用硬件的形式实现,也可以采用软件功能单元的形式实现。In addition, each functional module in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above integrated unit can be implemented in the form of hardware or in the form of a software functional unit.
所述集成的模块果以软件功能单元的形式实现并作为独立的产品销售或使用时,可以存储在一个计算机可读取存储介质中。基于这样的理解,本申请的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的全部或部分可以以软件产品的形式体现出来,该计算机软件产品存储在一个存储介质中,包括若干指令用以使得一台计算机设备(可以是个人计算机,服务器,或者网络设备等)执行本申请各个实施例所述方法的全部或部分步骤。而前述的存储介质包括:U盘、移动硬盘、只读存储器(ROM,Read-Only Memory)、随机存取存储器(RAM,Random Access Memory)、磁碟或者光盘等各种可以存储程序代码的介质。The integrated modules, when implemented in the form of software functional units and sold or used as separate products, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present application, in essence or the contribution to the prior art, or all or part of the technical solution may be embodied in the form of a software product stored in a storage medium. A number of instructions are included to cause a computer device (which may be a personal computer, server, or network device, etc.) to perform all or part of the steps of the methods described in various embodiments of the present application. The foregoing storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk, and the like. .
以上所述,以上实施例仅用以说明本申请的技术方案,而非对其限制;尽管参照前述实施例对本申请进行了详细的说明,本领域的普通技术人员应当理解:其依然可以对前述各实施例所记载的技术方案进行修改,或者对其中部分技术特征进行等同替换;而这些修改或者替换,并不使相应技术方案的本质脱离本申请各实施例技术方案的精神和范围。 The above embodiments are only used to explain the technical solutions of the present application, and are not limited thereto; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can still The technical solutions described in the embodiments are modified, or the equivalents of the technical features are replaced by the equivalents. The modifications and substitutions of the embodiments do not depart from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims (10)

  1. 一种时钟恢复装置,其特征在于,包括:A clock recovery device, comprising:
    信号时钟补偿器、信号调整器、鉴相器、环路滤波器、插值控制器以及信号特性参数修改器;a signal clock compensator, a signal adjuster, a phase detector, a loop filter, an interpolation controller, and a signal characteristic parameter modifier;
    所述信号时钟补偿器,用于将输入至所述信号时钟补偿器的第一信号、第二信号转换为频域形式的信号,根据B参数以及C参数对经过所述转换后的第一信号、第二信号进行时钟相位的调整,并将调整时钟相位后的所述第一信号、第二信号输出至所述信号调整器,所述第一、第二信号为光信号两个不同偏振态的信号,所述B参数由所述插值控制器反馈至所述信号时钟补偿器,所述C参数由所述信号特性参数修改器反馈至所述信号时钟补偿器;The signal clock compensator is configured to convert the first signal and the second signal input to the signal clock compensator into a signal in a frequency domain form, and pass the converted first signal according to the B parameter and the C parameter pair. And adjusting the clock phase by the second signal, and outputting the first signal and the second signal after adjusting the clock phase to the signal adjuster, where the first and second signals are two different polarization states of the optical signal a signal, the B parameter is fed back to the signal clock compensator by the interpolation controller, and the C parameter is fed back to the signal clock compensator by the signal characteristic parameter modifier;
    所述信号调整器,用于根据A参数对调整时钟相位后的所述第一信号、第二信号进行偏振角度调整,确定目标正频谱信息以及目标负频谱信息,将所述目标正频谱信息以及目标负频谱信息输出至所述鉴相器,所述A参数由所述信号特性参数修改器反馈至所述信号调整器,所述目标正频谱信息包括经过所述偏振角度调整后的所述第一信号、第二信号的正频谱信号,所述目标负频谱信息包括经过所述偏振角度调整后的所述第一信号、第二信号的负频谱信号;The signal adjuster is configured to perform polarization angle adjustment on the first signal and the second signal after adjusting a clock phase according to the A parameter, determine target positive spectrum information and target negative spectrum information, and use the target positive spectrum information and Target negative spectrum information is output to the phase detector, the A parameter is fed back to the signal adjuster by the signal characteristic parameter modifier, and the target positive spectrum information includes the first adjusted by the polarization angle a positive spectral signal of the second signal, the target negative spectral information comprising a negative spectral signal of the first signal and the second signal after the polarization angle adjustment;
    所述鉴相器,用于根据所述目标正频谱信息以及目标负频谱信息确定时钟误差信号,并将所述时钟误差信号输出至所述环路滤波器;The phase detector is configured to determine a clock error signal according to the target positive spectrum information and the target negative spectrum information, and output the clock error signal to the loop filter;
    所述环路滤波器,用于对所述时钟误差信号进行滤波,将滤波后的所述时钟误差信号输出至所述插值控制器,并将监控信号反馈至所述信号特性参数修改器,所述监控信号为所述环路滤波器的积分支路对所述时钟误差信号进行积分后的信号;The loop filter is configured to filter the clock error signal, output the filtered clock error signal to the interpolation controller, and feed back a monitoring signal to the signal characteristic parameter modifier. The monitoring signal is a signal obtained by integrating the clock error signal by a product branch path of the loop filter;
    所述插值控制器,用于根据滤波后的所述时钟误差信号确定所述B参数;The interpolation controller is configured to determine the B parameter according to the filtered clock error signal;
    所述信号特性参数修改器,用于判断所述监控信号是否在预置波动范围内,若否,则调整所述A参数以及C参数,使得所述监控信号在所述预置波动范围内。The signal characteristic parameter modifier is configured to determine whether the monitoring signal is within a preset fluctuation range, and if not, adjust the A parameter and the C parameter such that the monitoring signal is within the preset fluctuation range.
  2. 根据权利要求1所述的时钟恢复装置,其特征在于,所述信号调整器根据A参数对调整时钟相位后的所述第一、第二信号进行偏振角度调整,确 定目标正频谱信息以及目标负频谱信息,包括:The clock recovery device according to claim 1, wherein the signal adjuster adjusts the polarization angle of the first and second signals after adjusting the clock phase according to the A parameter. Target positive spectrum information and target negative spectrum information, including:
    所述信号调整器将调整时钟信号后的所述第一信号的正频谱信号乘以Cos(A),获得第一正频谱信号;将调整时钟信号后的所述第一信号的负频谱信号乘以Cos(A),获得第一负频谱信号;The signal adjuster multiplies the positive spectral signal of the first signal after adjusting the clock signal by Cos(A) to obtain a first positive spectral signal; multiplying the negative spectral signal of the first signal after adjusting the clock signal Obtaining a first negative spectral signal with Cos(A);
    将调整时钟信号后的所述第二信号的正频谱信号乘以Sin(A),获得第二正频谱信号;将调整时钟信号后的所述第二信号的负频谱信号乘以Sin(A),获得第二负频谱信号;Multiplying the positive spectral signal of the second signal after adjusting the clock signal by Sin(A) to obtain a second positive spectral signal; multiplying the negative spectral signal of the second signal after adjusting the clock signal by Sin(A) Obtaining a second negative spectral signal;
    将所述第一正频谱信号以及第二正频谱信号合并得到所述目标正频谱信息;将所述第一负频谱信号以及第二负频谱信号合并得到所述目标负频谱信息。Combining the first positive spectral signal and the second positive spectral signal to obtain the target positive spectral information; combining the first negative spectral signal and the second negative spectral signal to obtain the target negative spectral information.
  3. 根据权利要求2所述的时钟恢复装置,其特征在于,所述鉴相器根据所述目标正频谱信息以及目标负频谱信息确定时钟误差信号,包括:The clock recovery apparatus according to claim 2, wherein the phase detector determines the clock error signal according to the target positive spectrum information and the target negative spectrum information, including:
    所述鉴相器根据所述目标正频谱信息以及目标负频谱信息的全部频谱信息确定所述时钟误差信号。The phase detector determines the clock error signal according to the target positive spectrum information and all spectrum information of the target negative spectrum information.
  4. 根据权利要求1-3中任一项所述的时钟恢复装置,其特征在于,所述信号特性参数修改器调整所述A参数以及C参数,包括:The clock recovery apparatus according to any one of claims 1 to 3, wherein the signal characteristic parameter modifier adjusts the A parameter and the C parameter, including:
    所述信号特性参数修改器在第一预置调整范围内调整所述A参数,在第二预置调整范围内调整所述C参数。The signal characteristic parameter modifier adjusts the A parameter within a first preset adjustment range, and adjusts the C parameter within a second preset adjustment range.
  5. 根据权利要求1-4中任一项所述的时钟恢复装置,其特征在于,所述时钟恢复装置还包括:The clock recovery device according to any one of claims 1 to 4, wherein the clock recovery device further comprises:
    移位寄存器,用于根据D参数对输入至所述信号时钟补偿器的所述第一信号以及第二信号进行移位操作,所述D参数由所述插值控制器反馈至所述移位寄存器,所述D参数由所述插值控制器根据所述时钟误差信号确定。a shift register for performing a shift operation on the first signal and the second signal input to the signal clock compensator according to a D parameter, the D parameter being fed back to the shift register by the interpolation controller The D parameter is determined by the interpolation controller based on the clock error signal.
  6. 一种时钟恢复的方法,其特征在于,所述方法应用于时钟恢复装置,所述时钟恢复装置包括信号时钟补偿器、信号调整器、鉴相器、环路滤波器、插值控制器以及信号特性参数修改器,所述方法包括:A method for clock recovery, characterized in that the method is applied to a clock recovery device comprising a signal clock compensator, a signal adjuster, a phase detector, a loop filter, an interpolation controller, and signal characteristics A parameter modifier, the method comprising:
    信号时钟补偿器将输入至所述信号时钟补偿器的第一信号、第二信号转换为频域形式的信号,根据B参数以及C参数对经过所述转换后的第一信号、第二信号进行时钟相位的调整,并将调整时钟相位后的所述第一信号、第二信 号输出至所述信号调整器,所述第一、第二信号为光信号两个不同偏振态的信号,所述B参数由所述插值控制器反馈至所述信号时钟补偿器,所述C参数由所述信号特性参数修改器反馈至所述信号时钟补偿器;The signal clock compensator converts the first signal and the second signal input to the signal clock compensator into signals in the frequency domain form, and performs the converted first signal and the second signal according to the B parameter and the C parameter. Adjustment of the clock phase, and adjusting the first signal and the second signal after the clock phase And outputting to the signal adjuster, the first and second signals are signals of two different polarization states of the optical signal, and the B parameter is fed back by the interpolation controller to the signal clock compensator, the C The parameter is fed back to the signal clock compensator by the signal characteristic parameter modifier;
    所述信号调整器根据A参数对调整时钟相位后的所述第一信号、第二信号进行偏振角度调整,确定目标正频谱信息以及目标负频谱信息,将所述目标正频谱信息以及目标负频谱信息输出至所述鉴相器,所述A参数由所述信号特性参数修改器反馈至所述信号调整器,所述目标正频谱信息包括经过所述偏振角度调整后的所述第一信号、第二信号的正频谱信号,所述目标负频谱信息包括经过所述偏振角度调整后的所述第一信号、第二信号的负频谱信号;The signal adjuster adjusts the polarization angle of the first signal and the second signal after adjusting the clock phase according to the A parameter, and determines the target positive spectrum information and the target negative spectrum information, and the target positive spectrum information and the target negative spectrum. Information is output to the phase detector, the A parameter is fed back to the signal adjuster by the signal characteristic parameter modifier, and the target positive spectrum information includes the first signal after being adjusted by the polarization angle, a positive spectral signal of the second signal, the target negative spectral information comprising a negative spectral signal of the first signal and the second signal after the polarization angle adjustment;
    所述鉴相器根据所述目标正频谱信息以及目标负频谱信息确定时钟误差信号,并将所述时钟误差信号输出至所述环路滤波器;The phase detector determines a clock error signal according to the target positive spectrum information and the target negative spectrum information, and outputs the clock error signal to the loop filter;
    所述环路滤波器对所述时钟误差信号进行滤波,将滤波后的所述时钟误差信号输出至所述插值控制器,并将监控信号反馈至所述信号特性参数修改器,所述监控信号为所述环路滤波器的积分支路对所述时钟误差信号进行积分后的信号;The loop filter filters the clock error signal, outputs the filtered clock error signal to the interpolation controller, and feeds back a monitoring signal to the signal characteristic parameter modifier, the monitoring signal a signal obtained by integrating the clock error signal for a product branch path of the loop filter;
    所述插值控制器根据滤波后的所述定时误差信号确定所述B参数;The interpolation controller determines the B parameter according to the filtered timing error signal;
    所述信号特性参数修改器判断所述监控信号是否在预置波动范围内,若否,则调整所述A参数以及C参数,使得所述监控信号在所述预置波动范围内。The signal characteristic parameter modifier determines whether the monitoring signal is within a preset fluctuation range, and if not, adjusts the A parameter and the C parameter such that the monitoring signal is within the preset fluctuation range.
  7. 根据权利要求6所述的方法,其特征在于,所述信号调整器根据A参数对调整时钟相位后的所述第一、第二信号进行偏振角度调整,确定目标正频谱信息以及目标负频谱信息,包括:The method according to claim 6, wherein the signal adjuster adjusts the polarization angle of the first and second signals after adjusting the clock phase according to the A parameter, and determines the target positive spectrum information and the target negative spectrum information. ,include:
    所述信号调整器将调整时钟信号后的所述第一信号的正频谱信号乘以Cos(A),获得第一正频谱信号;将调整时钟信号后的所述第一信号的负频谱信号乘以Cos(A),获得第一负频谱信号;将调整时钟信号后的所述第二信号的正频谱信号乘以Sin(A),获得第二正频谱信号;将调整时钟信号后的所述第二信号的负频谱信号乘以Sin(A),获得第二负频谱信号;将所述第一正频谱信号以及第二正频谱信号合并得到所述目标正频谱信息,将所述第一负频谱信号以及第二负频谱信号合并得到所述目标负频谱信息。 The signal adjuster multiplies the positive spectral signal of the first signal after adjusting the clock signal by Cos(A) to obtain a first positive spectral signal; multiplying the negative spectral signal of the first signal after adjusting the clock signal Obtaining a first negative spectral signal with Cos(A); multiplying a positive spectral signal of the second signal after adjusting the clock signal by Sin(A) to obtain a second positive spectral signal; Multiplying the negative spectral signal of the second signal by Sin(A) to obtain a second negative spectral signal; combining the first positive spectral signal and the second positive spectral signal to obtain the target positive spectral information, the first negative The spectral signal and the second negative spectral signal are combined to obtain the target negative spectral information.
  8. 根据权利要求7所述的方法,其特征在于,所述鉴相器根据所述目标正频谱信息以及目标负频谱信息确定时钟误差信号,包括:The method according to claim 7, wherein the phase detector determines the clock error signal according to the target positive spectrum information and the target negative spectrum information, including:
    所述鉴相器根据所述目标正频谱信息以及目标负频谱信息的全部频谱信息确定所述时钟误差信号。The phase detector determines the clock error signal according to the target positive spectrum information and all spectrum information of the target negative spectrum information.
  9. 根据权利要求6-8中任一项所述的方法,其特征在于,所述信号特性参数修改器调整所述A参数以及C参数,包括:The method according to any one of claims 6-8, wherein the signal characteristic parameter modifier adjusts the A parameter and the C parameter, including:
    所述信号特性参数修改器在第一预置调整范围内调整所述A参数,在第二预置调整范围内调整所述C参数。The signal characteristic parameter modifier adjusts the A parameter within a first preset adjustment range, and adjusts the C parameter within a second preset adjustment range.
  10. 根据权利要求6-9中任一项所述的方法,其特征在于,所述时钟恢复装置还包括移位寄存器,所述方法还包括:The method of any of claims 6-9, wherein the clock recovery device further comprises a shift register, the method further comprising:
    所述移位寄存器根据D参数对输入至所述信号时钟补偿器的所述第一信号以及第二信号进行移位操作,所述D参数由所述插值控制器反馈至所述移位寄存器,所述D参数由所述插值控制器根据所述时钟误差信号确定。 The shift register performs a shift operation on the first signal and the second signal input to the signal clock compensator according to a D parameter, and the D parameter is fed back to the shift register by the interpolation controller, The D parameter is determined by the interpolation controller based on the clock error signal.
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