CN102859927A - Data and clock recovery module and data and clock recovery method - Google Patents
Data and clock recovery module and data and clock recovery method Download PDFInfo
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
- H04L7/0337—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/0807—Details of the phase-locked loop concerning mainly a recovery circuit for the reference signal
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
- H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
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Abstract
The embodiments of the present invention relate to a data and clock recovery module and a data and clock recovery method. The method includes: performing phase adjustment on a clock signal generated on the basis of the reference frequency according to a first control signal, and performing phase adjustment on a data signal according to the first control signal, wherein the phase adjustment direction of the clock signal is contrary to that of the data signal, the frequency of the clock signal is locked onto that of the data signal, and the first control signal is obtained by filtering the phase difference between the adjusted clock signal and the adjusted data signal; and sampling the adjusted data signal using the adjusted clock signal so as to obtain a data signal synchronous with the adjusted clock signal. The embodiments of the present invention reduce the synchronization time of the clock signal and the data signal, and improve the jitter performance.
Description
Technical field
The embodiment of the invention relates to communication technical field, and particularly a kind of data clock recovers module and data clock restoration methods.
Background technology
The light access more and more becomes the trend of broadband access, and EPON (Passive Optical Network, PON) is as the main technology of current light access, and it lays and study more and more extensive.Comprise optical line terminal (Optical Line Termination among the PON, OLT), Optical Distribution Node (Optical Distribution Node, ODN), optical network unit (Optical Network Unit, ONU), each OLT links together with the form of tree structure by ODN and a plurality of ONU, because each ONU is different from the OLT distance, the phase place of the data arrival OLT of each ONU emission is different, therefore, with before OLT communicates by letter, all need the clock synchronous with OLT at each ONU.
In the prior art, keep data-signal that OLT receives or OLT this locality clock signal both one of phase invariant, the phase place of regulating another signal is until data-signal and clock signal phase are synchronous.Yet this method so that data-signal and clock signal to arrive the synchronous time longer.
Summary of the invention
The embodiment of the invention provides a kind of data clock to recover module and data clock restoration methods, realizes reducing the lock in time of clock signal and data-signal.
On the one hand, the embodiment of the invention provides a kind of data clock to recover module, comprising: receiving interface, clock unit, the first phasing unit, the second phasing unit, phase detection unit and synchronizer;
Described clock unit is used for according to the reference frequency clocking, and described clock signal is inputed to described the first phasing unit, and the Frequency Locking of described clock signal is on the frequency of data-signal;
Described the first phasing unit be used for according to the first control signal of described phase detection unit feedback described clock signal being carried out the phase place adjustment, and the clock signal after will adjusting inputs to respectively described phase detection unit and described synchronizer;
Described receiving interface is used for reception of data signal;
Described the second phasing unit be used for according to described first control signal of described phase detection unit feedback described data-signal being carried out the phase place adjustment, and the data-signal after will adjusting inputs to respectively described phase detection unit and described synchronizer; The phase place of described the second phasing unit and described the first phasing unit is adjusted opposite direction;
Described phase detection unit, be used for obtaining clock signal after the described adjustment and the phase difference value of the data-signal after the described adjustment, described phase difference value is carried out filtering obtain described the first control signal, described the first control signal is fed back to respectively described the first phasing unit and described the second phasing unit;
Described synchronizer, the data-signal after being used for adopting clock signal after the described adjustment to described adjustment is sampled, obtain with described adjustment after the data-signal of clock signal synchronization.
On the other hand, the embodiment of the invention also provides a kind of data clock restoration methods, comprising:
According to the first control signal the clock signal that produces according to reference frequency is carried out the phase place adjustment, and according to described the first control signal data-signal is carried out the phase place adjustment; The phase place of described clock signal is adjusted the phase place of direction and described data-signal and is adjusted opposite direction; The Frequency Locking of described clock signal is on the frequency of data-signal; Described the first control signal is undertaken obtaining after the filtering by the phase difference value to the data-signal after the clock signal after the described adjustment and the described adjustment;
Data-signal after adopting clock signal after the described adjustment to described adjustment is sampled, obtain with described adjustment after the data-signal of clock signal synchronization.
The data clock that the embodiment of the invention provides recovers module and data clock restoration methods, the phase place of the data-signal by the clock signal that respectively this locality produced and reception is adjusted in the opposite direction, the phase place of the signal that phase place is leading pulls back, the phase place of phase lag signal is pushed out, realize the Phase synchronization of clock signal and data-signal, the two phase place is adjusted the lock in time that can realize reducing clock signal and data-signal simultaneously.
Description of drawings
In order to be illustrated more clearly in the embodiment of the invention or technical scheme of the prior art, the below will do to introduce simply to the accompanying drawing of required use in embodiment or the description of the Prior Art, apparently, accompanying drawing in the following describes only is some embodiments of the present invention, for those of ordinary skills, under the prerequisite of not paying creative work, can also obtain according to these accompanying drawings other accompanying drawing.
Fig. 1 is the structural representation that data clock provided by the invention recovers an embodiment of module;
Fig. 2 is the structural representation that data clock provided by the invention recovers an embodiment of clock unit in the module;
Fig. 3 is the structural representation that data clock provided by the invention recovers another embodiment of module;
Fig. 4 is the structural representation that data clock provided by the invention recovers another embodiment of clock unit in the module;
Fig. 5 is the flow chart of an embodiment of data clock restoration methods provided by the invention.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the invention, the technical scheme in the embodiment of the invention is clearly and completely described, obviously, described embodiment only is the present invention's part embodiment, rather than whole embodiment.Based on the embodiment among the present invention, those of ordinary skills belong to the scope of protection of the invention not making the every other embodiment that obtains under the creative work prerequisite.
Fig. 1 is the structural representation that data clock provided by the invention recovers an embodiment of module, as shown in Figure 1, this data clock recovery module comprises: receiving interface 1, clock unit 2, the first phasing unit 3, the second phasing unit 4, phase detection unit 5 and synchronizer 6;
The first phasing unit 3 be used for according to the first control signal of phase detection unit 5 feedbacks clock signal being carried out the phase place adjustment, and the clock signal after will adjusting inputs to respectively phase detection unit 5 and synchronizer 6;
Receiving interface 1 is used for reception of data signal;
The second phasing unit 4 be used for according to the first control signal of phase detection unit 5 feedbacks data-signal being carried out the phase place adjustment, and the data-signal after will adjusting inputs to respectively phase detection unit 5 and synchronizer 6; The phase place of the second phasing unit 3 and the first phasing unit 4 is adjusted opposite direction;
Synchronizer 6, the clock signal after be used for to adopt adjusting is sampled to the data-signal after adjusting, obtain with adjust after the data-signal of clock signal synchronization.
The data clock that the embodiment of the invention provides recovers module (Clock and Data Recovery, CDR), can be arranged on the OLT end of PON network, being used for will be from data-signal and the local clock signal synchronization that produces of CDR of each ONU termination receipts of PON network.
The CDR that the embodiment of the invention provides, its structure is based on pushing away-principle of La (push-pull) technology, in the process of carrying out the phase place adjustment, the phase place of the local clock signal that produces of the data-signal that receives and CDR is all adjusted, finally obtain synchronous phase place neither the original phase of data-signal, original phase that neither clock signal, but occupy a centre position of data-signal and clock signal original phase.Be understandable that, realize finally obtaining synchronous phase position, in the original phase of data-signal and clock signal, one leading, a hysteresis.Therefore, carry out in the process of phase place adjustment at CDR, in the original phase with data-signal and clock signal, the phase place of the signal that phase place is leading draws (pull) to return, the phase place of phase lag signal is pushed away (push) goes out, that is, the phase place of data-signal and clock signal is adjusted opposite direction.
For realizing the above-mentioned method of adjustment of CDR, among the CDR that the embodiment of the invention provides, the first phasing unit 3 and the second phasing unit 4 are set, wherein, the first phasing unit 3 is used for the clock signal that clock unit 2 produces is carried out the phase place adjustment, and the second phasing unit 4 is used for the data-signal that receives is carried out the phase place adjustment.Wherein, the first phasing unit 3 can adopt with the second phasing unit 4 possesses the mutually various devices of position adjusting function, for example: voltage control delay line (Voltage Controlled Delay Line, VCDL) etc.
Be appreciated that from the principle description partly of front Push-Pull technology, the phase place of the first phasing unit 3 and the second phasing unit 4 is adjusted opposite direction, to realize a data-signal and clock signal synchronization intermediate phase to data-signal original phase and clock signal original phase, and specifically which signal phase in clock signal and the data-signal is returned to this centre position, which signal phase is pushed into the centre position, depend on which signal is ahead of this centre position in clock signal and the data-signal, which signal lag is in this centre position.But need to guarantee that the first control signal that phase detection unit 5 feeds back to the first phasing unit 3 and the second phasing unit 4 is negative feedback, to guarantee a data-signal and clock signal synchronization intermediate phase to data-signal original phase and clock signal original phase.
The CDR that the embodiment of the invention provides, adopt the phase place of 3 pairs of clock signals of the first phasing unit to adjust, adopt the phase place of 4 pairs of data-signals of the second phasing unit to adjust, make the phase place of the two final phase place between clock signal original phase and data-signal original phase reach synchronous.Because the phase place adjustment of the first phasing unit 3 and the second phasing unit 4 is carried out synchronously, and the phase amplitude that each unit in the first phasing unit 3 and the second phasing unit 4 is adjusted, half of the phase amplitude of adjusting for a signal of only adjusting in clock signal and the data-signal, therefore, reduce the lock in time of clock signal and data-signal.
The data clock that the present embodiment provides recovers module, adjust in the opposite direction with the phase place of the data-signal that receives by the clock signal that respectively this locality is produced, the phase place of the signal that phase place is leading draws (pull) to return, the phase place of phase lag signal is pushed away (push) goes out, realize the Phase synchronization of clock signal and data-signal, the two phase place is adjusted the lock in time that can realize reducing clock signal and data-signal simultaneously.
Fig. 2 is the structural representation that data clock provided by the invention recovers an embodiment of clock unit in the module, and as shown in Figure 2, as a kind of feasible execution mode, the clock unit 2 among the CDR can comprise: Frequency Locking device 21 and voltage controlled oscillator 22; Wherein:
Voltage controlled oscillator 22 for generation of clock signal, inputs to the first phasing unit 3 and Frequency Locking device 21 with clock signal; Be used for adjusting according to the second control signal of Frequency Locking device 21 feedbacks the frequency of clock signal.
In the present embodiment, at the first phasing unit 3, the second phasing unit 4 and phase detection unit 5 consist of on the basis of the delay locked ring element with push-pull function jointly, clock unit 2 can be made of Frequency Locking device 21 and voltage controlled oscillator 22, behind voltage controlled oscillator 22 clockings, clock signal can be fed back to Frequency Locking device 21, Frequency Locking device 21 can be according to the clock signal frequency division of the divide ratio of being determined by frequency data signal to voltage controlled oscillator 22 feedbacks, clock signal behind the acquisition frequency division and the frequency-splitting of reference frequency, frequency-splitting is carried out filtering obtain the second control signal, and the second control signal fed back to voltage controlled oscillator 22, thereby make voltage controlled oscillator 22 can adjust according to the second control signal the frequency of clock signal.
Can find out, in the present embodiment, except the phase place that adopts 3 pairs of clock signals of the first phasing unit is adjusted, the frequency that also adopts 22 pairs of voltage controlled oscillators to input to the clock signal in the first phasing unit 3 is adjusted, thereby realizes adjusting the frequency of the clock signal in input the first phasing unit 3.
The data clock that this enforcement provides recovers module, the delay locked ring element that has the push-pull function in employing is adjusted with the phase place of the data-signal that receives in the opposite direction to the clock signal that this locality produces respectively, realize the Phase synchronization of clock signal and data-signal, can also adjust the frequency of the clock signal in the input phase adjustment unit by the voltage controlled oscillator in the clock unit, realize the Frequency Synchronization of clock signal and data-signal.The two phase place is adjusted the lock in time that can realize reducing clock signal and data-signal simultaneously, has heightened the jitter performance of data clock recovery module.
Fig. 3 is the structural representation that data clock provided by the invention recovers another embodiment of module, as shown in Figure 3, on basis embodiment illustrated in fig. 1, among the CDR that the embodiment of the invention provides, clock unit 2 can also be used for adjusting according to the first control signal of phase detection unit 5 feedbacks the phase place of clock signal.
In the present embodiment, jointly consist of on the basis of the delay locked ring element with push-pull function at the first phasing unit 3, the second phasing unit 4 and phase detection unit 5, phase detection unit 5 can also with by to the clock signal after adjusting and the phase difference value of the data-signal after adjusting carry out obtaining the first control signal after the filtering and input to clock unit 2, clock unit 2 can be adjusted the phase place of the clock signal that produces according to this first control signal.That is, clock unit 2 can be adjusted the phase place of the clock signal that inputs to the first phasing unit 3 according to the first control signal.
Fig. 4 is the structural representation that data clock provided by the invention recovers another embodiment of clock unit in the module, as shown in Figure 4, recover at data clock shown in Figure 3 on the basis of module, clock unit 2 can comprise: Frequency Locking device 21 and voltage controlled oscillator 22;
Voltage controlled oscillator 22 for generation of clock signal, inputs to the first phasing unit 3 and Frequency Locking device 21 with clock signal; Be used for adjusting according to the second control signal of Frequency Locking device 21 feedbacks the frequency of clock signal; Be used for adjusting according to the first control signal of phase detection unit 5 feedbacks the phase place of clock signal.
The clock unit that the present embodiment provides and embodiment illustrated in fig. 2 in the difference of the clock unit that provides be, voltage controlled oscillator 22 can also be adjusted according to the first control signal of phase detection unit 5 feedbacks the phase place of clock signal except adjusting the frequency of clock signal according to the second control signal adjustment that Frequency Locking device 21 produces.
Concrete, at the first phasing unit 3, the second phasing unit 4 and phase detection unit 5 consist of on the basis of the delay locked ring element with push-pull function jointly, phase detection unit 5, voltage controlled oscillator 22 and the first phasing unit 3 common formation phase locked looped function unit, in this phase locked looped function unit, phase detection unit 5 feeds back to voltage controlled oscillator 22 with the first control signal, thereby when making voltage controlled oscillator 22 adjust clock signal frequency according to Frequency Locking device 21, can also adjust according to this first control signal the phase place of clock signal.
Need to prove, because phase detection unit 5, in voltage controlled oscillator 22 and the first phasing unit 3 common phase locked looped function unit that consist of, the equivalent model of voltage controlled oscillator 22 is an integral processing, thereby the loop time constant of phase locked looped function unit is far longer than the loop time constant of delay locked ring element, this mainly is that the number of it is believed that of delay locked ring element logarithm and the clock signal with push-pull function carried out the phase place adjustment so that have larger phase difference value until data-signal and clock signal obtain Phase synchronization during this period of time detecting data-signal and clock signal from phase detection unit 5.And in this process, because the time constant of voltage controlled oscillator 22 is larger, therefore, the phase locked looped function unit is slower to the phase place adjustment of clock signal, can ignore the phase place adjustment of clock signal with respect to the delay locked ring element with push-pull function.In case and data-signal and clock signal obtain after the Phase synchronization, data-signal and clock signal have less phase difference value, in this case, the phase locked looped function unit has enough time to follow the tracks of this less phase difference value, thereby can carry out inching according to the first control signal to the phase place of clock signal by voltage controlled oscillator 22.And because the low frequency loop gain of phase locked looped function unit will be far longer than the delay locked ring element with push-pull function, therefore, after data-signal and clock signal obtain Phase synchronization, the phase locked looped function unit plays a leading role to the phase place adjustment of clock signal, and be adjusted into inching obtaining the later phase place of Phase synchronization, therefore can guarantee that CDR has good jitter performance.
The data clock that this enforcement provides recovers module, on the basis that the phase place of clock signal that the delay locked ring element that employing has a push-pull function produces this locality respectively and the data-signal that receives is adjusted in the opposite direction, can also adopt the phase locked looped function unit that clock signal is carried out inching, realize the Phase synchronization of clock signal and data-signal, the two phase place is adjusted the lock in time that can realize reducing clock signal and data-signal simultaneously, has heightened the jitter performance of data clock recovery module.
On the basis of aforementioned each embodiment, the present embodiment provides a kind of concrete structure of phase detection unit, and phase detection unit can comprise: phase-detection subelement and loop filter; Wherein:
The phase-detection subelement is for detection of the phase difference value of the data-signal after the clock signal after being adjusted and the adjustment;
Loop filter is used for the phase difference value signal of phase-detection subelement output is carried out filtering, obtains the first control signal, and the first control signal is inputed to respectively the first phasing unit and the second phasing unit.
Owing to usually carrying the high frequency signals such as pulse signal in the clock signal after the detection of phase-detection subelement is adjusted and the phase difference value of the data-signal after the adjustment, may affect the first phasing unit and the second phasing unit to the accuracy of clock signal and data signal phase adjustment.Therefore, can carry out filtering by the phase difference value that loop filter is exported the phase-detection subelement, the HFS that filters out in the phase difference value obtains the first control signal, and the first control signal of low frequency is inputed to respectively in the first phasing unit and the second phasing unit.Wherein, loop filter can adopt existing various filter with filter function.
Optionally, among the CDR amplifier can also be set, the data-signal that receiving interface 1 is received amplifies shaping, data-signal after the amplification shaping is inputted the second phasing unit, so that the first phasing unit and the second phasing unit are more accurate to the phase place adjustment of clock signal and data-signal.
The data clock that the present embodiment provides recovers module, adjust in the opposite direction with the phase place of the data-signal that receives by the clock signal that respectively this locality is produced, the phase place of the signal that phase place is leading pulls back, the phase place of phase lag signal is pushed out, realize the Phase synchronization of clock signal and data-signal, the two phase place is adjusted the lock in time that can realize reducing clock signal and data-signal simultaneously.Clock signal after detection is adjusted and adjust after the phase difference value of data-signal after, adopt filter to carry out filtering, remove the interference signal such as pulse and obtain the first control signal, thereby improve the accuracy that data-signal and clock signal phase are adjusted.In addition, adopt amplifier that data-signal is amplified shaping, further reduce interference signal to the interference of data-signal.
Fig. 5 is the flow chart of an embodiment of data clock restoration methods provided by the invention, and as shown in Figure 5, the method comprises:
S501, according to the first control signal the clock signal that produces according to reference frequency is carried out the phase place adjustment, and according to the first control signal data-signal is carried out the phase place adjustment; The phase place of clock signal is adjusted the phase place of direction and data-signal and is adjusted opposite direction; The Frequency Locking of clock signal is on the frequency of data-signal; The first control signal is undertaken obtaining after the filtering by the phase difference value to the clock signal after adjusting and the data-signal after the adjustment;
S502, the clock signal after adopt adjusting are sampled to the data-signal after adjusting, obtain with adjust after the data-signal of clock signal synchronization.
The executive agent of above step is that data clock recovers module CDR, and this data clock recovers module and can be arranged on the OLT in the PON network.
Optionally, the Frequency Locking of clock signal specifically can comprise on the frequency of data-signal: the frequency of clock signal is according to the second control signal adjustment; The second control signal by according to divide ratio to the clock signal frequency division, obtain clock signal behind the frequency division and the frequency-splitting of reference frequency, and frequency-splitting carried out obtaining after the filtering; Divide ratio is determined according to the frequency of data-signal.The second control signal can be negative-feedback signal.
Optionally, CDR carries out before the phase place adjustment the clock signal that produces according to reference frequency according to the first control signal, and is all right: the phase place of adjusting clock signal according to the first control signal.
Optionally, CDR carries out before the phase place adjustment data-signal according to the first control signal, and is all right:, data-signal is amplified shaping.
Wherein, the first control signal can be negative-feedback signal.
The executive agent of above step is that data clock recovers module, and the process of its concrete structure and performed data clock restoration methods can referring to the associated description among the data clock recovery module embodiment provided by the invention, not repeat them here.
The data clock restoration methods that the embodiment of the invention provides, the phase place of the data-signal that receives by the clock signal that respectively this locality produced with from optical network unit is adjusted in the opposite direction, the phase place of the signal that phase place is leading pulls back, the phase place of phase lag signal is pushed out, realize the Phase synchronization of clock signal and data-signal, the two phase place is adjusted the lock in time that can realize reducing clock signal and data-signal simultaneously.
One of ordinary skill in the art will appreciate that: all or part of step that realizes above-mentioned each embodiment of the method can be finished by the relevant hardware of program command.Aforesaid program can be stored in the computer read/write memory medium.This program is carried out the step that comprises above-mentioned each embodiment of the method when carrying out; And aforesaid storage medium comprises: the various media that can be program code stored such as ROM, RAM, magnetic disc or CD.
It should be noted that at last: above embodiment only in order to technical scheme of the present invention to be described, is not intended to limit; Although with reference to previous embodiment the present invention is had been described in detail, those of ordinary skill in the art is to be understood that: it still can be made amendment to the technical scheme that aforementioned each embodiment puts down in writing, and perhaps part technical characterictic wherein is equal to replacement; And these modifications or replacement do not make the essence of appropriate technical solution break away from the spirit and scope of various embodiments of the present invention technical scheme.
Claims (12)
1. a data clock recovers module, it is characterized in that, comprising: receiving interface, clock unit, the first phasing unit, the second phasing unit, phase detection unit and synchronizer;
Described clock unit is used for according to the reference frequency clocking, and described clock signal is inputed to described the first phasing unit; The Frequency Locking of described clock signal is on the frequency of data-signal;
Described the first phasing unit be used for according to the first control signal of described phase detection unit feedback described clock signal being carried out the phase place adjustment, and the clock signal after will adjusting inputs to respectively described phase detection unit and described synchronizer;
Described receiving interface is used for reception of data signal;
Described the second phasing unit be used for according to described first control signal of described phase detection unit feedback described data-signal being carried out the phase place adjustment, and the data-signal after will adjusting inputs to respectively described phase detection unit and described synchronizer; The phase place of described the second phasing unit and described the first phasing unit is adjusted opposite direction;
Described phase detection unit, be used for obtaining clock signal after the described adjustment and the phase difference value of the data-signal after the described adjustment, described phase difference value is carried out filtering obtain described the first control signal, described the first control signal is fed back to respectively described the first phasing unit and described the second phasing unit;
Described synchronizer, the data-signal after being used for adopting clock signal after the described adjustment to described adjustment is sampled, obtain with described adjustment after the data-signal of clock signal synchronization.
2. data clock according to claim 1 recovers module, it is characterized in that, described clock unit comprises: Frequency Locking device and voltage controlled oscillator;
Described Frequency Locking device, be used for according to the clock signal frequency division of divide ratio to described voltage controlled oscillator feedback, clock signal behind the acquisition frequency division and the frequency-splitting of described reference frequency, described frequency-splitting is carried out filtering obtain the second control signal, described the second control signal is fed back to described voltage controlled oscillator; Described divide ratio is determined according to the frequency of described data-signal;
Voltage controlled oscillator for generation of described clock signal, inputs to described the first phasing unit and described Frequency Locking device with described clock signal; Be used for adjusting according to described second control signal of described Frequency Locking device feedback the frequency of described clock signal.
3. data clock according to claim 1 recovers module, it is characterized in that, described clock unit also is used for adjusting according to the first control signal of described phase detection unit feedback the phase place of described clock signal.
4. data clock according to claim 3 recovers module, it is characterized in that, described clock unit comprises: Frequency Locking device and voltage controlled oscillator;
Described Frequency Locking device, be used for according to the clock signal frequency division of divide ratio to described voltage controlled oscillator feedback, clock signal behind the acquisition frequency division and the frequency-splitting of described reference frequency, described frequency-splitting is carried out filtering obtain the second control signal, described the second control signal is fed back to described voltage controlled oscillator; Described divide ratio is determined according to the frequency of described data-signal;
Voltage controlled oscillator for generation of described clock signal, inputs to described the first phasing unit and described Frequency Locking device with described clock signal; Be used for adjusting according to described second control signal of described Frequency Locking device feedback the frequency of described clock signal; Be used for adjusting according to the first control signal of described phase detection unit feedback the phase place of described clock signal.
5. each described data clock recovers module according to claim 1-4, it is characterized in that, described phase detection unit comprises: phase-detection subelement and loop filter;
Described phase-detection subelement is used for obtaining clock signal after the described adjustment and the phase difference value of the data-signal after the described adjustment;
Described loop filter, be used for the described phase difference value of described phase-detection subelement output is carried out filtering, obtain described the first control signal, and described the first control signal is inputed to respectively described the first phasing unit and described the second phasing unit.
6. each described data clock recovers module according to claim 1-5, it is characterized in that, also comprises:
Amplifier is used for the described data-signal that described receiving interface receives is amplified shaping, and the data-signal after the amplification shaping is inputted described the second phasing unit.
7. each described data clock recovers module according to claim 1-6, it is characterized in that, described the first control signal is negative-feedback signal.
8. a data clock restoration methods is characterized in that, comprising:
According to the first control signal the clock signal that produces according to reference frequency is carried out the phase place adjustment, and according to described the first control signal data-signal is carried out the phase place adjustment; The phase place of described clock signal is adjusted the phase place of direction and described data-signal and is adjusted opposite direction; The Frequency Locking of described clock signal is on the frequency of data-signal; Described the first control signal is undertaken obtaining after the filtering by the phase difference value to the data-signal after the clock signal after the described adjustment and the described adjustment;
Data-signal after adopting clock signal after the described adjustment to described adjustment is sampled, obtain with described adjustment after the data-signal of clock signal synchronization.
9. method according to claim 8 is characterized in that, the Frequency Locking of described clock signal specifically comprises on the frequency of data-signal:
The frequency of described clock signal is according to the second control signal adjustment; Described the second control signal by according to divide ratio to described clock signal frequency division, obtain clock signal behind the frequency division and the frequency-splitting of described reference frequency, and described frequency-splitting carried out obtaining after the filtering; Described divide ratio is determined according to the frequency of described data-signal.
10. according to claim 8 or 9 described methods, it is characterized in that, describedly according to the first control signal the clock signal that produces according to reference frequency carried out also comprising before the phase place adjustment:
Adjust the phase place of described clock signal according to described the first control signal.
11. each described method is characterized in that according to claim 8-10, describedly according to described the first control signal data-signal is carried out also comprising before the phase place adjustment:
Described data-signal is amplified shaping.
12. each described method is characterized in that according to claim 8-11, described the first control signal is negative-feedback signal.
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| Application Number | Priority Date | Filing Date | Title |
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| PCT/CN2012/075299 WO2012126420A2 (en) | 2012-05-10 | 2012-05-10 | Data and clock recovery module and data and clock recovery method |
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| CN102859927A true CN102859927A (en) | 2013-01-02 |
| CN102859927B CN102859927B (en) | 2015-03-11 |
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| WO2012126420A2 (en) * | 2012-05-10 | 2012-09-27 | 华为技术有限公司 | Data and clock recovery module and data and clock recovery method |
| CN104135413A (en) * | 2014-07-29 | 2014-11-05 | 北京航天自动控制研究所 | High-speed serial bus sampling system suitable for multipoint interconnection application occasion |
| CN105099442A (en) * | 2014-05-22 | 2015-11-25 | 亚德诺半导体集团 | Apparatus and method for modular signal acquisition and detection |
| WO2018040011A1 (en) * | 2016-08-31 | 2018-03-08 | 华为技术有限公司 | Clock recovery apparatus and clock recovery method |
| CN110299915A (en) * | 2019-05-05 | 2019-10-01 | 厦门星宸科技有限公司 | Clock recovery circuitry |
| CN111092714A (en) * | 2019-12-10 | 2020-05-01 | 中国科学院微电子研究所 | High-speed signal clock recovery method and device |
| CN113078978A (en) * | 2021-03-26 | 2021-07-06 | 杭州加速科技有限公司 | Synchronization method, system and test method for remote multi-ATE semiconductor test equipment |
| CN113507286A (en) * | 2021-06-16 | 2021-10-15 | 深圳市傲科光电子有限公司 | Method, apparatus and computer readable storage medium for determining clock signal |
| CN115378567A (en) * | 2022-08-19 | 2022-11-22 | 深圳市紫光同创电子有限公司 | Clock synchronization circuit, clock synchronization method and electronic equipment |
| WO2024103269A1 (en) * | 2022-11-16 | 2024-05-23 | 华为技术有限公司 | Time synchronization method and apparatus |
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| WO2013169860A1 (en) | 2012-05-09 | 2013-11-14 | Zafgen, Inc. | Fumigillol type compounds and methods of making and using same |
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| WO2012126420A3 (en) * | 2012-05-10 | 2013-04-18 | 华为技术有限公司 | Data and clock recovery module and data and clock recovery method |
| WO2012126420A2 (en) * | 2012-05-10 | 2012-09-27 | 华为技术有限公司 | Data and clock recovery module and data and clock recovery method |
| CN105099442A (en) * | 2014-05-22 | 2015-11-25 | 亚德诺半导体集团 | Apparatus and method for modular signal acquisition and detection |
| CN105099442B (en) * | 2014-05-22 | 2019-06-14 | 亚德诺半导体集团 | The device and method of modular signal acquisition and detection |
| CN104135413A (en) * | 2014-07-29 | 2014-11-05 | 北京航天自动控制研究所 | High-speed serial bus sampling system suitable for multipoint interconnection application occasion |
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| CN111092714A (en) * | 2019-12-10 | 2020-05-01 | 中国科学院微电子研究所 | High-speed signal clock recovery method and device |
| CN111092714B (en) * | 2019-12-10 | 2022-05-06 | 中国科学院微电子研究所 | High-speed signal clock recovery method and device |
| CN113078978A (en) * | 2021-03-26 | 2021-07-06 | 杭州加速科技有限公司 | Synchronization method, system and test method for remote multi-ATE semiconductor test equipment |
| CN113507286A (en) * | 2021-06-16 | 2021-10-15 | 深圳市傲科光电子有限公司 | Method, apparatus and computer readable storage medium for determining clock signal |
| CN115378567A (en) * | 2022-08-19 | 2022-11-22 | 深圳市紫光同创电子有限公司 | Clock synchronization circuit, clock synchronization method and electronic equipment |
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Also Published As
| Publication number | Publication date |
|---|---|
| WO2012126420A2 (en) | 2012-09-27 |
| CN102859927B (en) | 2015-03-11 |
| WO2012126420A3 (en) | 2013-04-18 |
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