CN113078978A - Synchronization method, system and test method for remote multi-ATE semiconductor test equipment - Google Patents
Synchronization method, system and test method for remote multi-ATE semiconductor test equipment Download PDFInfo
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- H—ELECTRICITY
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Abstract
The invention provides a synchronization method, a system and a test method for remote multi-ATE semiconductor test equipment, wherein the synchronization method comprises the following steps: the clock transmitting device transmits clock coding signals embedded with clock signals to a plurality of test devices through high-speed optical fibers; the test equipment receives the clock coding signal to recover the clock, and adjusts the clock of the test equipment to be consistent with the clock of the clock sending device according to the clock adjusting system; the clock sending device sends the trigger code signals embedded with the trigger signals to a plurality of test devices through the high-speed optical fibers; the test equipment receives and returns the trigger code signal to the clock sending device through the high-speed optical fiber; the clock sending device adjusts the time point of sending the trigger code signal according to the time difference of receiving the trigger code signal. The invention utilizes 25Gbps high-speed optical fiber to transmit signals, realizes the synchronous clock and synchronous triggering target among a plurality of high-precision long-distance semiconductor test devices, and has the characteristics of long synchronous distance, low cost and high precision.
Description
Technical Field
The invention relates to the field of ATE semiconductor test equipment, and particularly provides a method, a system and a method for synchronizing remote multi-ATE semiconductor test equipment.
Background
The development of many modern technologies does not depart from the progress of testing technology, and the testing technology is the source technology of information. With the development of the times, the requirements of people on the accuracy of the acquired information are gradually improved, and the requirements of modern test technology cannot be met by single independent test and centralized test.
Ate (automatic Test equipment) is automatic Test equipment, which is a system for automatically testing integrated circuits through computers and special equipment. ATE semiconductor test equipment is used to test the integrity of the function and performance of integrated circuits and is an important device in ensuring the quality of integrated circuits in the manufacturing process of integrated circuits. The semiconductor test equipment requires that the working clocks of the same service board in all the equipment are consistent and can be triggered to work synchronously. Clocks of similar chips on different test equipment need to meet the principle of same frequency and same phase, the phase error of the clocks of the middle and high-end test equipment is required to be within 100ps, and the frequencies must be completely consistent.
With the development of semiconductor technology, the scale of integrated circuits and the size of wafers are getting larger and larger, and often multiple testers are required to cooperatively operate to test the same semiconductor, so that multiple testers are required to have the same clock and synchronously receive trigger signals to cooperatively operate. In order to achieve the purpose, in the prior art, a clock signal source and a trigger signal source are generally sent to a plurality of test devices through electric signals, so that clock synchronization and trigger synchronization among the plurality of test devices are realized; however, the electrical signal will be attenuated during the propagation process, and when the testing equipment is far away from the signal source, the attenuation of the electrical signal is serious, and the quality and integrity of the signal are poor, so that the method is not suitable for transmitting the signal to a plurality of remote semiconductor testing equipment. In the device test, for example, in a high-speed wireless communication chip such as 5G device communication, extremely high test precision is required, and the synchronization of the clock and the triggering directly affects the accuracy of the chip test.
Therefore, a method and system for synchronizing clock and trigger among remote multi-semiconductor test equipment is needed to meet the requirement of the multi-semiconductor test equipment working together to test high-precision semiconductors.
Disclosure of Invention
Based on the problems in the prior art, the invention provides a synchronization method, a system and a test method for remote multi-ATE semiconductor test equipment, and the specific scheme is as follows:
a synchronization method for remote multi-ATE semiconductor test equipment comprises the following steps:
the clock transmitting device transmits clock coding signals embedded with clock signals to a plurality of test devices through high-speed optical fibers;
the test equipment receives the clock code and recovers a clock by a signal, and the clock of the test equipment is adjusted to be consistent with the clock of the clock sending device by combining a clock adjusting system;
the clock sending device sends the trigger code signals embedded with the trigger signals to a plurality of test devices through the high-speed optical fibers;
the test equipment receives the trigger code signal and returns the trigger code signal to the clock sending device through the high-speed optical fiber;
and the clock sending device receives the trigger code signal and adjusts the time for sending the trigger code signal to the test equipment according to the time difference for receiving the trigger code signal, so that the aim that a plurality of test equipment simultaneously receive the trigger code signal is fulfilled.
In one embodiment, the clock adjustment system includes an external crystal oscillator and an analog phase-locked loop;
the step of receiving the clock code and recovering a clock from a signal by the test equipment, and adjusting the clock of the test equipment to be consistent with the clock of the clock sending device by combining a clock adjusting system specifically includes:
the test equipment receives the clock coding signal;
the analog phase-locked loop generates a first clock by taking the clock of the external crystal oscillator as a reference clock and sends the first clock to the clock data recovery unit;
the clock data recovery unit takes the first clock as a reference clock, recovers the clock coding signal into a first recovered clock and sends the first recovered clock to the analog phase-locked loop;
the analog phase-locked loop uses the first recovery clock as a reference clock, generates a second clock and sends the second clock to the clock data recovery unit;
and the clock data recovery unit takes the second clock as a reference clock and adjusts the clock frequency of the test equipment to be consistent with the clock frequency of the clock sending device.
In a specific embodiment, the clock adjustment system further comprises a phase adjustment unit;
after "the clock data recovery unit adjusts the clock frequency of the test equipment to be consistent with the clock frequency of the clock transmission device with the second clock as a reference clock", the method further comprises,
and displaying the clock phase of the test equipment through an external oscilloscope, establishing communication between the phase adjusting unit and the analog phase-locked loop through I2C, and gradually adjusting the clock phase of the analog phase-locked loop with preset precision until the clock phase of the test equipment is consistent with the clock phase of the clock sending device.
In a specific embodiment, the step of the clock sending device receiving the trigger code signal and adjusting the time for sending the trigger code signal to the test devices according to the time difference for receiving the trigger code signal so as to achieve the purpose that a plurality of test devices receive the trigger code signal at the same time includes:
the clock sending device receives the trigger code signals sent by the test equipment, obtains the time for the clock sending device to receive the trigger code signals, and delays the time for the clock sending device to send the trigger code signals to other test equipment by taking the test equipment with the longest time for receiving the trigger code signals as a reference until the plurality of test equipment receive the trigger code signals at the same time.
In a specific embodiment, a physical coding sublayer is arranged in the clock sending device;
embedding the clock signal into the clock encoded signal by the physical coding sublayer;
embedding the trigger signal into the trigger code signal by the physical coding sublayer.
In a specific embodiment, the predetermined precision is 2ps, and/or the bandwidth of the high-speed optical fiber is 25 Gbps.
A remote multi-ATE semiconductor test equipment synchronization system is suitable for the remote multi-ATE semiconductor test equipment synchronization method, and comprises a clock sending device, a high-speed optical fiber and a plurality of test equipment, wherein the clock sending device is connected with the plurality of test equipment through the high-speed optical fiber;
the clock sending device is used for sending clock coding signals and trigger coding signals to a plurality of test devices through a high-speed optical fiber, receiving the trigger coding signals through the high-speed optical fiber and adjusting the sending time of the trigger coding signals according to the time for receiving the trigger coding signals;
the test equipment is used for receiving the clock coding signal and the trigger coding signal sent by the clock sending device, adjusting a clock according to the clock coding signal, and returning the received trigger coding signal to the clock sending device.
In a specific embodiment, the clock transmission apparatus includes:
a signal generation unit: for generating a clock signal and a trigger signal;
an encoding unit: the physical coding sublayer is arranged and used for embedding a clock signal into a clock coding signal, embedding a trigger signal into a trigger coding signal and sending the clock coding signal and the trigger coding signal to the test equipment through the high-speed optical fiber;
a time adjustment unit: and the device is used for receiving the trigger code signal and adjusting the sending time of the trigger code signal according to the time for receiving the trigger code signal until the plurality of test equipment simultaneously receive the trigger code signal.
In a specific embodiment, the test device is provided with:
a clock data recovery unit: for receiving and decoding the clock encoded signal;
the clock adjusting system comprises: the clock sending device is used for sending a clock of the test equipment to the external crystal oscillator; the phase-locked loop circuit comprises an analog phase-locked loop, an external crystal oscillator and a phase adjusting unit;
a phase adjustment unit: the device is used for establishing communication with the analog phase-locked loop through I2C and gradually adjusting the analog phase-locked loop with preset precision until the clock phase of the test equipment is consistent with the clock phase of the clock sending device.
A remote multi-ATE semiconductor test equipment testing method comprises clock synchronization and trigger synchronization, wherein the clock synchronization comprises the following steps:
the clock sending device sends a clock coding signal embedded with a clock signal to a plurality of test devices through a high-speed optical fiber, and each test device adjusts the clock to be consistent with the clock of the clock sending device according to the clock coding signal;
triggering synchronization includes:
the clock sending device sends the trigger code signals embedded with the trigger signals to a plurality of test devices through the high-speed optical fibers, and adjusts the time for sending the trigger code signals according to the time for receiving the trigger code signals returned by the test devices until the plurality of test devices receive the trigger code signals at the same time.
The invention has the following beneficial effects: the invention provides a method, a system and a test method for synchronizing multiple long-distance ATE semiconductor devices, realizes the purposes of synchronizing clocks and triggering synchronously among the test devices in a long distance, and has the characteristics of high test precision and low cost. The traditional electric signal transmission is replaced by high-speed optical fiber transmission, so that the problem of attenuation of the electric signal in the transmission process is solved, and the remote equipment test is realized. Self-locking is formed through the FPGA and the analog phase-locked loop, so that the clocks of the test equipment have the same frequency at high precision. The clock phase of the equipment is adjusted through the phase adjusting unit, and the problem of the synchronization precision of the remote equipment test in the prior art is solved. And adjusting the time for sending the signals according to the time for the trigger code signals to reach each test device, so that each test device receives the trigger code signals simultaneously to carry out trigger synchronization.
In order to make the aforementioned and other objects, features and advantages of the present invention comprehensible, preferred embodiments accompanied with figures are described in detail below.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the embodiments are simply received below, it should be understood that the following drawings only illustrate some embodiments of the present invention, and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained according to the drawings without inventive efforts.
FIG. 1 is a flow chart of a method for synchronizing remote multiple ATE semiconductor test equipment according to the present invention;
FIG. 2 is a flow chart of the test equipment of the present invention decoding a clock encoded signal;
fig. 3 is a schematic diagram of the structure of the remote device synchronization system of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The invention provides a synchronization method, a system and a test method for remote multi-ATE semiconductor test equipment, aiming at the problem of low test precision of remote equipment in the prior art, and the synchronization method, the system and the test method are used for recovering a clock and a trigger coding signal by using a 25Gbps high-speed data transmission line so as to achieve the clock and trigger targets between high-precision remote synchronization equipment.
Example 1
The embodiment provides a synchronization method for remote multi-ATE semiconductor test equipment, which can realize the requirement of maintaining high precision in remote test by transmitting a clock signal and a trigger signal through a high-speed optical fiber. The specific scheme is as follows:
a synchronization method for remote multi-ATE semiconductor test equipment comprises two parts of clock synchronization and trigger synchronization, wherein an electrical port for transmitting a clock signal and a trigger signal is removed on the basis of the original equipment test method, the clock signal and the trigger signal are transmitted through a high-speed optical fiber, and the limitation that the conventional optical fiber is only used for transmitting data is broken through under the condition that the test cost is not increased. Specifically, as shown in the attached figure 1 of the specification, the method comprises the following steps:
s1, the clock sending device sends the clock coding signal embedded with the clock signal to a plurality of test devices through the high-speed optical fiber;
s2, the test equipment receives the clock code and recovers the clock by the signal, and the clock of the test equipment is adjusted to be consistent with the clock of the clock sending device by combining the clock adjusting system;
s3, the clock sending device sends the trigger code signal embedded with the trigger signal to a plurality of test devices through the high-speed optical fiber;
s4, the test equipment receives the trigger code signal and returns the trigger code signal to the clock sending device through the high-speed optical fiber;
s5, the clock sending device receives the trigger code signal, and adjusts the time for sending the trigger code signal to the test equipment according to the time difference for receiving the trigger code signal, thereby achieving the purpose that a plurality of test equipment receive the trigger code signal at the same time.
Wherein, the clock sending device and the test equipment are both provided with an FPGA (field Programmable Gate array). The FPGA device belongs to a semi-custom circuit in an application-specific integrated circuit and is a programmable logic array. The basic structure of the FPGA comprises a programmable input/output unit, a configurable logic block, a digital clock management module, an analog phase-locked loop, an embedded block RAM, a high-speed serial transceiver, a wiring resource, an embedded special hard core and a bottom layer embedded functional unit. The FPGA has the characteristics of abundant wiring resources, high repeatable programming and integration level and low investment, and is widely applied to the field of digital circuit design. The FPGA is provided with a high-speed serial transceiver, and the high-speed serial transceiver is provided with a Physical Medium Attachment (PMA) sublayer, a Physical Coding Sublayer (PCS) and a Clock and Data Recovery-CDR (Clock and Data Recovery-CDR). The clock sending device is also provided with a plurality of high-speed optical fiber interfaces for transmitting signals. The FPGA on the clock sending device is provided with a time detection module and an adjustment module, and the time detection module is used for detecting the signal difference of different test devices received by the clock sending device and carrying out corresponding time adjustment through the adjustment module according to the signal difference. It should be noted that the clock signal of the clock transmission device is generated by the constant temperature crystal oscillator of the clock transmission device, and the final usage clock of each semiconductor test apparatus coincides with the clock signal, that is, is homologous to the very stable crystal oscillator clock of the clock transmission device.
Step S1 specifically includes: the clock sending device generates a clock signal, a Physical Coding Sublayer (PCS) in the high-speed serial transceiver codes the clock signal, the coding process comprises the steps of embedding the clock signal into the clock coding signal, the clock coding signal is a data stream with balanced 0 and 1, and the clock coding signal is transmitted to a plurality of test devices through a high-speed optical fiber. The electric signal in the high-speed serial transceiver is converted into an optical signal through the photoelectric conversion module and then transmitted through the high-speed optical fiber. Preferably, the high-speed fiber parameter selected by the present embodiment is 25 Gbps.
Step S2 specifically includes: the high-speed optical fiber interface on the test equipment receives the clock coding signal sent by the clock sending device, the CDR on the FPGA of the test equipment, namely the clock data recovery unit decodes the clock coding signal to obtain the clock signal, and the clock signal at the moment is basically consistent with the clock coding signal generated by the clock sending device, but has certain error. And adjusting the clock of the test equipment to be synchronous with the clock of the clock sending device through the clock data recovery unit and the clock adjusting system. The clock adjusting system comprises an analog phase-locked loop, an external crystal oscillator and a phase adjusting unit.
The specific steps are shown in the attached figure 2 in the specification. When the clock recovery method is started, the analog phase-locked loop takes an external crystal oscillator as a reference clock, the external crystal oscillator sends a crystal oscillator signal to the analog phase-locked loop, the analog phase-locked loop generates a first clock according to the crystal oscillator signal and sends the first clock to the CDR, and the CDR carries out clock recovery by taking the first clock as the reference clock, generates a first recovery clock and sends the first recovery clock to the analog phase-locked loop. The analog phase-locked loop takes the first recovery clock as a reference clock, the analog phase-locked loop and the recovery clock of the CDR form closed loop self-locking at the moment, the analog phase-locked loop generates a second clock according to the first recovery clock and sends the second clock to the CDR for clock recovery, the CDR takes the second clock as the reference clock to generate a clock coding signal, the clock coding signal at the moment is basically the same as the clock coding signal generated by the clock sending device, and namely the clock of the test equipment and the clock of the clock sending device have the same frequency. The plurality of test equipment receive the clock signals sent by the same clock sending device, so that the clocks of the plurality of test equipment have high precision and the same frequency and the phases are basically consistent. Furthermore, the phase of the clock is corrected through the phase adjusting unit, so that the clocks among different test devices not only have the same frequency, but also have the same phase. The test equipment is connected through the high-speed optical fiber, the phase between any two test equipment can be corrected by carrying the test equipment, and the output phase of the clock of the analog phase-locked loop is adjusted through I2C, so that the user clock output by the analog phase-locked loop and the clock transmitted by the clock transmitting unit are in the same frequency and phase. The external high-precision oscilloscope is used for displaying the clock phase of the test equipment in real time, and the phase adjusting unit is communicated with the analog phase-locked loop through the I2C to adjust the analog phase-locked loop step by step with preset precision until the clock phase of the test equipment is consistent with the clock phase of the clock sending device. In this embodiment, the preset precision is 2ps, that is, the phase adjustment unit gradually adjusts the analog pll in units of 2ps until the clock phases between the testing devices are the same, and the adjustment precision can be controlled within at least 10ps, which completely meets the precision required by the testing of high-end devices. After the phase adjustment, the test equipment is moved back to the original position, and at the moment, the test equipment at different positions has the same frequency and the same phase height.
Steps S3 and S4 specifically include: the clock sending device generates a trigger signal and encodes the trigger signal into a trigger code signal through the PCS, the trigger code signal is sent to a plurality of test devices through the high-speed optical fiber, and the test devices receive the trigger code signal and return the trigger code signal to the clock sending device through the high-speed optical fiber. After the processing of the steps S1 and S2, the clocks between the test devices are in the same frequency and phase. The trigger code signal comprises bit stream data consisting of 0 and 1, and the trigger code signal reaches the test equipment and returns to the clock sending device immediately, so that the trigger time of the trigger code signal from the clock sending device to the test equipment is half of the time difference from the sending of the trigger code signal to the receiving of the trigger code signal by the clock sending device.
Step S5 specifically includes: the clock sending device receives the trigger code signal, and adjusts the time for sending the trigger code signal by the test equipment according to the time difference of receiving the trigger code signal until the plurality of test equipment receive the trigger code signal at the same time. If the position difference between the test devices is not large, the clock sending device simultaneously sends the trigger code signals to the plurality of test devices, each test device simultaneously receives the trigger code signals, and then simultaneously sends the trigger code signals back to the clock sending device, and the clock sending device simultaneously receives the trigger code signals fed back by each test device. If the position difference between the test devices is large and the distance is extremely long, the time of the trigger code signal reaching the test devices is different, and the time of the clock sending device receiving the trigger code signal sent by each test device is also different. The specified trigger time is the time when the trigger code signal arrives at the test equipment from the clock transmission device, namely half of the time difference between the time when the clock transmission device transmits the trigger code signal and the time when the trigger code signal is received. The clock sending device adjusts the time for sending the trigger code signal according to the trigger time of each test device, calculates the time difference between the trigger time of other test devices and the trigger time of the test device by taking the test device with the longest trigger time as a reference, and sends the trigger code signal to each test device in sequence by delaying the respective time difference, namely delaying the time for sending the corresponding time difference by the clock sending device, so that the trigger code signal can reach each test device at the same time. The farther the test equipment is from the clock transmission device, the earlier the clock transmission device transmits the trigger code signal to the equipment. Assuming that a test device 1, a test device 2 and a test device 3 exist, distances between the test device 1, the test device 2 and the test device 3 and a clock sending device are sequentially increased, and triggering times between the test device 1, the test device 2 and the test device 3 and the clock sending device are respectively 1 clock cycle, 2 clock cycles and 3 clock cycles, then taking the test device 3 as a reference, the clock sending device sends a trigger code signal of the test device 3 first, sends the trigger code signal of the test device 2 after 1 clock cycle, and sends the trigger code signal of the test device 3 after 2 clock cycles, so that the trigger code signals can reach the test device 1, the test device 2 and the test device 3 at the same time. Through the steps of S3, S4, and S5, on the basis that the clocks of the test devices are in the same frequency and phase, the trigger code signals can be received at the same time, so that the test devices at different distances can be triggered at the same time, and even if the distance difference is extremely large, the signals can be received at the same time for triggering.
The embodiment provides a synchronization method for remote multi-ATE semiconductor test equipment, which utilizes 25Gbps high-speed optical fiber to transmit clock signals and trigger signals, adjusts clocks of the test equipment, realizes clock synchronization and trigger synchronization among a plurality of test equipment, and achieves the aims of high-precision remote synchronization of the clocks and synchronous trigger.
Example 2
In this embodiment, on the basis of embodiment 1, a remote multi-ATE semiconductor test equipment synchronization system is provided, and the remote equipment test method provided in embodiment 1 is systematized. The specific structure is shown in the attached figure 3 of the specification, and the scheme is as follows:
a remote equipment testing system comprises a clock sending device, a high-speed optical fiber and a plurality of testing devices, wherein the clock sending device is connected with the testing devices through the high-speed optical fiber, and high-speed optical fiber interfaces are arranged on the clock sending device and the testing devices. In the embodiment, 25Gbps high-speed optical fiber is preferably selected for transmitting clock coding signals and trigger coding signals, so that high-precision long-distance synchronous clocks and synchronous trigger targets are realized.
The clock sending device is used for sending clock code signals and trigger code signals to a plurality of test devices through the high-speed optical fiber, receiving the trigger code signals through the high-speed optical fiber and adjusting the sending time of the trigger code signals according to the time of receiving the trigger code signals.
The clock sending device is provided with an FPGA, a constant temperature crystal oscillator and a plurality of high-speed optical fiber interfaces. The constant temperature crystal oscillator provides crystal oscillation signals for the FPGA, the temperature of a quartz crystal resonator in the crystal oscillator is kept constant by using the constant temperature bath, the temperature of the quartz crystal resonator in the crystal oscillator is kept constant by using the constant temperature bath, the variation of the output frequency of the oscillator caused by the change of the ambient temperature is reduced to the minimum, and the variation of the output frequency of the oscillator caused by the change of the ambient temperature is reduced to the minimum. Multiple high-speed fiber interfaces connect 25Gbps high-speed fibers. The signal generating unit on the FPGA generates clock signals, the coding unit provided with the physical coding sublayer performs data coding on the clock signals, the clock signals are embedded into the clock coding signals with balanced 0 and 1, and the clock coding signals are sent to each test device through the high-speed optical fiber.
The signal generation unit on the FPGA generates a trigger signal, the coding unit provided with the physical coding sublayer performs data coding on the trigger signal, the trigger signal is embedded into the trigger coding signal, the trigger coding signal is sent to each test device through the high-speed optical fiber, and the trigger coding signal returned by the test device is received. The FPGA is provided with a time difference detection unit and a time adjustment unit, the time difference detection unit is used for measuring the trigger time of each test device for receiving the trigger code signal, and the time adjustment unit adjusts the sending time of the trigger code signal according to the time of each test device for receiving the trigger code signal. Assuming that a test device 1, a test device 2 and a test device 3 exist, distances between the test device 1, the test device 2 and the test device 3 and a clock sending device are sequentially increased, and it is detected by a time difference detection unit that trigger times between the test device 1, the test device 2 and the test device 3 and the clock sending device are respectively 1 clock cycle, 2 clock cycles and 3 clock cycles, a time adjustment unit controls the clock sending device to send a trigger code signal of the test device 3 first, sends a trigger code signal of the test device 2 after 1 clock cycle, and sends a trigger code signal of the test device 3 after 2 clock cycles, with the test device 3 as a reference, so that the trigger code signals can reach the test device 1, the test device 2 and the test device 3 at the same time.
The test equipment is used for receiving the clock coding signal and the trigger coding signal sent by the clock sending device, adjusting the clock of the test equipment according to the clock coding signal, and returning the received trigger coding signal to the clock sending device. The testing equipment is provided with an FPGA, an external crystal oscillator, an analog phase-locked loop, a phase adjusting unit and at least one high-speed optical fiber interface, and the external crystal oscillator, the analog phase-locked loop and the phase adjusting unit form a clock adjusting system. The analog phase-locked loop is respectively connected with the FPGA, the external crystal oscillator and the phase adjusting unit. The FPGA is provided with a clock data recovery unit, the clock data recovery unit can decode a clock coding signal by combining with a clock adjusting system to obtain a clock signal, and the obtained clock signal is basically consistent with the clock coding signal generated by a clock sending device but still has difference.
The clock adjusting unit is used for adjusting the clock of the testing equipment to be consistent with the clock of the clock sending device according to the preset analog phase-locked loop, the external crystal oscillator and the clock coding signal. When the clock recovery method is started, the analog phase-locked loop takes an external crystal oscillator as a reference clock, the external crystal oscillator sends a crystal oscillator signal to the analog phase-locked loop, the analog phase-locked loop generates a first clock according to the crystal oscillator signal and sends the first clock to the CDR, and the CDR carries out clock recovery by taking the first clock as the reference clock, generates a first recovery clock and sends the first recovery clock to the analog phase-locked loop. At the moment, the analog phase-locked loop takes the first recovered clock as a reference clock, the analog phase-locked loop and the recovered clock of the CDR form closed loop self locking, the analog phase-locked loop generates a second clock according to the first recovered clock and sends the second clock to the CDR for clock recovery, the CDR takes the second clock as the reference clock to generate a clock coding signal, the clock coding signal at the moment is basically the same as the clock coding signal generated by the clock sending device, and namely the clock of the test equipment and the clock of the clock sending device have the same frequency. The plurality of test equipment receive the clock signal sent by the same clock sending device, so that the high-precision same frequency and the basically consistent phase of the plurality of test equipment are formed. Furthermore, the phase of the clock is corrected through the phase adjusting unit, so that the clocks among different test devices not only have the same frequency, but also have the same phase. The test equipment is connected through the high-speed optical fiber, the phase between any two test equipment can be corrected by carrying the test equipment, and the IIC is used for adjusting the output phase of the analog phase-locked loop clock, so that the user clock output by the analog phase-locked loop and the clock transmitted by the clock transmitting unit are in the same frequency and phase. The external high-precision oscilloscope is used for displaying the clock phase of the test equipment in real time, and the phase adjusting unit is communicated with the analog phase-locked loop through the I2C to adjust the analog phase-locked loop step by step with preset precision until the clock phase of the test equipment is consistent with the clock phase of the clock sending device. In this embodiment, the preset precision is 2ps, that is, the phase adjustment unit gradually adjusts the analog pll in units of 2ps until the clock phases between the testing devices are the same, and the adjustment precision can be controlled within at least 10ps, which completely meets the precision required by the testing of high-end devices.
This embodiment provides a synchronization system for long-distance multi-ATE semiconductor test equipment, which systematizes the synchronization method for long-distance equipment provided in embodiment 1 to form a specific system, and transmits a clock code signal and a trigger code signal through a 25Gbps high-speed optical fiber to achieve high-precision long-distance synchronization clock and synchronization trigger targets.
Example 3
The embodiment provides a method for testing a plurality of long-distance ATE semiconductor test devices, which is suitable for the ATE semiconductor test devices. The specific scheme is as follows:
a method for testing remote multiple ATE semiconductor test equipment, comprising clock synchronization and trigger synchronization, wherein the clock synchronization comprises:
the clock sending device sends the clock coding signal embedded with the clock signal to a plurality of test devices through the high-speed optical fiber, and each test device adjusts the clock to be consistent with the clock of the clock sending device according to the clock coding signal.
Triggering synchronization includes:
the clock sending device sends the trigger code signals embedded with the trigger signals to the plurality of test equipment through the high-speed optical fibers, and adjusts the time for sending the trigger code signals to the plurality of test equipment to receive the trigger code signals at the same time according to the time for receiving the trigger code signals returned by the test equipment.
The test method provided by the embodiment is suitable for the synchronous test problem among a plurality of ATE semiconductor test devices, and can solve the problems of clock synchronization and trigger synchronization of a plurality of ATE semiconductor test devices.
In summary, the invention provides a synchronization method, a synchronization system and a synchronization test method for remote multi-ATE semiconductor test equipment, realizes high-precision remote synchronization of clocks and synchronization of trigger targets among the test equipment, and has the characteristics of high test precision and low cost. The traditional electric signal transmission is replaced by high-speed optical fiber transmission, so that the problem of attenuation of the electric signal in the transmission process is solved, and the remote equipment test is realized. Self-locking is formed through the FPGA and the analog phase-locked loop, so that the clocks of the test equipment have the same frequency at high precision. The clock phase of the equipment is adjusted through the phase adjusting unit, and the problem of the synchronization precision of the remote equipment test in the prior art is solved. And adjusting the time for sending the signals according to the time for the trigger code signals to reach each test device, so that each test device receives the trigger code signals simultaneously to carry out trigger synchronization.
It will be understood by those skilled in the art that the modules or steps of the invention described above may be implemented by a general purpose computing device, they may be centralized on a single computing device or distributed across a network of computing devices, and optionally they may be implemented by program code executable by a computing device, such that it may be stored in a memory device and executed by a computing device, or it may be separately fabricated into various integrated circuit modules, or it may be fabricated by fabricating a plurality of modules or steps thereof into a single integrated circuit module. Thus, the present invention is not limited to any specific combination of hardware and software.
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments illustrated herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.
The above disclosure is only a few specific implementation scenarios of the present invention, however, the present invention is not limited thereto, and any variations that can be made by those skilled in the art are intended to fall within the scope of the present invention.
Claims (10)
1. A synchronization method for remote multi-ATE semiconductor test equipment is characterized by comprising the following steps:
the clock transmitting device transmits clock coding signals embedded with clock signals to a plurality of test devices through high-speed optical fibers;
the test equipment receives the clock code and recovers a clock by a signal, and the clock of the test equipment is adjusted to be consistent with the clock of the clock sending device by combining a clock adjusting system;
the clock sending device sends the trigger code signals embedded with the trigger signals to a plurality of test devices through the high-speed optical fibers;
the test equipment receives the trigger code signal and returns the trigger code signal to the clock sending device through the high-speed optical fiber;
and the clock sending device receives the trigger code signal and adjusts the time for sending the trigger code signal to the test equipment according to the time difference for receiving the trigger code signal, so that the aim that a plurality of test equipment simultaneously receive the trigger code signal is fulfilled.
2. The method of claim 1, wherein the clock adjustment system comprises an external crystal oscillator and an analog phase-locked loop;
the step of receiving the clock code and recovering a clock from a signal by the test equipment, and adjusting the clock of the test equipment to be consistent with the clock of the clock sending device by combining a clock adjusting system specifically includes:
the test equipment receives the clock coding signal;
the analog phase-locked loop generates a first clock by taking the clock of the external crystal oscillator as a reference clock and sends the first clock to the clock data recovery unit;
the clock data recovery unit takes the first clock as a reference clock, recovers the clock coding signal into a first recovered clock and sends the first recovered clock to the analog phase-locked loop;
the analog phase-locked loop uses the first recovery clock as a reference clock, generates a second clock and sends the second clock to the clock data recovery unit;
and the clock data recovery unit takes the second clock as a reference clock and adjusts the clock frequency of the test equipment to be consistent with the clock frequency of the clock sending device.
3. The method of claim 2, wherein the clock adjustment system further comprises a phase adjustment unit;
after "the clock data recovery unit adjusts the clock frequency of the test equipment to be consistent with the clock frequency of the clock transmission device with the second clock as a reference clock", the method further comprises,
and displaying the clock phase of the test equipment through an external oscilloscope, establishing communication between the phase adjusting unit and the analog phase-locked loop through I2C, and gradually adjusting the clock phase of the analog phase-locked loop with preset precision until the clock phase of the test equipment is consistent with the clock phase of the clock sending device.
4. The method according to claim 1, wherein the step of the clock sending device receiving the trigger code signal and adjusting the time for sending the trigger code signal to the test devices according to the time difference for receiving the trigger code signal so as to achieve the purpose that a plurality of test devices receive the trigger code signal simultaneously includes:
the clock sending device receives the trigger code signals sent by the test equipment, obtains the time for the clock sending device to receive the trigger code signals, and delays the time for the clock sending device to send the trigger code signals to other test equipment by taking the test equipment with the longest time for receiving the trigger code signals as a reference until the plurality of test equipment receive the trigger code signals at the same time.
5. The method according to claim 1, wherein a physical coding sublayer is arranged in the clock transmission device;
embedding the clock signal into the clock encoded signal by the physical coding sublayer;
embedding the trigger signal into the trigger code signal by the physical coding sublayer.
6. A method according to claim 3, characterized in that the preset precision is 2ps and/or the bandwidth of the high speed fiber is 25 Gbps.
7. A remote multi-ATE semiconductor test equipment synchronization system adapted for use in the remote multi-ATE semiconductor test equipment synchronization method of any one of claims 1-6, comprising a clock transmission device, a high-speed optical fiber and a plurality of test equipment, wherein the clock transmission device is connected to the plurality of test equipment through the high-speed optical fiber;
the clock sending device is used for sending clock coding signals and trigger coding signals to a plurality of test devices through a high-speed optical fiber, receiving the trigger coding signals through the high-speed optical fiber and adjusting the sending time of the trigger coding signals according to the time for receiving the trigger coding signals;
the test equipment is used for receiving the clock coding signal and the trigger coding signal sent by the clock sending device, adjusting a clock according to the clock coding signal, and returning the received trigger coding signal to the clock sending device.
8. The system of claim 7, wherein the clock transmitting means comprises:
a signal generation unit: for generating a clock signal and a trigger signal;
an encoding unit: the physical coding sublayer is arranged and used for embedding a clock signal into a clock coding signal, embedding a trigger signal into a trigger coding signal and sending the clock coding signal and the trigger coding signal to the test equipment through the high-speed optical fiber;
a time adjustment unit: and the device is used for receiving the trigger code signal and adjusting the sending time of the trigger code signal according to the time for receiving the trigger code signal until the plurality of test equipment simultaneously receive the trigger code signal.
9. The system of claim 7, wherein the test device has disposed thereon:
a clock data recovery unit: for receiving and decoding the clock encoded signal;
the clock adjusting system comprises: the clock sending device is used for sending a clock of the test equipment to the external crystal oscillator; the phase-locked loop circuit comprises an analog phase-locked loop, an external crystal oscillator and a phase adjusting unit;
a phase adjustment unit: the device is used for establishing communication with the analog phase-locked loop through I2C and gradually adjusting the analog phase-locked loop with preset precision until the clock phase of the test equipment is consistent with the clock phase of the clock sending device.
10. A remote multi-ATE semiconductor test equipment testing method comprises clock synchronization and trigger synchronization, and is characterized in that the clock synchronization comprises the following steps:
the clock sending device sends a clock coding signal embedded with a clock signal to a plurality of test devices through a high-speed optical fiber, and each test device adjusts the clock to be consistent with the clock of the clock sending device according to the clock coding signal;
triggering synchronization includes:
the clock sending device sends the trigger code signals embedded with the trigger signals to a plurality of test devices through the high-speed optical fibers, and adjusts the time for sending the trigger code signals according to the time for receiving the trigger code signals returned by the test devices until the plurality of test devices receive the trigger code signals at the same time.
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