CN104917582A - High-precision clock distribution and phase automatic compensation system and phase adjusting method thereof - Google Patents
High-precision clock distribution and phase automatic compensation system and phase adjusting method thereof Download PDFInfo
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Abstract
The invention discloses a high-precision clock distribution and phase automatic compensation system and a phase adjusting method thereof. The system comprises a clock distribution module (master) and a plurality of front-end electronics nodes (slave). The master distributes clocks to the multiple slaves by using fibers. The master sends the clocks to the slaves by the fibers; after receiving the clocks, the slaves return the clocks to the master again; the master carries out dynamic measurement on the sum of round-trip time of the clocks to obtain uplink and downlink delay time of the clocks and sends measurement results to the slaves; and according to the measurement results, the slaves carries out dynamic phase adjustment on the received clocks, so that phase synchronization of the slaves and the master can be maintained. With the system and method, the phase synchronization precision is improved and a phase adjustment error caused by the temperature change can be reduced.
Description
Technical field
The present invention relates to high precision clock distribution simultaneous techniques field, particularly relate to the distribution of a kind of high precision clock based on multinode under the large-scale dimension (~ 1km) of field programmable gate array (Field-programmable-gate-array, FPGA) and phase automatic compensating system and phase regulation method thereof.
Background technology
Clock phase synchronization technology is widely used in network communication field at first, such as long-range charging, and its synchronization accuracy can reach hundred milliseconds of magnitudes; IP network packet delay is monitored, and its synchronization accuracy is better than hundred microseconds; LTE-TDD, WiMax-TDD, synchronization accuracy reaches submicrosecond magnitude.The traditional synchronous method in the communications field is based on satellite navigation systems such as global positioning systems (Global Positioning System, GPS), can reach the synchronous accuracy of few tens of nano-seconds.The accurate clock synchronization protocol (PTP, Precision Time Protocol, IEEE1588) of network precise clock synchronization committee proposition in 2002 can make clock phase synchronization precision reach subnanosecond level.
Compared with network communication field, the performance requirement of large-scale Physical Experiment to clock phase synchronization is harsher.A kind of conventional clock distribution method of Physical Experiment adopts clock chain circuit distribution clock, the RF signal that the such as clock system of Beijing Spectrometer (BESIII) flight time detector (TOF) will speed up device introduces VME cabinet by the steady phase optical fiber of 80m, the method shortcoming is that clock chain circuit is expensive, spend higher, and often design according to varying environment and demand, versatility is not strong.
Another kind of conventional clock synchronizing method uses GPS to carry out clock distribution, and Auger experiment uses gps receiver to carry out frequency and time synchronized, demarcates the droop of gps receiver in advance, at 3000km in laboratory
21600 water Cerenkov detectors on gps receiver is installed, the accurate precision of its time synchronized is better than 20ns, and the shortcoming of the method is that GPS receiving system is expensive, and receiver and cable are responsive to variations in temperature, easily affects by temperature drift.
A kind of method is also had to adopt microwave and laser technology, high precision can be obtained, such as XFEL clock system, U.S.'s linear accelerator coherent source (Linac Coherent Light Source, LCLS) pump probe experiment etc., but these clock system costs controlled based on high-precision optical are high.
In order to take into account large-scale dimension scope, high accuracy, the factors such as price, CERN proposes White Rabbit clock phase synchronization technology on the basis of IEEE1588, White Rabbit carries out clock distribution based on optical fiber, adopt two mixing phase discriminator (the Digital Dual Mixer TimeDifference of numeral simultaneously, DDMTD) measure phase difference, the outer VCXO of sheet is used to carry out phase adjusted, precision can reach subnanosecond, but its complex structure, and the phase modulation error that minimizing variations in temperature of not taking measures causes.
In order to reach higher phase modulation precision, the present invention, on the basis of PTP, adopts symmetrical FPGAPLL to carry out phase place fine tuning, structure is simple, synchronization accuracy can reach hundred picosecond magnitudes, adopts incremental adjustments algorithm simultaneously, reduce the synchronous error that variations in temperature causes to the delay variation that temperature causes.
Summary of the invention
(1) technical problem that will solve
In view of this, the object of the present invention is to provide a kind of high precision clock based on multinode under the large-scale dimension of FPGA to distribute and phase automatic compensating system and phase regulation method thereof, to improve Phase synchronization precision, the phase modulation error that minimizing variations in temperature causes.
(2) technical scheme
For achieving the above object, the invention provides the distribution of a kind of high precision clock and phase automatic compensating system, this system comprises clock distribution module (Master) and multiple front-end electronics node (Slave), Master adopts optical fiber that clock is distributed to multiple Slave, wherein: clock is sent to Slave by optical fiber by Master, clock is transferred back to Master by optical fiber after receiving clock by Slave again, the two-way time sum of Master to clock carries out the up-downgoing time delay that kinetic measurement obtains clock, and measurement result is sent to Slave, Slave carries out dynamic phasing adjustment according to measurement result to the clock received, Slave and Master is made to keep Phase synchronization.
In such scheme, the two-way time sum of described Master to clock carries out kinetic measurement, and adopt the two mixing phase discriminator of numeral to coordinate counter to realize, wherein counter measures part complete cycle is the thick time; Exceeding part adopts the two mixing phase discriminator of numeral to measure, and be the thin time, namely both combination obtain precise time.
In such scheme, each Slave has phase place coarse adjustment unit and phase place fine tuning unit, and Slave adopts phase place coarse adjustment and phase place fine tuning to carry out dynamic phasing adjustment to the clock received.
In such scheme, described phase place coarse adjustment unit realizes based on accurate clock synchronization protocol (PreciseTiming Protocol, PTP).
In such scheme, described phase place fine tuning unit adopts field programmable gate array phase-locked loop (FPGAPLL) to realize, and will need the clock input FPGA PLL of phase modulation, delayed rear output, realizes the fine adjustment to clock.
In such scheme, described phase place fine tuning unit adopts FPGA PLL composition symmetrical structure to carry out phase adjusted, after Slave receives clock, use FPGA PLL to carry out phase adjusted and obtain system clock, this system clock before being sent to Master again through a FPGA PLL phase adjusted, the phase modulation value of two FPGA PLL phase adjusted employings is identical, keeps symmetrical.
For achieving the above object, the invention provides a kind of described high precision clock distribution and phase automatic compensating system of utilizing and carry out phase-adjusted method, wherein, the method adopts and postpones delta algorithm calculating phase adjusted value, and adopts phase place coarse adjustment and phase place fine tuning to carry out dynamic phasing adjustment to clock.
In such scheme, described employing postpones delta algorithm and calculates phase adjusted value, comprise: clock is transferred to Slave by optical fiber from Master, and then return Master from Slave, namely sum two-way time measuring clock obtains the up-downgoing time delay of clock, by the change of the increment size under research up-downgoing time delay relatively certain reference temperature, record the proportionality coefficient of the increment of up-downgoing time delay, by the dynamic measurement results of this proportionality coefficient in conjunction with round trip delay time, realize real-time high-precision phase position when not needing temperature sensing circuit and compensate.
In such scheme, described employing postpones delta algorithm and calculates phase adjusted value, specifically comprises:
In time measurement, as shown in Figure 2, T is recorded
1, T
2, T
3, T
4, wherein the moment of Master transmission synchronization frame is designated as T
1, the moment that Slave receives synchronization frame is designated as T
2, the moment that Slave sends acknowledgement frame is designated as T
3, the moment that Master receives acknowledgement frame is designated as T
4, by following formulae discovery downlink delays T
delay_downwith upstream delay T
delay_up:
T
delay_down＝T
2-T
1-T
offset
T
delay_up＝T
4-T
3+T
offset
Wherein, T
offsetfor the time difference between Slave and Master, then up-downgoing postpones and T
delay_totalfor,
T
delay_total＝T
delay_up+T
delay_down
T
delay_total＝T
4-T
3+T
2-T
1
Under isoperibol, downlink delays and upstream delay remain unchanged, if ambient temperature changes, round-trip delay are deducted the length of delay of demarcation, obtain the temperature drift of length of delay, and the drift of wherein round-trip delay temperature is up-downgoing temperature drift sum:
ΔT
delay_total＝ΔT
delay_up+ΔT
delay_down
According to optical fiber temperature drift and the research of floating based on the Slave electronics temperature of symmetrical FPGA PLL phase modulation, T
delay_up, T
delay_downthe Slave of middle optical fiber and the symmetrical FPGA PLL phase modulation of employing postpones to vary with temperature approximately linear change, then have
T
delay_down＝k
1t+k
1't+b
1
T
delay_up＝k
2t+k
2't+b
2
Wherein k
1, k
2up-downgoing for optical fiber postpones temperature drift coefficient, k
1', k
2' for electronics up-downgoing postpone temperature drift coefficient, can be obtained fom the above equation,
ΔT
delay_down＝(k
1+k
1')*Δt
ΔT
delay_up＝(k
2+k
2')*Δt
ΔT
delay_down/ΔT
delay_up＝(k
1+k
1')/(k
2+k
2')
ΔT
delay_down＝ΔT
delay_total/(1+(k
2+k
2')/(k
1+k
1'))
When the temperature is changed, Δ T
delay_totalchange also directly can be measured and obtain, downlink delays increment Delta T thereupon
delay_downcan by k
1, k
2, k
1', k
2' calculate; Under the symmetrical structure based on FPGA PLL phase modulation, k
1' and k
2' equal, meanwhile, according to research, the up-downgoing temperature drift coefficient also approximately equal of optical fiber; Now computing formula can contract, Δ T
delay_downfor Δ T
delay_totalhalf, demarcate and compensation process simplify thereupon.
In such scheme, the coarse adjustment of described employing phase place and phase place fine tuning carry out dynamic phasing adjustment to clock, comprising: phase place coarse adjustment realizes based on accurate clock synchronization protocol (Precise Timing Protocol, PTP); Phase place fine tuning adopts FPGA PLL composition symmetrical structure to carry out phase adjusted, after Slave receives clock, use FPGA PLL to carry out phase adjusted and obtain system clock, this system clock before being sent to Master again through a FPGA PLL phase adjusted, the phase modulation value of two FPGA PLL phase adjusted employings is identical, keeps symmetrical.
(3) beneficial effect
As can be seen from technique scheme, the present invention has following beneficial effect:
1, the high precision clock based on multinode under the large-scale dimension of FPGA provided by the invention distribution and phase automatic compensating system and phase regulation method thereof, optical fiber is used to carry out clock distribution, phase place coarse adjustment is carried out based on traditional PTP, and add phase place fine tuning unit, improve Phase synchronization precision.Adopt incremental adjustments algorithm simultaneously, decrease the phase modulation error that variations in temperature causes.
2, the distribution of the high precision clock based on multinode under the large-scale dimension of FPGA provided by the invention and phase automatic compensating system, formant all realizes in FPGA, and tool has the following advantages:
(1), structure is simple, and phase modulation precision is high.Formant is all inner at FPGA, does not need other clock phase modulation chips, substantially increases the integrated level of system, add stability and the reliability of circuit, and phase modulation precision is high simultaneously, can reach 15ps.
(2), use flexibly.FPGA has all multiple resource and is used for supporting other logics and interface, can flexible design as required; Optical fiber, except transfer clock, can also realize data and command transfer simultaneously.
(3), use incremental adjustments method, calculate simple, the phase modulation error that variations in temperature causes can be reduced, simultaneously can not serviceability temperature transducer, directly regulate according to delay increment.
Accompanying drawing explanation
Fig. 1 is the structural representation of high precision clock provided by the invention distribution and phase automatic compensating system;
Fig. 2 is the principle process schematic utilizing high precision clock provided by the invention distribution and phase automatic compensating system to carry out clock phase synchronization.
Fig. 3 is the structural representation of numeral pair mixing phase discriminator (Digital Dual Mixer Time Difference, DDMTD) in high precision clock provided by the invention distribution and phase automatic compensating system.
Fig. 4 is the structural representation of phase modulation phase-locked loop (Phase-locked-loop, PLL) in high precision clock provided by the invention distribution and phase automatic compensating system.
Fig. 5 is the schematic diagram of clock delay in high precision clock provided by the invention distribution and phase automatic compensating system.
Fig. 6 is the schematic diagram of clock synchronous in high precision clock provided by the invention distribution and phase automatic compensating system.
Embodiment
For making the object, technical solutions and advantages of the present invention clearly understand, below in conjunction with specific embodiment, and with reference to accompanying drawing, the present invention is described in more detail.
Principle of the present invention is: based on traditional accurate clock synchronization protocol (PTP), clock distribution module (Master) forward end electronics node (Slave) sends synchronization frame, after Slave receives synchronization frame, send acknowledgement frame to Master.Master and Slave measures and sends and time of reception, and calculates two-way time according to measured value.In PTP protocol, the measurement of time and adjustment, all adopt counter to carry out, limited precision.In order to improve precision, the present invention adopts DDMTD to coordinate counter to carry out time measurement, adopts FPGA PLL to coordinate counter to carry out Timing.In phase modulation method, adopt and postpone incremental calculation method, reduce temperature and float the phase modulation error caused.
The distribution of the high precision clock based on (~ 1km) multinode under the large-scale dimension of FPGA that the present invention proposes and phase automatic compensating system, comprise clock distribution module (Master) and multiple front-end electronics node (Slave), clock is distributed to multiple Slave by Master, in order to ensure signal quality, adopt optical fiber to carry out clock distribution, generally adopt long optical fibers.Wherein: clock is sent to Slave (descending) by optical fiber by Master, by optical fiber, clock is transferred back to Master (up) again after Slave receives clock, the two-way time sum of Master to clock carries out the up-downgoing time delay that kinetic measurement obtains clock, and measurement result is sent to Slave, Slave carries out dynamic phasing adjustment according to measurement result to the clock received, and makes Slave and Master keep Phase synchronization.
Wherein, the two-way time sum of Master to clock carries out kinetic measurement, and adopt the two mixing phase discriminator of numeral to coordinate counter to realize, wherein counter measures part complete cycle is the thick time; Exceeding part adopts the two mixing phase discriminator of numeral to measure, and be the thin time, namely both combination obtain precise time.
Each Slave has phase place coarse adjustment unit and phase place fine tuning unit, and Slave adopts phase place coarse adjustment and phase place fine tuning to carry out dynamic phasing adjustment to the clock received.Described phase place coarse adjustment unit realizes based on accurate clock synchronization protocol (Precise Timing Protocol, PTP).On this basis, the present invention additionally uses phase place fine tuning unit, improves phase modulation precision further.Described phase place fine tuning unit adopts field programmable gate array phase-locked loop (FPGA PLL) to realize, to need the clock input FPGA PLL of phase modulation, delayed rear output, realizes the fine adjustment to clock, PLL phase delay can regulate arbitrarily, and precision can reach 15ps.Specifically, phase place fine tuning unit adopts FPGA PLL composition symmetrical structure to carry out phase adjusted, ensures symmetry, simplifies electronics structure; After Slave receives clock, use FPGA PLL to carry out phase adjusted and obtain system clock, this system clock is again through a FPGA PLL phase adjusted before being sent to Master, and the phase modulation value of two FPGA PLL phase adjusted employings is identical, keeps symmetrical.
Further, present invention also offers a kind of described high precision clock distribution and phase automatic compensating system of utilizing and carry out phase-adjusted method, the method adopts and postpones delta algorithm calculating phase adjusted value, and adopts phase place coarse adjustment and phase place fine tuning to carry out dynamic phasing adjustment to clock.
Wherein, adopt and postpone delta algorithm calculating phase adjusted value, comprise: clock is transferred to Slave (descending) by optical fiber from Master, and then return Master (up) from Slave, namely sum two-way time measuring clock obtains the up-downgoing time delay of clock.In conventional methods where (as White Rabbit scheme), studying by postponing proportionate relationship to optical fiber up-downgoing, will distribute by a fixed proportion coefficient two-way time, but when the temperature is changed, this proportionality coefficient changes thereupon, therefore phase modulation deterioration in accuracy in varying temperature environment; In further studying, propose the real-time measures ambient temperature of serviceability temperature transducer, cooperation look-up table revises the phase modulation error that variations in temperature is brought, and its shortcoming is method complex structure.The present invention's technology used is based on delay method of addition, by the change of the increment size under research up-downgoing time delay relatively certain reference temperature, record the proportionality coefficient of the increment of up-downgoing time delay, by the dynamic measurement results of this proportionality coefficient in conjunction with round trip delay time, realize real-time high-precision phase position to compensate when not needing temperature sensing circuit, thus reduce the complexity of system.
Adopt phase place coarse adjustment and phase place fine tuning to carry out dynamic phasing adjustment to clock, comprising: phase place coarse adjustment realizes based on accurate clock synchronization protocol (Precise Timing Protocol, PTP); Phase place fine tuning adopts FPGA PLL composition symmetrical structure to carry out phase adjusted, after Slave receives clock, use FPGA PLL to carry out phase adjusted and obtain system clock, this system clock before being sent to Master again through a FPGA PLL phase adjusted, the phase modulation value of two FPGA PLL phase adjusted employings is identical, keeps symmetrical.
In this enforcement, Slave holds the field programmable device selected to be the low-power consumption of Xilinx company, the XC7A200T-1FFG1156 of low-cost FPGA Artix-7 series, Master end uses the XC6VLX195T-1FFG1156 of Xilinx company Virtex-6 series.Software environment is ISE.Master and Slave is all authenticated on the FPGA of Xilinx, and FPGA is field programmable logic device, and FPGA has complete development sequence and flow process, and producer provides complete service.
Apply above-mentioned based on the high precision clock under the large-scale dimension of FPGA synchronous and phase automatic compensating method mainly contain following link:
(1), data clock recovers
Application example of the present invention adopts FPGA GTX/GTP to carry out data clock recovery.GTX/GTP is Xilinx FPGA height number serial data transceiver IP kernel.In the Virtex-6FPGA of Master end, use GTX, in the Artix-7FPGA of Slave end, use GTP.The two function is substantially identical, parallel data can be converted into high-speed serial data and send, the serial data of reception is converted into parallel data simultaneously, and therefrom recover clock.Data clock recovery process is as follows: 8 bit parallel data are transferred to GTX by Master, and speed is that 125MHz, GTX carry out 8B10B coding to it, parallel-serial conversion, and simultaneously by tranmitting data register and data fusion, the serial data rate after fusion is 1.25Gb/s.The serial data module converter that is photoelectrically converted is light signal, through Optical Fiber Transmission to Slave.Light signal is converted into the signal of telecommunication by the photoelectric conversion module of Slave again, and carries out serioparallel exchange by GTP unit, therefrom recovers data and clock, then carries out 8B10B decoding, finally obtains data and the clock of Master transmission.Slave also adopts same way that data clock is sent to Master.When powering at every turn, the delay that GTX and GTP receives data and clock can change, and can use the bitslide function of GTX/GTP, read its delay variation value from GTX/GTP, demarcates up-downgoing and postpones.
(2), thick time measurement
Based on traditional accurate clock synchronization protocol (Precise Timing Protocol, PTP), thick time measurement adopts synchronous binary counter to carry out.In Master and Slave, all have a coincidence counter using system clock to drive, in the present embodiment, system clock frequency is 125MHz, and each cycle, this Counter Value added 1, is used for recording current time.When Master and Slave sends or receive syn ack frame, the pulse of generation time stamp, by this pulse latching accumulator value, namely obtains the thick time, precision 8ns.In order to prevent metastable state phenomenon, simultaneously in rising edge and the trailing edge latching accumulator value of clock, a value wherein must be had to be accurately, by comparing the phase place between timestamp pulse and rising edge clock, if the two is close, then there is not metastable state in trailing edge latched value, adopts trailing edge latched value, otherwise adopt rising edge latched value.
(3), fine measurement
As shown in Figure 2, Master sends synchronization frame, and the pulse of generation time stamp, its time is designated as T
1, in like manner its time receiving acknowledgement frame is T
4, the time that Slave receives synchronization frame is T
2, the time sending acknowledgement frame is T
3.According to phase modulation method, T
1, T
2, T
3, T
4certainty of measurement determine synchronization accuracy.In PTP protocol, when timestamp pulse arrives, employing counter is measured, precision is only a clock cycle, for improving precision, the present invention adopts the two mixing phase discriminator (DDMTD) of numeral to coordinate counter to carry out time measurement, wherein counter measures part complete cycle, precision 8ns is the thick time; Exceeding part adopts DDMTD to measure, and be the thin time, both combine, and can obtain correct time.
T
1, T
2, T
3, T
4in, T
1for Master sends the time of synchronization frame, when Master sends synchronization frame, its timestamp pulse and system clock synchronization, therefore its thin time is 0, does not need to adopt DDMTD to measure.T
2for Slave receives time of synchronization frame, when Slave receives synchronization frame, its timestamp pulse and recovered clock synchronous, and counter to be Slave system clock drive, then the thin time is the phase difference between system clock and recovered clock.According to Fig. 2, Slave recovered clock after PLL postpones to system clock, namely the thin time is PLL length of delay, can directly read.In like manner, Slave sends acknowledgement frame time T
3, the thin time is the phase difference between tranmitting data register and system clock, is a clock cycle to deduct PLL length of delay.T
4for Master receives the acknowledgement frame time, its timestamp pulse is synchronous with Master recovered clock, and counter is the driving of Master system clock, therefore the thin time is the phase difference between Master recovered clock and system clock, and this phase difference adopts DDMTD to measure.
As shown in Figure 3, Master recovered clock and system clock are inputted DDMTD, then adopt a frequency to sample to it close to the reference clock of system clock.In the present embodiment, reference clock frequency is 1279/1280 of system clock, and sampling output is equivalent to carry out cycle amplification in tested, and multiplication factor A is relevant with the frequency degree of closeness of measured clock with reference clock, is 1280 times herein.
A＝T
clk/(T
clk_fx-T
clk)
After the cycle amplifies, the phase difference between recovered clock and system clock also amplifies thereupon, and when the rising edge of system clock arrives, counter starts counting, and when the rising edge of clock arrives when recovered, counter stops counting.The value M of counter reflects phase difference Ф.
Φ＝Μ*Τ
clk/A
The theoretical certainty of measurement of DDMTD is 12.5ps.But in order to reduce the impact that clock jitter causes, 60,000 repetitive measurement being carried out to phase difference and averages again, effectively can improve certainty of measurement.Compared to the TDC based on FPGA carry chain that certainty of measurement is higher, DDMTD is saving resource and cost more, and logic is simple and convenient.
(5), FPGA PLL phase modulation
As shown in Figure 4, Xilinx FPGA inside is integrated with PLL, has dynamic phase modulation function, can adjust the phase place of input clock, then export.Slave receives serial data and after recovering clock, produces system clock through PLL phase modulation, and system clock, through the PLL of another symmetry, produces tranmitting data register, returns Master through optical fiber.FPGA PLL phase modulation precision is for can reach 15ps, and phase modulation scope is 0-360 degree.During PLL work, PSCLK input clock signal, is used for synchronous control signal, postpones, then PSINCDEC signal is put 1, PSEN signal is put 1 simultaneously, keeps a clock cycle to increase output clock, and PLL output clock delay increase step-length, is about 15ps.Otherwise PSINCDEC zero setting, PSEN signal puts 1, then PLL output clock postpones minimizing step-length.Repeat above operation, namely adjustable clock is to desired phase value.Compare and use the outside VCXO of logic control to carry out phase modulation, be characterized in that structure is simple, easy to use, precision is high.Meanwhile, respectively add a PLL phase modulation in downlink path and up path, keep up-downgoing way symmetric, when slave temperature change, the temperature drift that up-downgoing can be made to postpone is consistent, and reduces phase modulation error.
(6), incremental adjustments method
As shown in Figure 6, when not carrying out time synchronized, Master and Slave life period difference T
offset, to the time difference 0 will be adjusted to, first need adjustment Slave to hold Counter Value, secondly also will adjust the phase place of Slave system clock.Slave system clock is obtained through Optical Fiber Transmission by Master clock, and its phase place is postponed to determine by optical fiber and electronics.
As shown in Figure 5, clock and data are transferred to Slave by optical fiber from Master, need the delay through electronics and optical fiber, are referred to as downlink delays T
delay_down, clock is returned Master by Slave, needs equally to postpone through optical fiber and electronics, is referred to as upstream delay T
delay_up, upstream delay and downlink delays sum are round-trip delay T
delay_total.Electronics postpones to be divided into Master and Slave two parts, and in actual use, residing for Slave and optical fiber, the temperature of environment very likely changes, and cause up-downgoing to postpone to produce temperature drift, further, round-trip delay also changes with temperature drift.According to the research to optical fiber temperature drift and the drift of Slave electronics temperature, the present invention adopts to increase and adjusts control method to carry out phase place dynamic adjustments.Under a certain ambient temperature, calibrate downlink delays, and regulate, when the temperature is changed, calculate it and postpone increment, adopt incremental adjustments method, carry out phase modulation.As shown in Figure 2, in time measurement, record T
1, T
2, T
3, T
4, can by following formulae discovery downlink delays T
delay_downwith upstream delay T
delay_up.
T
delay_down＝T
2-T
1-T
offset
T
delay_up＝T
4-T
3+T
offset
Wherein, T
offsetfor the time difference between Slave and Master, then up-downgoing postpones and T
delay_totalfor,
T
delay_total＝T
delay_up+T
delay_down
T
delay_total＝T
4-T
3+T
2-T
1
Under isoperibol, downlink delays and upstream delay remain unchanged, if ambient temperature changes, round-trip delay are deducted the length of delay of demarcation, obtain the temperature drift of length of delay, and the drift of wherein round-trip delay temperature is up-downgoing temperature drift sum.
ΔT
delay_total＝ΔT
delay_up+ΔT
delay_down
According to optical fiber temperature drift and the research of floating based on the Slave electronics temperature of symmetrical FPGA PLL phase modulation, T
delay_up, T
delay_downthe Slave of middle optical fiber and the symmetrical FPGA PLL phase modulation of employing postpones to vary with temperature approximately linear change, then have
T
delay_down＝k
1t+k
1't+b
1
T
delay_up＝k
2t+k
2't+b
2
Wherein k
1, k
2up-downgoing for optical fiber postpones temperature drift coefficient, k
1', k
2' for electronics up-downgoing postpone temperature drift coefficient, can be obtained fom the above equation,
ΔT
delay_down＝(k
1+k
1')*Δt
ΔT
delay_up＝(k
2+k
2')*Δt
ΔT
delay_down/ΔT
delay_up＝(k
1+k
1')/(k
2+k
2')
ΔT
delay_down＝ΔT
delay_total/(1+(k
2+k
2')/(k
1+k
1'))
When the temperature is changed, Δ T
delay_totalchange also can directly obtain by survey calculation thereupon, then downlink delays increment Delta T
delay_downcan by k
1, k
2, k
1', k
2' calculate.In this enforcement, Slave phase modulation module adopts symmetrical structure, k
1' and k
2' approximately equal, meanwhile, the fiber lengths that this enforcement adopts is 1km, and model is G625D, and the temperature drift approximately linear that its up-downgoing postpones, temperature drift coefficient is respectively 146.6ps/ DEG C, 146.4ps/ DEG C, approximately equal.Now, formula can contract, Δ T
delay_downfor Δ T
delay_totalhalf, demarcate and compensation process simplify thereupon.
This method is also applicable to above-mentioned four unequal situations of coefficient.
Above-described specific embodiment; object of the present invention, technical scheme and beneficial effect are further described; be understood that; the foregoing is only specific embodiments of the invention; be not limited to the present invention; within the spirit and principles in the present invention all, any amendment made, equivalent replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (10)
1. high precision clock distribution and a phase automatic compensating system, this system comprises clock distribution module Master and multiple front-end electronics node Slave, Master adopt optical fiber that clock is distributed to multiple Slave, wherein:
Clock is sent to Slave by optical fiber by Master, clock is transferred back to Master by optical fiber after receiving clock by Slave again, the two-way time sum of Master to clock carries out the up-downgoing time delay that kinetic measurement obtains clock, and measurement result is sent to Slave, Slave carries out dynamic phasing adjustment according to measurement result to the clock received, and makes Slave and Master keep Phase synchronization.
2. high precision clock distribution according to claim 1 and phase automatic compensating system, wherein, the two-way time sum of described Master to clock carries out kinetic measurement, adopts the two mixing phase discriminator of numeral to coordinate counter to realize, wherein counter measures part complete cycle is the thick time; Exceeding part adopts the two mixing phase discriminator of numeral to measure, and be the thin time, namely both combination obtain precise time.
3. high precision clock distribution according to claim 1 and phase automatic compensating system, wherein, each Slave has phase place coarse adjustment unit and phase place fine tuning unit, and Slave adopts phase place coarse adjustment and phase place fine tuning to carry out dynamic phasing adjustment to the clock received.
4. high precision clock distribution according to claim 3 and phase automatic compensating system, wherein, described phase place coarse adjustment unit realizes based on accurate clock synchronization protocol.
5. high precision clock distribution according to claim 3 and phase automatic compensating system, wherein, described phase place fine tuning unit adopts field programmable gate array phase-locked loop FPGA PLL to realize, and will need the clock input FPGA PLL of phase modulation, delayed rear output, realizes the fine adjustment to clock.
6. high precision clock distribution according to claim 3 and phase automatic compensating system, wherein, described phase place fine tuning unit adopts FPGA PLL composition symmetrical structure to carry out phase adjusted, after Slave receives clock, use FPGA PLL to carry out phase adjusted and obtain system clock, this system clock is again through a FPGA PLL phase adjusted before being sent to Master, and the phase modulation value of two FPGA PLL phase adjusted employings is identical, keeps symmetrical.
7. one kind utilizes the distribution of the high precision clock according to any one of claim 1 to 6 and phase automatic compensating system to carry out phase-adjusted method, wherein, the method adopts and postpones delta algorithm calculating phase adjusted value, and adopts phase place coarse adjustment and phase place fine tuning to carry out dynamic phasing adjustment to clock.
8. phase-adjusted method according to claim 7, wherein, described employing postpones delta algorithm and calculates phase adjusted value, comprising:
Clock is transferred to Slave by optical fiber from Master, and then return Master from Slave, namely sum two-way time measuring clock obtains the up-downgoing time delay of clock, by the change of the increment size under research up-downgoing time delay relatively certain reference temperature, record the proportionality coefficient of the increment of up-downgoing time delay, by the dynamic measurement results of this proportionality coefficient in conjunction with round trip delay time, realize real-time high-precision phase position when not needing temperature sensing circuit and compensate.
9. phase-adjusted method according to claim 8, wherein, described employing postpones delta algorithm and calculates phase adjusted value, specifically comprises:
In time measurement, record T
1, T
2, T
3, T
4, wherein the moment of Master transmission synchronization frame is designated as T
1, the moment that Slave receives synchronization frame is designated as T
2, the moment that Slave sends acknowledgement frame is designated as T
3, the moment that Master receives acknowledgement frame is designated as T
4, by following formulae discovery downlink delays T
delay_downwith upstream delay T
delay_up:
T
delay_down＝T
2-T
1-T
offset
T
delay_up＝T
4-T
3+T
offset
Wherein, T
offsetfor the time difference between Slave and Master, then up-downgoing postpones and T
delay_totalfor,
T
delay_total＝T
delay_up+T
delay_down
T
delay_total＝T
4-T
3+T
2-T
1
Under isoperibol, downlink delays and upstream delay remain unchanged, if ambient temperature changes, round-trip delay are deducted the length of delay of demarcation, obtain the temperature drift of length of delay, and the drift of wherein round-trip delay temperature is up-downgoing temperature drift sum:
ΔT
delay_total＝ΔT
delay_up+ΔT
delay_down
According to optical fiber temperature drift and the research of floating based on the Slave electronics temperature of symmetrical FPGA PLL phase modulation, T
delay_up, T
delay_downthe Slave of middle optical fiber and the symmetrical FPGA PLL phase modulation of employing postpones to vary with temperature approximately linear change, then have
T
delay_down＝k
1t+k
1't+b
1
T
delay_up＝k
2t+k
2't+b
2
Wherein k
1, k
2up-downgoing for optical fiber postpones temperature drift coefficient, k
1', k
2' for electronics up-downgoing postpone temperature drift coefficient, can be obtained fom the above equation,
ΔT
delay_down＝(k
1+k
1')*Δt
ΔT
delay_up＝(k
2+k
2')*Δt
ΔT
delay_down/ΔT
delay_up＝(k
1+k
1')/(k
2+k
2')
ΔT
delay_down＝ΔT
delay_total/(1+(k
2+k
2')/(k
1+k
1'))
When the temperature is changed, Δ T
delay_totalchange also directly can be measured and obtain, downlink delays increment Delta T thereupon
delay_downcan by k
1, k
2, k
1', k
2' calculate; Under the symmetrical structure based on FPGA PLL phase modulation, k
1' and k
2' equal, meanwhile, according to research, the up-downgoing temperature drift coefficient also approximately equal of optical fiber; Now computing formula can contract, Δ T
delay_downfor Δ T
delay_totalhalf, demarcate and compensation process simplify thereupon.
10. phase-adjusted method according to claim 7, wherein, the coarse adjustment of described employing phase place and phase place fine tuning carry out dynamic phasing adjustment to clock, comprising:
Phase place coarse adjustment realizes based on accurate clock synchronization protocol;
Phase place fine tuning adopts FPGA PLL composition symmetrical structure to carry out phase adjusted, after Slave receives clock, use FPGA PLL to carry out phase adjusted and obtain system clock, this system clock before being sent to Master again through a FPGA PLL phase adjusted, the phase modulation value of two FPGA PLL phase adjusted employings is identical, keeps symmetrical.
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