CN108111246A - A kind of method of the distributed parallel computing environment synchronised clock transmission based on high speed serialization link - Google Patents
A kind of method of the distributed parallel computing environment synchronised clock transmission based on high speed serialization link Download PDFInfo
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- CN108111246A CN108111246A CN201711335924.7A CN201711335924A CN108111246A CN 108111246 A CN108111246 A CN 108111246A CN 201711335924 A CN201711335924 A CN 201711335924A CN 108111246 A CN108111246 A CN 108111246A
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- link
- delay
- synchronised clock
- clock
- host node
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
Abstract
The invention discloses it is a kind of based on high speed serialization link distributed parallel computing environment synchronised clock transmission method, including：Host node is measured to the link delay of each child node；The link delay that the host node is obtained based on measurement configures the clock delay value of each child node；The host node sends synchronised clock；Each child node is recovered to obtain the synchronised clock that the host node is sent from link；Each child node will recover obtained synchronised clock, postpone the synchronised clock as local after the clock delay value received.This method on the hardware foundation of differential link, can realize transmission and the local recovery of synchronised clock, ensure the stability of synchronised clock transmission, and can reduce system hardware complexity, and then reduce hardware spending and hardware maintenance cost.
Description
Technical field
The present invention relates to fields of communication technology, and in particular to a kind of distributed parallel computing environment based on high speed serialization link is same
The method for walking clock transfer.
Background technology
Traditional data collection and transfering system, it is total using 100 m ethernet or other industry spots between each child node
Line is attached.In order to ensure that all child nodes can start simultaneously at sampling, system needs to safeguard a synchronised clock.The synchronization
Clock is generally safeguarded using dedicated hardware circuit.To ensure synchronism, the host node of synchronised clock is sent to each height
The line delay of node will ensure basically identical.When there are many systematic sampling passage, it is necessary to safeguard substantial amounts of synchronised clock transmission
Link, hardware spending are very big.
The content of the invention
The object of the present invention is to provide a kind of distributed parallel computing environment synchronised clock transmission based on high speed serialization link
Method.This method on the hardware foundation of differential link, can realize transmission and the local recovery of synchronised clock, ensure synchronous
The stability of clock transfer, and system hardware complexity can be reduced, and then reduce hardware spending and hardware maintenance cost.
To achieve the above object, technical solution provided by the invention is as follows：
A kind of method of the distributed parallel computing environment synchronised clock transmission based on high speed serialization link, comprises the following steps：
Host node is measured to the link delay of each child node；
The link delay that the host node is obtained based on measurement configures the clock delay value of each child node；
The host node sends synchronised clock；
Each child node is recovered to obtain the synchronised clock that the host node is sent from link；
Each child node will recover obtained synchronised clock, postpone the synchronization as local after the clock delay value received
Clock.
On the basis of above-mentioned technical proposal, in distributed parallel computing environment, it is standby that child node can synchronize clock
Part, when link channel communication quality declines, it is still able to the normal working hours that system is made to remain certain.
Compared with prior art, the device have the advantages that being：
The method of distributed parallel computing environment synchronised clock transmission provided by the invention based on high speed serialization link, Neng Gou
Transmission and the local recovery of synchronised clock are realized in differential link, while system stability is kept, reduces and synchronously adopts
Collect the hardware spending of Transmission system, have broad application prospects.
Description of the drawings
Fig. 1 is the method for the transmission of the distributed parallel computing environment synchronised clock based on high speed serialization link that embodiment provides
Flow diagram；
Fig. 2 is the measurement process schematic diagram of the link delay between the host node that embodiment provides and child node；
Fig. 3 is the structure diagram of the delay measurements sequence that embodiment provides and feedback sequence；
Fig. 4 is the structure diagram for the length of delay configuration sequence that embodiment provides；
Fig. 5 is the realization method schematic diagram that the host node that embodiment provides sends synchronised clock；
Fig. 6 is the schematic diagram localized after the synchronised clock for the child node that embodiment provides recovers；
Fig. 7 is the module that embodiment provides the differential link physical layer for being host node FPGA and child node FPGA realizations
Figure.
Specific embodiment
To make the objectives, technical solutions, and advantages of the present invention more comprehensible, this hair with reference to the accompanying drawings and embodiments
It is bright to be described in further detail.It should be appreciated that the specific embodiments described herein are only used to explain the present invention, and
Do not limit protection scope of the present invention.
The present embodiment is related to the data collecting system based on high speed serialization link, and in particular to a kind of realization the type system
The method that synchronised clock and data are transmitted in serial link simultaneously.
Fig. 1 is the method for the distributed parallel computing environment synchronised clock transmission provided in this embodiment based on high speed serialization link
Flow diagram.Referring to Fig. 1, synchronised clock transmission method provided in this embodiment comprises the following steps：
S101, the link delay of measurement host node to each child node.
In this step, specifically, mainly by forward delay interval measuring command, host node FPGA and child node FPGA are utilized
Between send delay measurements order and receive feedback command time difference, calculate the transmission delay time, realize link delay
Measurement.
Fig. 2 is the measurement process schematic diagram of the link delay between the host node that embodiment provides and child node.Fig. 3 is
The delay measurements sequence and the structure diagram of feedback sequence that embodiment provides.Referring to Fig. 2, Fig. 3, host node and child node it
Between be attached using very high speed serial differential link, physical layer use 8b/10b coding modes, due to coding redundancy, can will encode
10b characters afterwards are divided into data character and control character.All 8b characters are all encoded using two kinds of 10b of CRD+ and CRD-, with
Ensure DC balance during transmission.The present embodiment is using control character K1 as the feature frame head of delay measurements sequence, delay measurements
Sequence and feedback sequence include two control character K1 and child node address Addr (H), Addr (L).
Measurement for a link delay, host node will send a delay measurements sequence, while with local high frequency
Clock opens counter, and child node, which receives, counter at once after Time delay measurement sequence send a feedback sequence, content and delay measurements
Sequence is consistent, is identified for host node, after host node receives feedback sequence, closes counter, obtains child node at this time
Link delay.
S102, the link delay that the host node is obtained based on measurement, the clock delay value of configuration each child node.
In the present embodiment, specifically, the host node after the link delay value of all child nodes, leads in link has been measured
The mode for sending length of delay configuration sequence is crossed, configures the clock delay value of each child node, each child node receives the length of delay and matches somebody with somebody
Local address is compared after putting sequence, the clock delay value in length of delay configuration sequence is taken out if identical, and local clock is set
Length of delay.
Fig. 4 is the structure diagram for the length of delay configuration sequence that embodiment provides, provided in this embodiment to prolong referring to Fig. 4
Value configuration sequence is target child node address as feature frame head, after 2 control character K2 using control character K2 late, Zhi Houwei
The length of delay (Delay) of 8 characters, a high position is preceding.
S103, the host node send synchronised clock.
Specifically, the host node transmits specific control code into data in link layer stream to realize the biography of synchronised clock
It is defeated.Fig. 5 is the realization method schematic diagram that the host node that embodiment provides sends synchronised clock.As shown in figure 5, by control character K3
As synchronised clock identity code.According to the frequency of synchronised clock, host node is in the character stream of data link layer according to fixed
Control character K3 is inserted into realize the transmission of synchronised clock in interval.
S104, each child node are recovered to obtain the synchronised clock that the host node is sent from link.
Specifically, the synchronised clock control code in each child node monitoring data link layer, and it is synchronous from the clock
The synchronised clock that the host node is sent is recovered in control code.
Character in child node monitoring data link represents that synchronised clock transmission starts if control character K3 is detected,
A rising edge or trailing edge that a control character K3 represents synchronised clock are often received afterwards.Child node is same according to receiving
The state for walking the clock last time is overturn into row clock, to recover synchronised clock.
S105, each child node will recover obtained synchronised clock, be used as locally after postponing the clock delay value received
Synchronised clock.
Fig. 6 is the schematic diagram localized after the synchronised clock for the child node that embodiment provides recovers.As shown in fig. 6, when section
Point recovers synchronised clock, is started counting up at once with local clock, once the clock delay value M phases obtained in count value and S102
Meanwhile start to generate the synchronised clock after delay, which will be used as local real synchronised clock.
Fig. 7 is the module of the differential link physical layer provided in this embodiment for being host node FPGA and child node FPGA realizations
Figure, as shown in fig. 7, differential link physical layer includes：
As described in Fig. 7 (a), transmitting terminal：
Tx_buffer caches the data from data link layer.
It sends control logic and realizes data, synchronised clock, delay measurements and the switching of configuration.
Scrambling module generates pseudo-random sequence and send data flow by a linear shift register carries out exclusive or reduction
The EMI noise of data flow.
8b/10b modular converters realize the conversion of 8b to 10b.
As described in Fig. 7 (b), receiving terminal：
10b/8b modular converters realize the conversion of 10b to 8b.
It goes to disturb module and passes through a linear shift register synchronous with transmitting terminal and realize descrambling operation.
Control logic is received, realizes the operations such as control code in length of delay configuration, removal data character stream.
Rx_buffer cachings are from the data for receiving control logic.
The transmission of synchronised clock can be realized in the distributed parallel computing environment based on high speed serialization link using this method
And the local recovery of child node, while system stability is kept, reduce the hardware spending of synchronous acquisition Transmission system.By
In the addition of programmable logic so that hardware configuration is simplified, and is expanded beneficial to the system under complex application context and function increases
By force.
Technical scheme and advantageous effect is described in detail in above-described specific embodiment, Ying Li
Solution is the foregoing is merely presently most preferred embodiment of the invention, is not intended to limit the invention, all principle models in the present invention
Interior done any modification, supplementary, and equivalent replacement etc. are enclosed, should all be included in the protection scope of the present invention.
Claims (6)
1. a kind of method of the distributed parallel computing environment synchronised clock transmission based on high speed serialization link, comprises the following steps：
Host node is measured to the link delay of each child node；
The link delay that the host node is obtained based on measurement configures the clock delay value of each child node；
The host node sends synchronised clock；
Each child node is recovered to obtain the synchronised clock that the host node is sent from link；
Each child node will recover obtained synchronised clock, when postponing after the clock delay value received the synchronization as local
Clock.
2. the method for the distributed parallel computing environment synchronised clock transmission based on high speed serialization link as described in claim 1,
It is characterized in that, the link delay of measurement host node to each child node includes：
By forward delay interval measuring command, transmission delay measurements sequence and reception between host node FPGA and child node FPGA are utilized
The mode of feedback sequence realizes the measurement of link delay.
3. the method for the distributed parallel computing environment synchronised clock transmission based on high speed serialization link as described in claim 1,
It is characterized in that, the link delay that the host node is obtained based on measurement, configuring the clock delay value of each child node includes：
The host node is in link has been measured after the link delay value of all child nodes, by sending length of delay configuration sequence
Mode configures the clock delay value of each child node.
4. the method for the distributed parallel computing environment synchronised clock transmission based on high speed serialization link as described in claim 1,
It is characterized in that, the host node, which sends synchronised clock, to be included：
The host node transmits specific control code into data in link layer stream to realize the transmission of synchronised clock.
5. the method for the distributed parallel computing environment synchronised clock transmission based on high speed serialization link as claimed in claim 4,
It is characterized in that, the synchronised clock that each child node recovers to obtain from link the host node transmission includes：
Synchronised clock control code in each child node monitoring data link layer, and recover from the clock Synchronization Control code
Go out the synchronised clock that the host node is sent.
6. the method for the distributed parallel computing environment synchronised clock transmission based on high speed serialization link as described in claim 1,
It being characterized in that, the measurement for a link delay, host node will send a delay measurements sequence, while with local high frequency
Clock opens counter, and child node, which receives, counter at once after Time delay measurement sequence send a feedback sequence, content and delay measurements
Sequence is consistent, is identified for host node, after host node receives feedback sequence, closes counter, obtains child node at this time
Link delay.
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