CN205490577U - System for use difference signal transmission synchronized clock - Google Patents
System for use difference signal transmission synchronized clock Download PDFInfo
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- CN205490577U CN205490577U CN201620143067.5U CN201620143067U CN205490577U CN 205490577 U CN205490577 U CN 205490577U CN 201620143067 U CN201620143067 U CN 201620143067U CN 205490577 U CN205490577 U CN 205490577U
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Abstract
The utility model relates to a system for use difference signal transmission synchronized clock belongs to civil engineering field, is applied to structure safety and health monitoring trade. It includes PC, switch, main equipment, synchronized clock input port, synchronized clock output port, slave unit, paired line, FPGA, RJ45 input terminal, RJ45 output terminal, the PC through the switch will main equipment, the slave unit cascades together. The utility model discloses a through the full differential signal of physical medium transmission that utilizes the paired line, the effectual synchronized clock of multiple devices when carrying out synchronous sampling that has improved stabilizes the transmission problem for systematic stability promotes greatly.
Description
Technical field
This utility model relates to a kind of system using differential signal transmission synchronised clock, belongs to field of civil engineering, is applied to structural safety health monitoring industry.
Background technology
Prior art: at present when relating to multiple devices and sensor being carried out synchronous data collection, the collection stringent synchronization being desirable that between equipment and equipment, ensure phase contrast within the specific limits, such as when the vibration characteristics that assessment automobile is overall or when assessing bridge at high capacity waggon excessively, firstly the need of the key position installation sensor at testee, and need to consider at a time, gather the sensing data at each position simultaneously, the overall dynamics characteristic of testee could be embodied, the data of the most each measuring point are not that synchronization occurs, the most overall assessment result will be nonsensical.
Synchronous acquisition between multiple devices to be realized, general employing main frame transmission synchronised clock is to from machine, and concrete implementation mode is typically also TTL or CMOS logic level, but single-ended digital signal is easily subject to external interference, thus produce clock entanglement, cause gathering data exception from machine.
Summary of the invention
This utility model is in order to overcome drawbacks described above, purpose is to provide a kind of system using differential signal transmission synchronised clock, solve the transmission avoiding the interference effect of outside to use signal in synchronised clock transmitting procedure again, thus ensure the reliability of multiple devices synchronous acquisition.
This utility model to achieve these goals, adopts the following technical scheme that
A kind of system using differential signal transmission synchronised clock, it include PC, switch, main equipment, synchronised clock input port, synchronised clock output port, from equipment, twisted-pair feeder, FPGA, RJ45 input terminal, RJ45 lead-out terminal；
PC is by switch by main equipment, subordinate devices cascaded together.
Synchronised clock input port, synchronised clock output port it is provided with on main equipment；
Main equipment is connected with from equipment by twisted-pair feeder；
Synchronizing clock signals is sent to the RJ45 input terminal from equipment by twisted-pair feeder by main equipment, and synchronizing clock signals is sent to RJ45 lead-out terminal by FPGA, and synchronizing clock signals is sent to FPGA by RJ45 input terminal.
Further, main equipment passes through twisted-pair feeder for providing synchronised clock from equipment.
The principle that this utility model realizes, by using double RJ45 interfaces of embedded with network transformator, the twisted-pair feeder utilizing RJ45 realizes the transmission of fully differential signal, and producing of differential clocks is generated by the FPGA of system, realizes the output of differential signal by configuring differential pairs pins.Configuring an Acquisition Instrument in system is main equipment, other collecting devices are from equipment, main equipment provides fully differential synchronizing clock signals to be transferred to the First RJ45 input interface from machine by RJ45 output interface, First is after the RJ45 input interface of machine receives the fully differential synchronised clock that main frame is sent, in addition to being supplied to the machine and carrying out synchronous acquisition, synchronised clock is passed through after internal FPGA shaping again again RJ45 output interface transmission second again from machine, by that analogy, because fully differential signal is that the signal in both threads is done difference, it is thus possible to be reasonably resistant to external common-mode interference, improve the reliability of synchronised clock transmission.
The beneficial effects of the utility model:
This utility model patent, by utilizing the physical medium transport fully differential signal of twisted-pair feeder, effectively raises the multiple devices synchronised clock when carrying out synchronous acquisition and stablizes transmission problem so that the stability of system is greatly promoted.
Accompanying drawing explanation
Fig. 1 is connection block diagram of the present utility model；
Fig. 2 is that fully differential synchronised clock of the present utility model produces block diagram；
Fig. 3 is fully differential clock signal timing diagram of the present utility model.
Detailed description of the invention
1,2,3 pairs of this utility model are described in detail below in conjunction with the accompanying drawings:
A kind of system using differential signal transmission synchronised clock, it include PC 1, switch 2, main equipment 3, synchronised clock input port 4, synchronised clock output port 5, from equipment (6,7,8), twisted-pair feeder 9, FPGA10, RJ45 input terminal 11, RJ45 lead-out terminal 12；
PC 1 by switch 2 by main equipment 3, be concatenated together from equipment 6,7,8.
Synchronised clock input port 4, synchronised clock output port 5 it is provided with on main equipment 3；
Main equipment 3 is connected with from equipment 6 by twisted-pair feeder 9；
Synchronizing clock signals is sent to the RJ45 input terminal 11 from equipment 6 by twisted-pair feeder 9 by main equipment 3, and synchronizing clock signals is sent to RJ45 lead-out terminal 12 by FPGA10, and synchronizing clock signals is sent to FPGA10 by RJ45 input terminal 11.
Main equipment 3 passes through twisted-pair feeder 9 for providing synchronised clock from equipment 6.
This utility model patent is in implementation process, first by multiple devices by twisted-pair feeder series connection hand in hand, from the beginning of main frame, it is sequentially connected with, and by same for the communication interface of equipment connection on switches, on-the-spot notebook computer connects switch by netting twine again, after whole system cable connects, and it is electrified, begins to carry out the configuration of equipment mode of operation, first the equipment providing synchronised clock being configured to main frame, other are configured to successively from machine.After having configured, start and gather, at this moment carry out synchronous acquisition under the frequency of the synchronised clock that multiple devices just may be simultaneously operated in main frame offer.
Claims (2)
1. use a system for differential signal transmission synchronised clock, it include PC (1), switch (2), main equipment (3), synchronised clock input port (4), synchronised clock output port (5), from equipment (6,7,8), twisted-pair feeder (9), FPGA(10), RJ45 input terminal (11), RJ45 lead-out terminal (12)；
It is characterized in that: PC (1) by switch (2) by main equipment (3), be concatenated together from equipment (6,7,8)；Synchronised clock input port (4), synchronised clock output port (5) it is provided with on main equipment (3)；
Main equipment (3) is connected with from equipment (6) by twisted-pair feeder (9)；
Synchronizing clock signals is sent to the RJ45 input terminal (11) from equipment (6) by twisted-pair feeder (9) by main equipment (3), synchronizing clock signals is by FPGA(10) it is sent to RJ45 lead-out terminal (12), synchronizing clock signals is sent to FPGA(10 by RJ45 input terminal (11)).
The system of use differential signal transmission synchronised clock the most according to claim 1, it is characterised in that: main equipment (3) is to provide synchronised clock from equipment (6) by twisted-pair feeder (9).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201620143067.5U CN205490577U (en) | 2016-02-26 | 2016-02-26 | System for use difference signal transmission synchronized clock |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201620143067.5U CN205490577U (en) | 2016-02-26 | 2016-02-26 | System for use difference signal transmission synchronized clock |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN205490577U true CN205490577U (en) | 2016-08-17 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201620143067.5U Active CN205490577U (en) | 2016-02-26 | 2016-02-26 | System for use difference signal transmission synchronized clock |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108632015A (en) * | 2017-03-21 | 2018-10-09 | 发那科株式会社 | The communication means of slave unit, serial communication system and serial communication system |
-
2016
- 2016-02-26 CN CN201620143067.5U patent/CN205490577U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108632015A (en) * | 2017-03-21 | 2018-10-09 | 发那科株式会社 | The communication means of slave unit, serial communication system and serial communication system |
| US10374736B2 (en) | 2017-03-21 | 2019-08-06 | Fanuc Corporation | Slave device, serial communications system, and communication method for serial communications system |
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