CN108111246B

CN108111246B - A method of the distributed parallel computing environment synchronised clock transmission based on high speed serialization link

Info

Publication number: CN108111246B
Application number: CN201711335924.7A
Authority: CN
Inventors: 陈耀武; 刘雪松
Original assignee: Zhejiang University ZJU
Current assignee: Zhejiang University ZJU
Priority date: 2017-12-14
Filing date: 2017-12-14
Publication date: 2019-09-20
Anticipated expiration: 2037-12-14
Also published as: CN108111246A

Abstract

The method for the distributed parallel computing environment synchronised clock transmission based on high speed serialization link that the invention discloses a kind of, comprising: the link delay of measurement host node to each child node；The link delay that the host node is obtained based on measurement configures the clock delay value of each child node；The host node sends synchronised clock；Each child node is restored to obtain the synchronised clock that the host node is sent from link；Each child node will restore obtained synchronised clock, postpone the synchronised clock after received clock delay value as local.This method on the hardware foundation of differential link, can realize transmission and the local recovery of synchronised clock, guarantee the stability of synchronised clock transmission, and can reduce system hardware complexity, and then reduce hardware spending and hardware maintenance cost.

Description

It is a kind of based on high speed serialization link distributed parallel computing environment synchronised clock transmission Method

Technical field

The present invention relates to fields of communication technology, and in particular to a kind of distributed parallel computing environment based on high speed serialization link is same The method for walking clock transfer.

Background technique

Traditional data collection and transfering system, it is total using 100 m ethernet or other industry spots between each child node Line is attached.In order to guarantee that all child nodes can start simultaneously at sampling, system needs to safeguard a synchronised clock.The synchronization Clock is generally safeguarded using dedicated hardware circuit.To guarantee synchronism, the host node of synchronised clock is sent to each height The line delay of node will guarantee almost the same.When there are many systematic sampling channel, need to safeguard a large amount of synchronised clock transmission Link, hardware spending are very big.

Summary of the invention

The distributed parallel computing environment synchronised clock transmission based on high speed serialization link that the object of the present invention is to provide a kind of Method.This method on the hardware foundation of differential link, can realize transmission and the local recovery of synchronised clock, guarantee to synchronize The stability of clock transfer, and can reduce system hardware complexity, and then reduce hardware spending and hardware maintenance cost.

To achieve the above object, technical solution provided by the invention is as follows:

A method of the distributed parallel computing environment synchronised clock transmission based on high speed serialization link, comprising the following steps:

Measure the link delay of host node to each child node；

The link delay that the host node is obtained based on measurement configures the clock delay value of each child node；

The host node sends synchronised clock；

Each child node is restored to obtain the synchronised clock that the host node is sent from link；

Each child node will restore obtained synchronised clock, postpone the synchronization after received clock delay value as local Clock.

On the basis of above-mentioned technical proposal, in distributed parallel computing environment, it is standby that child node is able to carry out synchronised clock Part, when the decline of link channel communication quality, it is still able to the normal working hours for making system remain certain.

Compared with prior art, the device have the advantages that are as follows:

The method of distributed parallel computing environment synchronised clock transmission provided by the invention based on high speed serialization link, Neng Gou Realize that the transmission of synchronised clock and local recovery are reduced to synchronize and be adopted while keeping system stability in differential link The hardware spending for collecting Transmission system, has broad application prospects.

Detailed description of the invention

Fig. 1 is the method for the distributed parallel computing environment synchronised clock transmission based on high speed serialization link that embodiment provides Flow diagram；

The measurement process schematic diagram of link delay of the Fig. 2 between the embodiment host node provided and child node；

Fig. 3 is the structural schematic diagram of delay measurements sequence and feedback sequence that embodiment provides；

Fig. 4 is the structural schematic diagram for the length of delay configuration sequence that embodiment provides；

Fig. 5 is the implementation schematic diagram that the host node that embodiment provides sends synchronised clock；

Fig. 6 is the schematic diagram localized after the synchronised clock for the child node that embodiment provides restores；

Fig. 7 be embodiment provide be the differential link physical layer that host node FPGA and child node FPGA are realized module Figure.

Specific embodiment

To make the objectives, technical solutions, and advantages of the present invention more comprehensible, this hair with reference to the accompanying drawings and embodiments It is bright to be described in further detail.It should be appreciated that the specific embodiments described herein are only used to explain the present invention, and The scope of protection of the present invention is not limited.

The present embodiment is related to the data collection system based on high speed serialization link, and in particular to a kind of realization the type system The method that synchronised clock and data are transmitted in serial link simultaneously.

Fig. 1 is the method for the distributed parallel computing environment synchronised clock transmission provided in this embodiment based on high speed serialization link Flow diagram.Referring to Fig. 1, synchronised clock transmission method provided in this embodiment the following steps are included:

S101, the link delay of measurement host node to each child node.

In this step, specifically, mainly by forward delay interval measuring command, host node FPGA and child node FPGA are utilized Between send delay measurements order and receive feedback command time difference, calculate the transmission delay time, realize link delay Measurement.

The measurement process schematic diagram of link delay of the Fig. 2 between the embodiment host node provided and child node.Fig. 3 is The structural schematic diagram of delay measurements sequence and feedback sequence that embodiment provides.Referring to fig. 2, Fig. 3, host node and child node it Between be attached using very high speed serial differential link, physical layer can will be encoded due to coding redundancy using 8b/10b coding mode 10b character afterwards is divided into data character and control character.All 8b characters all use two kinds of 10b codings of CRD+ and CRD-, with Guarantee DC balance when transmission.The present embodiment is using control character K1 as the feature frame head of delay measurements sequence, delay measurements Sequence and feedback sequence include two control character K1 and child node address Addr (H), Addr (L).

Measurement for a link delay, host node will send a delay measurements sequence, while with local high frequency Clock opens counter, and child node, which receives, counter at once after Time delay measurement sequence send a feedback sequence, content and delay measurements Sequence is consistent, is identified for host node, after host node receives feedback sequence, closes counter, obtains child node at this time Link delay.

S102, the link delay that the host node is obtained based on measurement configure the clock delay value of each child node.

In the present embodiment, specifically, the host node after the link delay value of all child nodes, leads in having measured link The mode for sending length of delay configuration sequence is crossed, configures the clock delay value of each child node, each child node receives the length of delay and matches Local address is compared after setting sequence, then take out the clock delay value in length of delay configuration sequence, and local clock is set if they are the same Length of delay.

Fig. 4 is the structural schematic diagram for the length of delay configuration sequence that embodiment provides, referring to fig. 4, provided in this embodiment to prolong Value configuration sequence is used as feature frame head using control character K2 late, is target child node address after 2 control character K2, Zhi Houwei The length of delay (Delay) of 8 characters, a high position is preceding.

S103, the host node send synchronised clock.

Specifically, the host node transmits specific control code into data in link layer stream to realize the biography of synchronised clock It is defeated.Fig. 5 is the implementation schematic diagram that the host node that embodiment provides sends synchronised clock.As shown in figure 5, by control character K3 As synchronised clock identity code.According to the frequency of synchronised clock, host node is in the character stream of data link layer according to fixed Control character K3 is inserted into realize the transmission of synchronised clock in interval.

S104, each child node are restored to obtain the synchronised clock that the host node is sent from link.

Specifically, the synchronised clock control code in each child node monitoring data link layer, and it is synchronous from the clock The synchronised clock that the host node is sent is recovered in control code.

Character in child node monitoring data link indicates that synchronised clock transmission starts if detecting control character K3, Often receiving a control character K3 later indicates the rising edge or failing edge of synchronised clock.Child node is same according to receiving The state for walking the clock last time carries out clock overturning, Lai Huifu synchronised clock.

S105, the synchronised clock that each child node obtains recovery are used as locally after postponing received clock delay value Synchronised clock.

Fig. 6 is the schematic diagram localized after the synchronised clock for the child node that embodiment provides restores.As shown in fig. 6, when section Point recovers synchronised clock, is started counting at once with local clock, once clock delay value M phase obtained in count value and S102 Meanwhile starting to generate the synchronised clock after delay, which will be as local real synchronised clock.

The module for the differential link physical layer that it is host node FPGA that Fig. 7, which is provided in this embodiment, and child node FPGA is realized Figure, as shown in fig. 7, differential link physical layer includes:

As described in Fig. 7 (a), transmitting terminal:

Tx_buffer caches the data from data link layer.

It sends control logic and realizes data, synchronised clock, delay measurements and the switching of configuration.

Scrambling module generates pseudo-random sequence and send data flow by a linear shift register carries out exclusive or reduction The EMI noise of data flow.

The conversion of 8b/10b conversion module realization 8b to 10b.

As described in Fig. 7 (b), receiving end:

The conversion of 10b/8b conversion module realization 10b to 8b.

It goes to disturb module and passes through a linear shift register realization descrambling operation synchronous with transmitting terminal.

Receive control logic, the operation such as control code in the configuration of realization length of delay, removal data character stream.

Rx_buffer caching is from the data for receiving control logic.

The transmission of synchronised clock can be realized in the distributed parallel computing environment based on high speed serialization link using this method And the local recovery of child node reduces the hardware spending of synchronous acquisition Transmission system while keeping system stability.By In the addition of programmable logic, so that hardware configuration is simplified, is expanded conducive to the system under complex application context and function increases By force.

Technical solution of the present invention and beneficial effect is described in detail in above-described specific embodiment, Ying Li Solution is not intended to restrict the invention the foregoing is merely presently most preferred embodiment of the invention, all in principle model of the invention Interior done any modification, supplementary, and equivalent replacement etc. are enclosed, should all be included in the protection scope of the present invention.

Claims

1. a kind of method of the distributed parallel computing environment synchronised clock transmission based on high speed serialization link, comprising the following steps:

By forward delay interval measuring command, transmission delay measurements sequence and reception between host node FPGA and child node FPGA are utilized The mode of feedback sequence realizes the measurement of link delay, and specifically, the measurement for a link delay, host node will A delay measurements sequence is sent, while opening counter with local high frequency clock, after child node receives Time delay measurement sequence Counter at once to send a feedback sequence, content is consistent with delay measurements sequence, is identified for host node, and host node receives feedback After sequence, counter is closed, obtains the link delay of child node at this time；

The host node after the link delay value of all child nodes, passes through transmission length of delay configuration sequence in having measured link Mode configures the clock delay value of each child node；

The host node transmits specific control code into data in link layer stream to realize the transmission of synchronised clock；

Synchronised clock control code in each child node monitoring data link layer, and restore from the clock synchronously control code The synchronised clock that the host node is sent out；

Each child node will restore obtained synchronised clock, when postponing the synchronization after received clock delay value as local Clock.