CN102315849A - Method for generating reference clock signal and data receiving and transmitting system - Google Patents
Method for generating reference clock signal and data receiving and transmitting system Download PDFInfo
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- CN102315849A CN102315849A CN201010220056XA CN201010220056A CN102315849A CN 102315849 A CN102315849 A CN 102315849A CN 201010220056X A CN201010220056X A CN 201010220056XA CN 201010220056 A CN201010220056 A CN 201010220056A CN 102315849 A CN102315849 A CN 102315849A
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Abstract
The invention provides a method for generating a reference clock signal and a data receiving and transmitting system. The data receiving and transmitting system comprises a pressure-control oscillator, a lock-phase ring unit and a data receiver, wherein the pressure-control oscillator is used for generating the reference clock signal. The lock-phase ring unit is used for increasing the clock frequency of the reference clock signal so as to generate a lock-phase ring clock signal. The data receiver is used for receiving input data stream and the lock-phase ring clock signal and comparing the lock-phase ring clock signal and a clock signal of the input data stream so as to output a voltage-adjusting signal to the pressure-control oscillator; and the pressure-control oscillator is used for adjusting the clock frequency of the generated reference clock signal according to the voltage-adjusting signal so as to lock the clock frequency of the lock-phase ring clock signal generated by the lock-phase ring unit to the basic frequency of the clock signal of the input data stream.
Description
Technical field
The present invention relates to a kind of data receiving-transmitting system, relate in particular to a kind of method and data receiving-transmitting system that produces reference clock signal.
Background technology
Fig. 1 is data collector (transceiver) framework of existing integrated chip (integrated chip).Wherein, Data collector 100 comprise phase locked-loop unit (Phase Lock Loop, PLL) 110, data transmitter (Transmitter, TX) 120, have a clock and data recovery (Clock Data Recovery; CDR) data sink of function (Receiver, RX) 130 pieces such as front-end circuit such as grade.This integrated chip also utilizes a quartz (crystal) device 140 to produce the accurately clock signal of (differing tens of ppm with target frequency) of frequency, the reference clock in order to as its transceive data the time.In detail, phase locked-loop unit 110 can use this reference clock as input, and produces the pll clock output that frequency is the multiple of reference clock frequency.This pll clock promptly is used as the reference clock of clock and data recovery, and in order to produce the data flow of reclocking (retimed).The clock output that is produced during above-mentioned clock and data recovery is based on the fundamental frequency of the input traffic that receives and produces.In addition, above-mentioned pll clock also can be used as signal source of clock, and in order to send data flow (not having the accompanying clock signal originally).
The accuracy of the reference frequency of above-mentioned pll clock (accuracy) is considerable in Serial Data Transfer Mode (serial datatransmission), and only can allow quite little frequency error.In detail, this frequency error must satisfy the specification of given standard, be generally admissible maximum bit error rate (Bit ErrorRate, BER).For example, (Universal Serial Bus, USB) in 2.0 the fast mode (High-Speed Mode, HS Mode), the accuracy of required pll clock frequency is the positive and negative 500ppm of the fundamental frequency of reception (RX) data flow at USB.Though commercial quartz devices can produce the clock signal that frequency error is lower than positive and negative 100ppm, and can be used as desirable signal source of clock, the costing an arm and a leg of this quartz devices, and can occupy bigger circuit board space.
Summary of the invention
The present invention provides a kind of method and data receiving-transmitting system that produces reference clock signal, can produce frequency reference clock signal accurately, and in order to transceive data.
The present invention proposes a kind of data receiving-transmitting system that produces reference clock signal, and it comprises voltage controlled oscillator, phase locked-loop unit and data sink.Wherein, voltage controlled oscillator is in order to produce reference clock signal.Phase locked-loop unit is to connect voltage controlled oscillator, and in order to increase the clock frequency of reference clock signal, to produce pll clock signal.Data sink is to connect phase locked-loop unit and voltage controlled oscillator; In order to receive input traffic and pll clock signal; And with the pll clock signal clock signal comparison of input traffic therewith; Adjust signal to voltage controlled oscillator with output voltage; Wherein voltage controlled oscillator is the clock frequency of the reference clock signal that produced according to voltage adjustment signal adjustment, is locked to the fundamental frequency of the clock signal of input traffic with the clock frequency of pll clock signal that phase locked-loop unit is produced.
In one embodiment of this invention, above-mentioned data sink comprises frequency detector and frequency locking controller.Wherein, frequency detector is in order to receiving input traffic, and with the fundamental frequency of the clock frequency of pll clock signal and the clock signal of input traffic relatively, with the generation frequency adjusted signal.The frequency locking controller is in order to receive frequency adjustment signal and pll clock signal, to produce voltage adjustment signal.
In one embodiment of this invention, above-mentioned frequency detector is in the fundamental frequency of the clock signal of input traffic during greater than the clock frequency of pll clock signal, the frequency adjusted signal that output logic is high; And in the fundamental frequency of the clock signal of input traffic during less than the clock frequency of pll clock signal, the frequency adjusted signal that output logic is low.
In one embodiment of this invention, above-mentioned frequency locking controller is when receiving the frequency adjusted signal of logic high, heightens the numerical value of voltage adjustment signal, improves the clock frequency of reference clock signal with the control voltage controlled oscillator; And when receiving the frequency adjusted signal of logic low, turn down the numerical value of voltage adjustment signal, reduce the clock frequency of reference clock signal with the control voltage controlled oscillator.
In one embodiment of this invention, above-mentioned data sink comprises clock data recovery circuit, start frame decoder and frequency locking controller.Wherein, clock data recovery circuit is in order to receiving input traffic and pll clock signal, and uses this pll clock signal clock as a reference, so that the input traffic that is received is flowed for chronometric data again.The start frame decoder is the start frame in order to each frame in a plurality of frames of finding out the reclocking data flow, to produce a start frame signal.The frequency locking controller is these start frame signal and pll clock signals that produced in order to reception start frame decoder, and utilizes pll clock signal that these start frame signals are counted, to produce voltage adjustment signal.
In one embodiment of this invention; Above-mentioned frequency locking controller comprises the number of the start frame signal of being counted and standard value is compared; And during less than standard value, heighten the numerical value of voltage adjustment signal at this number, improve the clock frequency of reference clock signal with the control voltage controlled oscillator; Otherwise, when this number overgauge value, turn down the numerical value of voltage adjustment signal, reduce the clock frequency of reference clock signal with the control voltage controlled oscillator.
In one embodiment of this invention, above-mentioned voltage controlled oscillator is according to voltage adjustment signal, and the clock frequency of the reference clock signal that is produced is improved or reduce a frequency class.Wherein, described frequency class is the frequency gain of voltage controlled oscillator and the product of voltage variety.
In one embodiment of this invention; Above-mentioned data receiving-transmitting system also comprises digital analog converter; It is to be disposed between voltage controlled oscillator and the data sink; And convert voltage variety in order to voltage adjustment signal with data sink output, with the clock signal of the adjustment reference clock signal that voltage controlled oscillator was produced.
In one embodiment of this invention, above-mentioned data receiving-transmitting system also comprises data transmitter, and it is to connect phase locked-loop unit, and in order to reception output stream and pll clock signal, and according to this pll clock signal transmission output stream.
The present invention proposes a kind of method that produces reference clock signal, and it is to utilize voltage controlled oscillator to produce reference clock signal, and increases the clock frequency of this reference clock signal, to produce pll clock signal.Then; The clock signal of pll clock signal and input traffic is compared; With output voltage adjustment signal; Last then, be locked to the fundamental frequency of the clock signal of input traffic with clock frequency with the pll clock signal that is produced according to the clock frequency of this voltage adjustment signal adjustment reference clock signal that voltage controlled oscillator produced.
Based on above-mentioned; The method of generation reference clock signal of the present invention and data receiving-transmitting system are by in integrated chip, disposing independently voltage controlled oscillator producing reference clock signal, and the frequency of using the clock signal of the input traffic that receives to proofread this reference clock signal.The result of this check and correction will feed back to voltage controlled oscillator; Clock frequency with the adjustment reference clock signal that voltage controlled oscillator was produced makes the clock frequency of the pll clock signal that phase locked-loop unit produced may be locked to the clock frequency of the clock signal of input traffic.Therefore, the present invention can obtain frequency pll clock signal accurately under the situation of not using quartz devices.
For letting the above-mentioned feature and advantage of the present invention can be more obviously understandable, hereinafter is special lifts embodiment, and conjunction with figs. elaborates as follows.
Description of drawings
Fig. 1 is the framework of the data collector of existing integrated chip.
Fig. 2 is the calcspar of the data receiving-transmitting system of the generation reference clock signal shown in the first embodiment of the invention.
Fig. 3 is the example of the phase locked-loop unit shown in the first embodiment of the invention.
Fig. 4 is the example of the phase locked-loop unit shown in the first embodiment of the invention.
Fig. 5 is the calcspar of the data receiving-transmitting system of the generation reference clock signal shown in the second embodiment of the invention.
Fig. 6 is the method flow diagram of the generation reference clock signal shown in the second embodiment of the invention.
Fig. 7 is the calcspar of the data receiving-transmitting system of the generation reference clock signal shown in the third embodiment of the invention.
Fig. 8 is the method flow diagram of the generation reference clock signal shown in the third embodiment of the invention.
Fig. 9 is the oscillogram of the start frame token shown in the third embodiment of the invention.
Main description of reference numerals:
100: data collector; 140: quartz devices;
110,220,300,400,520,720: phase locked-loop unit;
120,550,750: data transmitter; 910,920: the start frame token;
130,230,530,730: data sink;
200,500,700: data receiving-transmitting system; 210,510,710: voltage controlled oscillator;
302: frequency comparator; 304: phase detectors;
306: the frequency gain register; 308: the phase gain register;
310: the addition multiplexer; 312: the subtraction multiplexer;
314: adder; 316: subtracter;
318: the anchor register; 320: numerically-controlled oscillator;
322: digital control register; 324: controller;
402: phase-frequency detector; 404: charge pump;
406: ring wave filter; 408: voltage-controlled oscillator;
532: frequency detector; 534,736: the frequency locking controller;
540,740: digital analog converter; 732: clock data recovery circuit;
734: the start frame decoder; 900: input traffic;
S602～612: the step of the generation reference clock signal method of second embodiment of the invention;
S802～814: the step of the generation reference clock signal method of third embodiment of the invention.
Embodiment
The present invention is configured in the inner voltage controlled oscillator of integrated chip with one to replace traditional quartz devices, and sends the required reference clock signal of data flow in order to produce.Wherein, (Process-Voltage-Temperature, the variation on PVT) all can increase the frequency error of signal that oscillator produces, and makes oscillator can't use on the serial data transceiver because semiconductor technology, voltage and temperature.In order to compensate these factors for the influence of oscillator and let this oscillator be able to be applied in the integrated chip; The present invention adopts a cover reponse system; By with the fundamental frequency of institute's receiving data stream and phase locked-loop unit (Phase LockLoop, PLL) clock frequency relatively, to send frequency adjusted signal; With the clock frequency of the adjustment reference clock signal that oscillator was produced, and then obtain frequency pll clock signal comparatively accurately.Explain that with next act embodiment the present invention produces the function mode of the data receiving-transmitting system of reference clock signal.
First embodiment
Fig. 2 is the calcspar of the data receiving-transmitting system of the generation reference clock signal shown in the first embodiment of the invention.Please with reference to Fig. 2, the data receiving-transmitting system 200 of present embodiment comprises voltage controlled oscillator 210, phase locked-loop unit 220 and data sink 230, and its function division is following:
Voltage controlled oscillator 210 is that it for example is a resistance (RC) oscillator, ring-like (Ring) oscillator or inductance/capacitance (LC) oscillator, can produce reference clock signal in order to the generation reference clock signal.
Phase locked-loop unit 220 is to be connected to voltage controlled oscillator 210, and in order to utilize the reference clock signal of voltage controlled oscillator 210 outputs, exports the pll clock signal of a preset frequency and phase place.
In this exemplary embodiment, phase locked-loop unit 220 can be implemented with digital mode.For instance, Fig. 3 is the example of the phase locked-loop unit shown in the first embodiment of the invention.Please with reference to Fig. 3; Phase locked-loop unit 300 can comprise frequency comparator (frequency comparator) 302, phase detectors (phasedetector) 304, frequency gain register (frequency gain register) 306, phase gain register (phase gain register) 308, addition multiplexer (adder MUX) 310, subtraction multiplexer (substrate MUX) 312, adder 314, subtracter 316, anchor register (anchorregister) 318, numerically-controlled oscillator (Digital Control Oscillator, DCO) 320, digital control register 322 and controller 324.
In another exemplary embodiment, phase locked-loop unit 220 also can be implemented with the mode of analog or digital analog mixed.For instance, Fig. 4 is the example of the phase locked-loop unit shown in the first embodiment of the invention.Please with reference to Fig. 4; Phase locked-loop unit 400 comprises phase-frequency detector (phase frequency detector; PFD) 402, charge pump (charge pump, CP) 404, ring wave filter (loop filter, LP) 406; And voltage-controlled oscillator (voltage controlled oscillator, VCO) 408.Wherein, Fin is an incoming frequency; Fout is an output frequency; Vup is the voltage rising signals; Vdn is a voltage reduction signal; Vlp is a voltage signal; Vcp is filtered voltage signal.In this article, because phase-locked loop is the technology that those skilled in the art are familiar with, so no longer add to give unnecessary details at this.
Data sink 230 is to connect phase locked-loop unit 220 and voltage controlled oscillator 210; Transmit and input traffic that comes and the pll clock signal of exporting by phase locked-loop unit 220 in order to receive by the outside; And with the pll clock signal clock signal comparison of input traffic therewith; To export voltage adjustment signal a to voltage controlled oscillator 210, with the clock frequency of the control voltage controlled oscillator adjustment reference clock signal that it was produced.
In detail; Voltage controlled oscillator 210 for example is the clock frequency according to the voltage adjustment signal adjustment reference clock signal that it produced; And produce pll clock signal, data sink 130 comparison clock signals by repeating above-mentioned phase locked-loop unit 220; And the step of voltage controlled oscillator 210 adjustment clock frequencies, the clock frequency of the pll clock signal that finally can phase locked-loop unit 220 be produced is locked to the fundamental frequency of the clock signal of input traffic.
What need explanation is; Comparison for the clock signal of above-mentioned pll clock signal and input traffic; The present invention provides two kinds of exemplary embodiment: a kind of is that the clock frequency of pll clock signal is directly compared with the fundamental frequency of the clock signal of input traffic, to determine whether to increase and decrease the clock frequency of the reference clock signal that voltage controlled oscillator produced; Another kind of then be the number of the start frame of a plurality of frames in the data flow in the unit of account time, whether increase and decrease the clock frequency of the reference clock signal that voltage controlled oscillator produced with decision.Below promptly respectively lifting an embodiment to above-mentioned dual mode specifies.
Second embodiment
Fig. 5 is the calcspar of the data receiving-transmitting system of the generation reference clock signal shown in the second embodiment of the invention.Fig. 6 is the method flow diagram of the generation reference clock signal shown in the second embodiment of the invention.Please be simultaneously with reference to Fig. 5 and Fig. 6; The data receiving-transmitting system 500 of present embodiment comprises voltage controlled oscillator 510, phase locked-loop unit 520, data sink 530, digital analog converter 540 and data transmitter 550, and wherein data sink 530 also comprises frequency detector 532 and frequency locking controller 534.Even below with the detailed step of above-mentioned each element explanation reference clock signal production method of the present invention:
At first, utilize voltage controlled oscillator 510 to produce reference clock signal (step S602).This voltage controlled oscillator 510 for example is a resistance (RC) oscillator, ring-like (Ring) oscillator or inductance/capacitance (LC) oscillator, can produce reference clock signal.And the reference clock signal that this moment, voltage controlled oscillator 510 was produced for example is a predetermined value, and is proofreaied and correct gradually by the circuit at rear.
Then, utilize phase locked-loop unit 520 to increase the clock frequency f (ref_n) by the reference clock signal of voltage controlled oscillator 510 outputs, and produce pll clock signal f (pll) (step S604), f (pll)=M*f (ref_n) wherein, M are one greater than 1 numerical value.
Then; Utilizing frequency detector 532 to receive by the outside by data sink 530 transmits and input traffic that comes and the pll clock signal that is come by phase locked-loop unit 520 transmission; And with the clock frequency of pll clock signal therewith the clock signal of input traffic fundamental frequency relatively, to produce frequency adjusted signal (step S606).In detail; Data sink 530 be utilize frequency detector 532 relatively the clock frequency of pll clock signals produce frequency adjusted signal after the clock signal of input traffic therewith, therefore make the clock frequency of pll clock signal near the clock signal of input traffic.Wherein, this frequency detector 532 can be a speed detector (Rotational Frequency Detector), wideband detector (Wide Range Frequency Detector), differential frequency detector (DifferentialFrequency Detector) or digital quadratic surface frequency detector (Digital QuadricorrelatorFrequency Detector).
In addition, in one embodiment, frequency detector 532 for example is in the clock frequency of pll clock signal during less than the fundamental frequency of the clock signal of input traffic, and the frequency adjusted signal of a logic high of output is to heighten frequency; And in the clock frequency of pll clock signal during greater than the fundamental frequency of the clock signal of input traffic, the frequency adjusted signal of a logic low of output is to turn down frequency.In addition; In another embodiment; Frequency detector 532 for example is to reduce signal by output one class frequency increase signal and frequency to adjust frequency; Wherein in the clock frequency of pll clock signal during less than the fundamental frequency of the clock signal of input traffic, the frequency that the frequency of a logic high of output increases a signal and a logic low reduces signal, to heighten frequency; During greater than the fundamental frequency of the clock signal of input traffic, the frequency that the frequency of a logic low of output increases a signal and a logic high reduces signal, to turn down frequency in the clock frequency of pll clock signal.But the invention is not restricted to above-mentioned dual mode.
Above-mentioned frequency adjusted signal is to export frequency locking controller 534 to; And frequency locking controller 534 is except receiving this frequency adjusted signal; Also receive the pll clock signal that produces by phase locked-loop unit 520; And, produce voltage adjustment signal (step S608) according to this frequency adjusted signal and pll clock signal.
In detail, frequency locking controller 534 for example is when receiving the frequency adjusted signal of the logic high of being exported by frequency detector 532, heightens the numerical value of voltage adjustment signal, improves the clock frequency of reference clock signals with control voltage controlled oscillator 510; And when receiving the frequency adjusted signal of the logic low of exporting by frequency detector 532, turn down the numerical value of voltage adjustment signal, reduce the clock frequency of reference clock signals with control voltage controlled oscillator 510.
For instance, as shown in Figure 5, frequency locking controller 534 for example can produce the voltage adjustment signal FREQ_D of a N position, and increases or reduce the numerical value of this voltage adjustment signal FREQ_D according to the frequency adjusted signal of frequency detector 532 outputs.
The voltage adjustment signal FREQ_D of this N position then can be sent to digital analog converter 540; And convert the voltage variety VA (step S610) of simulation into by digital analog converter 540, and the clock frequency of the reference clock signal that can be produced in order to adjustment voltage controlled oscillator 510.
In detail, voltage controlled oscillator 510 is the voltage variety VA according to digital analog converter 540 output, the clock frequency of the reference clock signal that it produced is improved or reduces a frequency class, and export adjusted reference clock signal (step S612).Above-mentioned frequency class for example is the frequency gain Kf of voltage controlled oscillator 510 and the product of voltage variety VA; And the clock frequency f of above-mentioned adjusted reference clock signal (ref_t_n) is the product that former clock frequency f (ref_t_n-1) adds frequency gain Kf and voltage variety VA, i.e. f (ref_t_n)=f (ref_t_n-1)+Kf*VA.
Above-mentioned adjusted reference clock signal then can be imported phase locked-loop unit 520; And increase the clock frequency of these adjusted reference clock signals again by phase locked-loop unit 520; To produce pll clock signal (step S604); And produce pll clock signal, data sink 530 comparison clock signals, digital analog converter 540 changing voltages adjustment signal by repeating above-mentioned phase locked-loop unit 520; And the step of voltage controlled oscillator 510 adjustment clock frequencies; The clock frequency of the pll clock signal that finally can phase locked-loop unit 520 be produced is locked to the fundamental frequency of the clock signal of input traffic, makes this pll clock signal can be used as frequency signal source of clock comparatively accurately, and offers data transmitter 550 to send output stream.
In detail, data transmitter 550 is to be connected to phase locked-loop unit 520, and the pll clock signal that can receive output stream and produced by phase locked-loop unit 520, and sends output stream according to this pll clock signal.
By above-mentioned feedback mechanism; The phase locked-loop unit 520 of present embodiment can be locked to the clock frequency of the pll clock signal that it produced the fundamental frequency or the one of which prearranged multiple of the clock signal of input traffic; Therefore can be with the frequency error reduction (like 100ppm) of pll clock signal; And then replace traditional quartz devices, and as the derived reference signal of integrated chip inside.
The 3rd embodiment
On the other hand; The present invention's USB also capable of using (Universal Serial Bus; USB) defined start frame (Start-of-Frame in 2.0 specifications; SOF) token (Token), the clock signal of coming comparison pll clock signal and input traffic is with the clock frequency of the adjustment reference clock signal that voltage controlled oscillator was produced.
Fig. 7 is the calcspar of the data receiving-transmitting system of the generation reference clock signal shown in the third embodiment of the invention.Fig. 8 is the method flow diagram of the generation reference clock signal shown in the third embodiment of the invention.Please be simultaneously with reference to Fig. 7 and Fig. 8; The data receiving-transmitting system 700 of present embodiment comprises voltage controlled oscillator 710, phase locked-loop unit 720, data sink 730, digital analog converter 740 and data transmitter 750, and wherein data sink 730 also comprises clock data recovery circuit 732, start frame decoder 734 and frequency locking controller 736.The function division of above-mentioned each element is following:
At first; Utilize voltage controlled oscillator 710 to produce reference clock signal f (ref_tn) (step S802); And phase locked-loop unit 720 is to be connected to voltage controlled oscillator 710; And in order to increase the clock frequency by the reference clock signal of voltage controlled oscillator 710 outputs, to produce pll clock signal (step S804).Wherein, voltage controlled oscillator 710 and the function of phase locked-loop unit 720 be with second embodiment in voltage controlled oscillator 510 identical with phase locked-loop unit 520, repeat no more at this.
Different with second embodiment is; The data receiving-transmitting system 700 of present embodiment is to utilize clock data recovery circuit (clock and data recovery circuit) 732 to receive by the outside to transmit and input traffic that comes and the pll clock signal that is produced by phase locked-loop unit 720; And use this pll clock signal clock as a reference, convert the input traffic that is received into reclocking (Retimed) data flow (step S806).Wherein in this exemplary embodiment; Clock data recovery circuit 732 can be oversampling data recovery circuit (oversampling data recovery circuit); But in another exemplary embodiment, it also can be the circuit that burst clock and data recovery circuit (burst-mode clock and data recoverycircuit) or other types come out in order to the clock that will receive data and reduction of data.
Then, find out the start frame of each frame in a plurality of frames of this reclocking data flow by start frame decoder 734, and produce start frame signal (step S808).In detail, external USB device or usb hub (Hub) produce under fast mode or during transmitting data stream, can add a start frame token in the packet front of each frame, for the starting point of each frame of data sink interpretation.
For instance, Fig. 9 is the oscillogram of the start frame token shown in the third embodiment of the invention.Wherein, Fig. 9 illustrates frame N and the frame N-1 in the input traffic 900, and in the front of the packet of these two frames, promptly can add start frame token 910,920 respectively, for data sink interpretation frame N and frame N-1.Wherein, in this exemplary embodiment, can be according to the specification of USB 2.0; Start frame token 910, be spaced apart 125 microseconds (micro-second) between 920; And error range is positive and negative 500ppm, but this at interval also can be 225 microseconds or set according to different specifications, not as limit.
Present embodiment promptly receives start frame signal that is produced by start frame decoder 734 and the pll clock signal that is produced by phase locked-loop unit 720 by frequency locking controller 736; And utilize this pll clock signal to count the start frame signal, to produce voltage adjustment signal (step S810).
In detail; Frequency locking controller 736 for example is that the number of its start frame signal of counting and a standard value are compared; And during less than standard value, promptly heighten the numerical value of voltage adjustment signal at this number, improve the clock frequency of reference clock signals with control voltage controlled oscillator 710; Otherwise, when this number overgauge value, then turn down the numerical value of voltage adjustment signal, reduce the clock frequency of reference clock signal with control voltage controlled oscillator 710.
For instance, the clock frequency of tentative standard pll clock signal is 480 megahertzes (MHz), and is spaced apart 125 microseconds between the start frame token, and then the counting at the start frame token of a phase locked-loop unit in the clock cycle should be 60000.Yet; Under actual state; If the clock frequency of pll clock signal is less than 480MHz; Then will be less than 60000 at the counting of the start frame token of a phase locked-loop unit in the clock cycle, this moment, the frequency locking controller needed by the numerical value of heightening voltage adjustment signal, and the control voltage controlled oscillator improves the clock frequency of reference clock signal; Otherwise; If the clock frequency of pll clock signal is greater than 480MHz; Then will be greater than 60000 at the counting of the start frame token of a phase locked-loop unit in the clock cycle; This moment, the frequency locking controller needed by the numerical value of turning down voltage adjustment signal, and the control voltage controlled oscillator reduces the clock frequency of reference clock signal.By above-mentioned adjustment mode, finally can make the clock frequency of pll clock signal level off to the 480MHz under the standard state.
In addition, said as second embodiment, the frequency locking controller 736 of present embodiment for example can produce the voltage adjustment signal FREQ_D of a N position, and increases and decreases the numerical value of this voltage adjustment signal FREQ_D according to the frequency adjusted signal of frequency detector 532 outputs.Then, convert this voltage adjustment signal FREQ_D the voltage variety VA (step S812) of simulation into by digital analog converter 740, and adjust the clock frequency (step S814) of the reference clock signals that it produced in order to control voltage controlled oscillator 510.Detailed adjustment mode repeats no more at this please with reference to second embodiment.
Above-mentioned adjusted reference clock signal then can be imported phase locked-loop unit 720; And increase the clock frequency of these adjusted reference clock signals again by phase locked-loop unit 720; To produce pll clock signal (step S804); And produce pll clock signal, data sink 730 comparison clock signals, digital analog converter 740 changing voltages adjustment signal by repeating above-mentioned phase locked-loop unit 720; And the step of voltage controlled oscillator 710 adjustment clock frequencies; The clock frequency of the pll clock signal that finally can phase locked-loop unit 720 be produced is locked to the fundamental frequency of the clock signal of input traffic, makes this pll clock signal can be used as frequency signal source of clock accurately, and offers data transmitter 750 to send output stream.
What need explanation is that the framework of above-mentioned second embodiment and the 3rd embodiment also can be incorporated in the same data receiving-transmitting system, and can adopt which kind of mode to adjust with decision by detecting start frame.Wherein, when detecting start frame, promptly adopt the path of clock data recovery circuit, whether the number of the start frame of a plurality of frames in the data flow in the unit of account time increases and decreases the clock frequency of the reference clock signal that voltage controlled oscillator produced with decision; Otherwise the path of then adopting frequency detector directly compares the clock frequency of pll clock signal with the fundamental frequency of the clock signal of input traffic, to determine whether to increase and decrease the clock frequency of the reference clock signal that voltage controlled oscillator produced.
In sum; The method of generation reference clock signal of the present invention and data receiving-transmitting system are by with the clock signal of pll clock signal that phase locked-loop unit produced and input traffic relatively; To judge whether pll clock signal is accurate; And by feedback mechanism judged result is fed back to the voltage controlled oscillator that produces reference clock signal, the clock frequency of the reference clock signal that is produced with adjustment.Via comparison, feedback and set-up procedure repeatedly, finally can the clock frequency of pll clock signal be locked to the fundamental frequency of the clock signal of input traffic, and make the frequency error of pll clock signal meet standard requirements.In view of the above, the present invention promptly can replace traditional quartz devices by a configurable voltage controlled oscillator in integrated chip, and reduces the cost of manufacture of integrated chip.
Though the present invention discloses as above with embodiment; But it is not in order to limit the present invention; Person skilled under any; Do not breaking away from the spirit and scope of the present invention, can change arbitrarily or be equal to replacement, so protection scope of the present invention is as the criterion when the scope that defined with the application's claim.
Claims (20)
1. data receiving-transmitting system that produces reference clock signal comprises:
One voltage controlled oscillator is in order to produce a reference clock signal;
One phase locked-loop unit connects this voltage controlled oscillator, in order to increase a clock frequency of this reference clock signal, to produce a pll clock signal;
And
One data sink; Connect this phase locked-loop unit and this voltage controlled oscillator, in order to receiving an input traffic and this pll clock signal, and with a clock signal of this pll clock signal and this input traffic relatively; To export a voltage adjustment signal to this voltage controlled oscillator, wherein
The clock frequency of this voltage controlled oscillator this reference clock signal that adjustment is produced according to this voltage adjustment signal is locked to a fundamental frequency of this clock signal of this input traffic with the clock frequency of this pll clock signal that this phase locked-loop unit is produced.
2. data receiving-transmitting system according to claim 1, wherein this data sink comprises:
One frequency detector, in order to receiving this input traffic, and this fundamental frequency of this clock signal of clock frequency and this input traffic of this pll clock signal relatively, to produce a frequency adjusted signal;
And
One frequency locking controller is in order to receive this frequency adjusted signal and this pll clock signal, to produce this voltage adjustment signal.
3. data receiving-transmitting system according to claim 2, wherein this frequency detector comprises:
During greater than the clock frequency of this pll clock signal, export this frequency adjusted signal of a logic high in this fundamental frequency of this clock signal of this input traffic;
And
During less than the clock frequency of this pll clock signal, export this frequency adjusted signal of a logic low in this fundamental frequency of this clock signal of this input traffic.
4. data receiving-transmitting system according to claim 3, wherein this frequency locking controller comprises:
When receiving this frequency adjusted signal of this logic high, heighten a numerical value of this voltage adjustment signal, to control the clock frequency that this voltage controlled oscillator improves this reference clock signal;
And
When receiving this frequency adjusted signal of this logic low, turn down this numerical value of this voltage adjustment signal, to control the clock frequency that this voltage controlled oscillator reduces this reference clock signal.
5. data receiving-transmitting system according to claim 1, wherein this data sink comprises:
One clock data recovery circuit receives this input traffic and this pll clock signal, and uses this pll clock signal clock as a reference, and this input traffic that is received with conversion is a reclocking data flow;
One initial frame decoder is found out a start frame of each frame in a plurality of frames of this reclocking data flow, to produce an initial frame signal;
And
One frequency locking controller receives said start frame signal and this pll clock signal that this start frame decoder is produced, and utilizes this pll clock signal to count said start frame signal, to produce this voltage adjustment signal.
6. data receiving-transmitting system according to claim 5, wherein this frequency locking controller comprises that a number and a standard value with the said start frame signal of being counted compare, wherein
During less than this standard value, heighten a numerical value of this voltage adjustment signal at this number, to control the clock frequency that this voltage controlled oscillator improves this reference clock signal;
And
During greater than this standard value, turn down this numerical value of this voltage adjustment signal at this number, to control the clock frequency that this voltage controlled oscillator reduces this reference clock signal.
7. data receiving-transmitting system according to claim 1, wherein this voltage controlled oscillator comprises according to this voltage adjustment signal, and the clock frequency of this reference clock signal that is produced is improved or reduce a frequency class.
8. data receiving-transmitting system according to claim 7, wherein this frequency class is a frequency gain of this voltage controlled oscillator and the product of a voltage variety.
9. data receiving-transmitting system according to claim 8 also comprises:
One digital analog converter is disposed between this voltage controlled oscillator and this data sink, and this voltage adjustment signal of changing the output of this data sink is this voltage variety, to adjust the clock frequency of this reference clock signal that this voltage controlled oscillator produced.
10. data receiving-transmitting system according to claim 1 also comprises:
One data transmitter connects this phase locked-loop unit, receives an output stream and this pll clock signal, and sends this output stream according to this pll clock signal.
11. a method that produces reference clock signal comprises the following steps:
Utilize a voltage controlled oscillator to produce a reference clock signal;
Increase a clock frequency of this reference clock signal, to produce a pll clock signal;
One clock signal of this pll clock signal and an input traffic is compared, to export a voltage adjustment signal;
And
According to the clock frequency of this voltage adjustment signal adjustment this reference clock signal that this voltage controlled oscillator produced, be locked to a fundamental frequency of this clock signal of this input traffic with clock frequency with this pll clock signal that is produced.
12. method according to claim 11, wherein this clock signal with this pll clock signal and this input traffic compares, and comprises with the step of exporting this voltage adjustment signal:
Receive this input traffic, and this fundamental frequency of this clock signal of clock frequency and this input traffic of this pll clock signal relatively, to produce a frequency adjusted signal;
And
Receive this frequency adjusted signal and this pll clock signal, to produce this voltage adjustment signal.
13. method according to claim 12, this fundamental frequency of this clock signal of the clock frequency of this pll clock signal and this input traffic relatively wherein comprises with the step that produces this frequency adjusted signal:
During greater than the clock frequency of this pll clock signal, export this frequency adjusted signal of a logic high in this fundamental frequency of this clock signal of this input traffic;
And
During less than the clock frequency of this pll clock signal, export this frequency adjusted signal of a logic low in this fundamental frequency of this clock signal of this input traffic.
14. method according to claim 13 wherein receives this frequency adjusted signal and this pll clock signal, comprises with the step that produces this voltage adjustment signal:
When receiving this frequency adjusted signal of this logic high, heighten a numerical value of this voltage adjustment signal, to control the clock frequency that this voltage controlled oscillator improves this reference clock signal;
And
When receiving this frequency adjusted signal of this logic low, turn down this numerical value of this voltage adjustment signal, to control the clock frequency that this voltage controlled oscillator reduces this reference clock signal.
15. method according to claim 11, wherein this clock signal with this pll clock signal and this input traffic compares, and comprises with the step of exporting this voltage adjustment signal:
Receive this input traffic and this pll clock signal, and use this pll clock signal clock as a reference, this input traffic that is received with conversion is a reclocking data flow;
Find out a start frame of each frame in a plurality of frames of this reclocking data flow, to produce an initial frame signal;
And
Receive said start frame signal and this pll clock signal, and utilize this pll clock signal to count said start frame signal, to produce this voltage adjustment signal.
16. method according to claim 15 wherein utilizes this pll clock signal to count said start frame signal, comprises with the step that produces this voltage adjustment signal:
One number and a standard value of the said start frame signal of being counted are compared;
During less than this standard value, heighten a numerical value of this voltage adjustment signal at this number, to control the clock frequency that this voltage controlled oscillator improves this reference clock signal;
And
During greater than this standard value, turn down this numerical value of this voltage adjustment signal at this number, to control the clock frequency that this voltage controlled oscillator reduces this reference clock signal.
17. method according to claim 11, wherein the step according to the clock frequency of this voltage adjustment signal adjustment this reference clock signal that this voltage controlled oscillator produced comprises:
According to this voltage adjustment signal, the clock frequency of this reference clock signal that this voltage controlled oscillator produced is improved or reduces a frequency class.
18. method according to claim 17, wherein this frequency class is a frequency gain of this voltage controlled oscillator and the product of a voltage variety.
19. method according to claim 18 wherein compares in this clock signal with this pll clock signal and this input traffic, after the step of exporting this voltage adjustment signal, also comprises:
Changing this voltage adjustment signal is this voltage variety, to adjust the clock frequency of this reference clock signal that this voltage controlled oscillator produced.
20. method according to claim 18; Wherein in clock frequency according to this voltage adjustment signal adjustment this reference clock signal that this voltage controlled oscillator produced; Be locked to clock frequency after the step of this fundamental frequency of this clock signal of this input traffic, also comprise this pll clock signal that is produced:
Send an output stream according to this pll clock signal.
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