CN102315849B - Method for generating reference clock signal and data receiving and transmitting system - Google Patents

Method for generating reference clock signal and data receiving and transmitting system Download PDF

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Publication number
CN102315849B
CN102315849B CN201010220056.XA CN201010220056A CN102315849B CN 102315849 B CN102315849 B CN 102315849B CN 201010220056 A CN201010220056 A CN 201010220056A CN 102315849 B CN102315849 B CN 102315849B
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China
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clock signal
frequency
signal
clock
controlled oscillator
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CN201010220056.XA
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Chinese (zh)
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CN102315849A (en
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陈安忠
郑文隆
陈维咏
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群联电子股份有限公司
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Abstract

The invention provides a method for generating a reference clock signal and a data receiving and transmitting system. The data receiving and transmitting system comprises a pressure-control oscillator, a lock-phase ring unit and a data receiver, wherein the pressure-control oscillator is used for generating the reference clock signal. The lock-phase ring unit is used for increasing the clock frequency of the reference clock signal so as to generate a lock-phase ring clock signal. The data receiver is used for receiving input data stream and the lock-phase ring clock signal and comparing the lock-phase ring clock signal and a clock signal of the input data stream so as to output a voltage-adjusting signal to the pressure-control oscillator; and the pressure-control oscillator is used for adjusting the clock frequency of the generated reference clock signal according to the voltage-adjusting signal so as to lock the clock frequency of the lock-phase ring clock signal generated by the lock-phase ring unit to the basic frequency of the clock signal of the input data stream.

Description

Produce method and the data receiving-transmitting system of reference clock signal

Technical field

The present invention relates to a kind of data receiving-transmitting system, relate in particular to a kind of method and data receiving-transmitting system that produces reference clock signal.

Background technology

Fig. 1 is data collector (transceiver) framework of existing integrated chip (integrated chip).Wherein, data collector 100 comprises phase locked-loop unit (Phase Lock Loop, PLL) 110, data transmitter (Transmitter, TX) 120, there is clock and data recovery (Clock Data Recovery, CDR) data sink (Receiver, RX) 130 pieces such as front-end circuit such as grade of function.This integrated chip also utilizes a quartz (crystal) device 140 to produce the accurately clock signal of (differing tens of ppm with target frequency) of frequency, the reference clock when as its transceiving data.In detail, phase locked-loop unit 110 can be used this reference clock as input, and the pll clock output that produces the multiple that frequency is reference clock frequency.This pll clock is used as the reference clock of clock and data recovery, and in order to produce the data flow of reclocking (retimed).The clock output producing when above-mentioned clock and data recovery is the fundamental frequency based on received input traffic and producing.In addition, above-mentioned pll clock also can be used as signal source of clock, and in order to send data flow (there is no accompanying clock signal originally).

The accuracy (accuracy) of the reference frequency of above-mentioned pll clock is considerable in serial data transmission (serial datatransmission), and only can allow quite little frequency error.In detail, this frequency error must meet the specification of given standard, is generally admissible maximum bit error rate (Bit ErrorRate, BER).For example, at USB (Universal Serial Bus, USB), in 2.0 fast mode (High-Speed Mode, HS Mode), the accuracy of required pll clock frequency is the positive and negative 500ppm of the fundamental frequency of reception (RX) data flow.Although commercial quartz devices can produce the clock signal of frequency error lower than positive and negative 100ppm, and can be used as desirable signal source of clock, this quartz devices expensive, and can occupy larger circuit board space.

Summary of the invention

The invention provides a kind of method and data receiving-transmitting system that produces reference clock signal, can produce frequency reference clock signal accurately, and in order to transceiving data.

The present invention proposes a kind of data receiving-transmitting system that produces reference clock signal, and it comprises voltage controlled oscillator, phase locked-loop unit and data sink.Wherein, voltage controlled oscillator is to produce reference clock signal.Phase locked-loop unit is to connect voltage controlled oscillator, and in order to increase the clock frequency of reference clock signal, to produce pll clock signal.Data sink is to connect phase locked-loop unit and voltage controlled oscillator, in order to receive input traffic and pll clock signal, and by the pll clock signal clock signal comparison of input traffic therewith, adjust signal to voltage controlled oscillator with output voltage, wherein voltage controlled oscillator is the clock frequency of the reference clock signal that adjustment produces according to voltage adjustment signal, the clock frequency of the pll clock signal of phase locked-loop unit generation is locked to the fundamental frequency of the clock signal of input traffic.

In one embodiment of this invention, above-mentioned data sink comprises frequency detector and frequency locking controller.Wherein, frequency detector is to receive input traffic, and by the fundamental frequency comparison of the clock signal of the clock frequency of pll clock signal and input traffic, to produce frequency adjusted signal.Frequency locking controller is to adjust signal and pll clock signal in order to receive frequency, to produce voltage adjustment signal.

In one embodiment of this invention, above-mentioned frequency detector is in the time that the fundamental frequency of the clock signal of input traffic is greater than the clock frequency of pll clock signal, the frequency adjusted signal that output logic is high; And in the time that the fundamental frequency of the clock signal of input traffic is less than the clock frequency of pll clock signal, the frequency adjusted signal that output logic is low.

In one embodiment of this invention, above-mentioned frequency locking controller is in the time receiving the high frequency adjusted signal of logic, heightens the numerical value of voltage adjustment signal, improves the clock frequency of reference clock signal to control voltage controlled oscillator; And in the time receiving the frequency adjusted signal of logic low, turn down the numerical value of voltage adjustment signal, reduce the clock frequency of reference clock signal to control voltage controlled oscillator.

In one embodiment of this invention, above-mentioned data sink comprises clock data recovery circuit, start frame decoder and frequency locking controller.Wherein, clock data recovery circuit is to receive input traffic and pll clock signal, and uses this pll clock signal as with reference to clock, with by the input traffic being received for chronometric data stream again.Start frame decoder is the start frame of finding out each frame in multiple frames of reclocking data flow, to produce a start frame signal.Frequency locking controller is to receive these start frame signal and pll clock signals that start frame decoder produces, and utilizes pll clock signal to count these start frame signals, to produce voltage adjustment signal.

In one embodiment of this invention, above-mentioned frequency locking controller comprises the number of counted start frame signal and standard value comparison, and in the time that this number is less than standard value, heighten the numerical value of voltage adjustment signal, improve the clock frequency of reference clock signal to control voltage controlled oscillator; Otherwise, in the time that this number is greater than standard value, turn down the numerical value of voltage adjustment signal, reduce the clock frequency of reference clock signal to control voltage controlled oscillator.

In one embodiment of this invention, above-mentioned voltage controlled oscillator is according to voltage adjustment signal, the clock frequency of produced reference clock signal is improved or reduced a frequency class.Wherein, the frequency gain that described frequency class is voltage controlled oscillator and the product of voltage variety.

In one embodiment of this invention, above-mentioned data receiving-transmitting system also comprises digital analog converter, it is to be disposed between voltage controlled oscillator and data sink, and in order to the voltage adjustment signal of data sink output is converted to voltage variety, to adjust the clock signal of the reference clock signal that voltage controlled oscillator produced.

In one embodiment of this invention, above-mentioned data receiving-transmitting system also comprises data transmitter, and it is to connect phase locked-loop unit, and in order to receive output stream and pll clock signal, and send output stream according to this pll clock signal.

The present invention proposes a kind of method that produces reference clock signal, and it is to utilize voltage controlled oscillator to produce reference clock signal, and increases the clock frequency of this reference clock signal, to produce pll clock signal.Then, by the clock signal comparison of pll clock signal and input traffic, adjust signal with output voltage, the clock frequency of reference clock signal last that produce according to this voltage adjustment signal adjustment voltage controlled oscillator, to be locked to the clock frequency of the pll clock signal being produced the fundamental frequency of the clock signal of input traffic.

Based on above-mentioned, the method of generation reference clock signal of the present invention and data receiving-transmitting system are by configuring independently voltage controlled oscillator to produce reference clock signal in integrated chip, and the frequency that uses the clock signal of the input traffic that receives to proofread this reference clock signal.The result of this check and correction will feed back to voltage controlled oscillator, to adjust the clock frequency of the reference clock signal that voltage controlled oscillator was produced, make the clock frequency of the pll clock signal that phase locked-loop unit produces may be locked to the clock frequency of the clock signal of input traffic.Therefore, the present invention can, in the situation that not using quartz devices, obtain frequency pll clock signal accurately.

For above-mentioned feature and advantage of the present invention can be become apparent, special embodiment below, and coordinate accompanying drawing to be described in detail below.

Accompanying drawing explanation

Fig. 1 is the framework of the data collector of existing integrated chip.

Fig. 2 is the calcspar of the data receiving-transmitting system of the generation reference clock signal shown in first embodiment of the invention.

Fig. 3 is the example of the phase locked-loop unit shown in first embodiment of the invention.

Fig. 4 is the example of the phase locked-loop unit shown in first embodiment of the invention.

Fig. 5 is the calcspar of the data receiving-transmitting system of the generation reference clock signal shown in second embodiment of the invention.

Fig. 6 is the method flow diagram of the generation reference clock signal shown in second embodiment of the invention.

Fig. 7 is the calcspar of the data receiving-transmitting system of the generation reference clock signal shown in third embodiment of the invention.

Fig. 8 is the method flow diagram of the generation reference clock signal shown in third embodiment of the invention.

Fig. 9 is the oscillogram of the start frame token shown in third embodiment of the invention.

Main description of reference numerals:

100: data collector; 140: quartz devices;

110,220,300,400,520,720: phase locked-loop unit;

120,550,750: data transmitter; 910,920: start frame token;

130,230,530,730: data sink;

200,500,700: data receiving-transmitting system; 210,510,710: voltage controlled oscillator;

302: frequency comparator; 304: phase detectors;

306: frequency gain register; 308: phase gain register;

310: addition multiplexer; 312: subtraction multiplexer;

314: adder; 316: subtracter;

318: anchor register; 320: numerically-controlled oscillator;

322: digital control register; 324: controller;

402: phase-frequency detector; 404: charge pump;

406: ring wave filter; 408: voltage-controlled oscillator;

532: frequency detector; 534,736: frequency locking controller;

540,740: digital analog converter; 732: clock data recovery circuit;

734: start frame decoder; 900: input traffic;

S602~612: the step of the generation reference clock signal method of second embodiment of the invention;

S802~814: the step of the generation reference clock signal method of third embodiment of the invention.

Embodiment

The present invention replaces traditional quartz devices with a voltage controlled oscillator that is configured in integrated chip inside, and sends the required reference clock signal of data flow in order to produce.Wherein, because the variation in semiconductor technology, voltage and temperature (Process-Voltage-Temperature, PVT) all can increase the frequency error of signal that oscillator produces, oscillator cannot be used on serial data transceiver.Allow this oscillator be applied in integrated chip in order to compensate these factors for the impact of oscillator, the present invention adopts a set of reponse system, by the fundamental frequency that received data is flowed and phase locked-loop unit (Phase LockLoop, PLL) clock frequency comparison, to send frequency adjusted signal, to adjust the clock frequency of the reference clock signal that oscillator was produced, and then obtain frequency pll clock signal comparatively accurately.Illustrate that for embodiment the present invention produces the function mode of the data receiving-transmitting system of reference clock signal with next.

The first embodiment

Fig. 2 is the calcspar of the data receiving-transmitting system of the generation reference clock signal shown in first embodiment of the invention.Please refer to Fig. 2, the data receiving-transmitting system 200 of the present embodiment comprises voltage controlled oscillator 210, phase locked-loop unit 220 and data sink 230, and its function is described below:

Voltage controlled oscillator 210 is to produce reference clock signal, and it is for example a resistance/capacitance (RC) oscillator, ring-like (Ring) oscillator or inductance/capacitance (LC) oscillator, can produce reference clock signal.

Phase locked-loop unit 220 is to be connected to voltage controlled oscillator 210, and reference clock signal in order to utilize voltage controlled oscillator 210 to export, the pll clock signal of output one preset frequency and phase place.

In this exemplary embodiment, phase locked-loop unit 220 can be implemented in digital mode.For instance, Fig. 3 is the example of the phase locked-loop unit shown in first embodiment of the invention.Please refer to Fig. 3, phase locked-loop unit 300 can comprise frequency comparator (frequency comparator) 302, phase detectors (phasedetector) 304, frequency gain register (frequency gain register) 306, phase gain register (phase gain register) 308, addition multiplexer (adder MUX) 310, subtraction multiplexer (substrate MUX) 312, adder 314, subtracter 316, anchor register (anchorregister) 318, numerically-controlled oscillator (Digital Control Oscillator, DCO) 320, digital control register 322 and controller 324.

In another exemplary embodiment, phase locked-loop unit 220 also can be implemented in the mode of analog or digital analog mixed.For instance, Fig. 4 is the example of the phase locked-loop unit shown in first embodiment of the invention.Please refer to Fig. 4, phase locked-loop unit 400 comprises phase-frequency detector (phase frequency detector, PFD) 402, charge pump (charge pump, CP) 404, ring wave filter (loop filter, LP) 406, and voltage-controlled oscillator (voltage controlled oscillator, VCO) 408.Wherein, Fin is incoming frequency; Fout is output frequency; Vup is voltage rising signals; Vdn is voltage reduction signal; Vlp is voltage signal; Vcp is filtered voltage signal.In this article, because phase-locked loop is the familiar technology of those skilled in the art, therefore no longer add to repeat at this.

Data sink 230 is to connect phase locked-loop unit 220 and voltage controlled oscillator 210, transmit and the input traffic coming and the pll clock signal of being exported by phase locked-loop unit 220 in order to receive by outside, and by the pll clock signal clock signal comparison of input traffic therewith, to export a voltage adjustment signal to voltage controlled oscillator 210, adjust the clock frequency of its reference clock signal being produced to control voltage controlled oscillator.

In detail, voltage controlled oscillator 210 is for example the clock frequency of adjusting its reference clock signal producing according to voltage adjustment signal, and produce pll clock signal, data sink 130 comparison clock signals by repeating above-mentioned phase locked-loop unit 220, and voltage controlled oscillator 210 adjusts the step of clock frequency, the clock frequency of the pll clock signal that finally phase locked-loop unit 220 can be produced is locked to the fundamental frequency of the clock signal of input traffic.

It should be noted that, for the comparison of the clock signal of above-mentioned pll clock signal and input traffic, the invention provides two kinds of exemplary embodiment: a kind of be by the clock frequency of pll clock signal directly and the fundamental frequency of the clock signal of input traffic compare, to determine whether to increase and decrease the clock frequency of the reference clock signal that voltage controlled oscillator produced; Another kind of be the number of the start frame of multiple frames in data flow in the unit of account time, to determine whether to increase and decrease the clock frequency of the reference clock signal that voltage controlled oscillator produced.Below respectively describe in detail for an embodiment for above-mentioned two kinds of modes.

The second embodiment

Fig. 5 is the calcspar of the data receiving-transmitting system of the generation reference clock signal shown in second embodiment of the invention.Fig. 6 is the method flow diagram of the generation reference clock signal shown in second embodiment of the invention.Referring to Fig. 5 and Fig. 6, the data receiving-transmitting system 500 of the present embodiment comprises voltage controlled oscillator 510, phase locked-loop unit 520, data sink 530, digital analog converter 540 and data transmitter 550, and wherein data sink 530 also comprises frequency detector 532 and frequency locking controller 534.Even if the detailed step of reference clock signal production method of the present invention is described with above-mentioned each element below:

First, utilize voltage controlled oscillator 510 to produce reference clock signal (step S602).This voltage controlled oscillator 510 is for example a resistance/capacitance (RC) oscillator, ring-like (Ring) oscillator or inductance/capacitance (LC) oscillator, can produce reference clock signal.And the reference clock signal that now voltage controlled oscillator 510 produces is for example a predetermined value, and proofreaied and correct gradually by the circuit at rear.

Then, utilize phase locked-loop unit 520 to increase the clock frequency f (ref_n) of the reference clock signal of being exported by voltage controlled oscillator 510, and generation pll clock signal f (pll) (step S604), wherein f (pll)=M*f (ref_n), M is a numerical value that is greater than 1.

Then, by data sink 530 utilize frequency detector 532 receive by outside transmit and come input traffic and by phase locked-loop unit 520 transmit and come pll clock signal, and by the fundamental frequency comparison of the clock signal of input traffic therewith of the clock frequency of pll clock signal, to produce frequency adjusted signal (step S606).In detail, data sink 530 be utilize frequency detector 532 relatively the clock frequency of pll clock signals after the clock signal of input traffic, produce frequency adjusted signal therewith, therefore make the clock frequency of pll clock signal approach the clock signal of input traffic.Wherein, this frequency detector 532 can be a speed detector (Rotational Frequency Detector), wideband detector (Wide Range Frequency Detector), differential frequency detector (DifferentialFrequency Detector) or digital quadratic surface frequency detector (Digital QuadricorrelatorFrequency Detector).

In addition, in one embodiment, frequency detector 532 is for example in the time that the clock frequency of pll clock signal is less than the fundamental frequency of clock signal of input traffic, exports a frequency adjusted signal that logic is high, to heighten frequency; And in the time that the clock frequency of pll clock signal is greater than the fundamental frequency of clock signal of input traffic, the frequency adjusted signal of a logic low of output, to turn down frequency.In addition, in another embodiment, frequency detector 532 is for example to reduce signal by output one class frequency increase signal and frequency to adjust frequency, wherein in the time that the clock frequency of pll clock signal is less than the fundamental frequency of clock signal of input traffic, the frequency that exporting a high frequency of logic increases signal and a logic low reduces signal, to heighten frequency; In the time that the clock frequency of pll clock signal is greater than the fundamental frequency of clock signal of input traffic, the frequency of a logic low of output increases signal and a high frequency of logic reduces signal, to turn down frequency.But the invention is not restricted to above-mentioned two kinds of modes.

Above-mentioned frequency adjusted signal is to export frequency locking controller 534 to, and frequency locking controller 534 is except receiving this frequency adjusted signal, also receive the pll clock signal being produced by phase locked-loop unit 520, and according to this frequency adjusted signal and pll clock signal, produce voltage adjustment signal (step S608).

In detail, frequency locking controller 534 is for example in the time receiving the high frequency adjusted signal of the logic exported by frequency detector 532, heightens the numerical value of voltage adjustment signal, improves the clock frequency of reference clock signal to control voltage controlled oscillator 510; And in the time receiving the frequency adjusted signal of the logic low of being exported by frequency detector 532, turn down the numerical value of voltage adjustment signal, reduce the clock frequency of reference clock signal to control voltage controlled oscillator 510.

For instance, as shown in Figure 5, frequency locking controller 534 for example can produce the voltage adjustment signal FREQ_D of a N position, and the frequency adjusted signal of exporting according to frequency detector 532 increases or reduce the numerical value of this voltage adjustment signal FREQ_D.

The voltage adjustment signal FREQ_D of this N position then can be sent to digital analog converter 540, and be converted to the voltage variety VA (step S610) of simulation by digital analog converter 540, and can be in order to adjust the clock frequency of the reference clock signal that voltage controlled oscillator 510 produces.

In detail, voltage controlled oscillator 510 is the voltage variety VA that export according to digital analog converter 540, the clock frequency of the reference clock signal that it is produced improves or reduces a frequency class, and exports the reference clock signal (step S612) after adjusting.Above-mentioned frequency class is for example the frequency gain Kf of voltage controlled oscillator 510 and the product of voltage variety VA, and being former clock frequency f (ref_t_n-1), the clock frequency f (ref_t_n) of reference clock signal after above-mentioned adjustment adds the product of frequency gain Kf and voltage variety VA, i.e. f (ref_t_n)=f (ref_t_n-1)+Kf*VA.

Reference clock signal after above-mentioned adjustment can be inputted phase locked-loop unit 520, and the clock frequency of reference clock signal after increasing this and adjust by phase locked-loop unit 520 again, to produce pll clock signal (step S604), and produce pll clock signal by repeating above-mentioned phase locked-loop unit 520, data sink 530 comparison clock signals, digital analog converter 540 changing voltages are adjusted signal, and voltage controlled oscillator 510 is adjusted the step of clock frequency, the clock frequency of the pll clock signal that finally phase locked-loop unit 520 can be produced is locked to the fundamental frequency of the clock signal of input traffic, make this pll clock signal can be used as frequency signal source of clock comparatively accurately, and offer data transmitter 550 to send output stream.

In detail, data transmitter 550 is to be connected to phase locked-loop unit 520, and the pll clock signal that can receive output stream and be produced by phase locked-loop unit 520, and sends output stream according to this pll clock signal.

By above-mentioned feedback mechanism, the clock frequency of the pll clock signal that the phase locked-loop unit 520 of the present embodiment can produce it is locked to fundamental frequency or the one prearranged multiple of the clock signal of input traffic, therefore can be by the frequency error reduction (as 100ppm) of pll clock signal, and then replace traditional quartz devices, and as the derived reference signal of integrated chip inside.

The 3rd embodiment

On the other hand, the present invention also can utilize USB (Universal Serial Bus, USB) defined start frame (Start-of-Frame in 2.0 specifications, SOF) token (Token), carry out the clock signal of comparison pll clock signal and input traffic, to adjust the clock frequency of the reference clock signal that voltage controlled oscillator produced.

Fig. 7 is the calcspar of the data receiving-transmitting system of the generation reference clock signal shown in third embodiment of the invention.Fig. 8 is the method flow diagram of the generation reference clock signal shown in third embodiment of the invention.Referring to Fig. 7 and Fig. 8, the data receiving-transmitting system 700 of the present embodiment comprises voltage controlled oscillator 710, phase locked-loop unit 720, data sink 730, digital analog converter 740 and data transmitter 750, and wherein data sink 730 also comprises clock data recovery circuit 732, start frame decoder 734 and frequency locking controller 736.The function of above-mentioned each element is described below:

First, utilize voltage controlled oscillator 710 to produce reference clock signal f (ref_tn) (step S802), and phase locked-loop unit 720 is to be connected to voltage controlled oscillator 710, and in order to increase the clock frequency of the reference clock signal of being exported by voltage controlled oscillator 710, to produce pll clock signal (step S804).Wherein, voltage controlled oscillator 710 and the function of phase locked-loop unit 720 be with the second embodiment in voltage controlled oscillator 510 identical with phase locked-loop unit 520, do not repeat them here.

Different from the second embodiment is, the data receiving-transmitting system 700 of the present embodiment is to utilize clock data recovery circuit (clock and data recovery circuit) 732 to receive by outside to transmit and the input traffic coming and the pll clock signal being produced by phase locked-loop unit 720, and use this pll clock signal as with reference to clock, received input traffic is converted to reclocking (Retimed) data flow (step S806).Wherein in this exemplary embodiment, clock data recovery circuit 732 can be oversampling data recovery circuit (oversampling data recovery circuit), but in another exemplary embodiment, it also can be burst clock and data recovery circuit (burst-mode clock and data recoverycircuit) or other types in order to receiving the clock of data and the circuit that data restore.

Then, found out the start frame of each frame in multiple frames of this reclocking data flow by start frame decoder 734, and produce start frame signal (step S808).In detail, external USB device or usb hub (Hub) produce or when transmitting data stream, can add a start frame token in the packet front of each frame, for the starting point of each frame of data sink interpretation under fast mode.

For instance, Fig. 9 is the oscillogram of the start frame token shown in third embodiment of the invention.Wherein, Fig. 9 illustrates frame N and the frame N-1 in input traffic 900, and in the front of the packet of these two frames, can add respectively start frame token 910,920, for data sink interpretation frame N and frame N-1.Wherein, in this exemplary embodiment, can be according to the specification of USB 2.0, between start frame token 910,920, be spaced apart 125 microseconds (micro-second), and error range is positive and negative 500ppm, but this interval also can be 225 microseconds or sets according to different specifications, not as limit.

The present embodiment receives the start frame signal being produced by start frame decoder 734 and the pll clock signal being produced by phase locked-loop unit 720 by frequency locking controller 736, and utilize this pll clock signal to count start frame signal, to produce voltage adjustment signal (step S810).

In detail, frequency locking controller 736 is for example number and a standard value comparison of start frame signal that it is counted, and in the time that this number is less than standard value, heighten the numerical value of voltage adjustment signal, improve the clock frequency of reference clock signal to control voltage controlled oscillator 710; Otherwise, in the time that this number is greater than standard value, turn down the numerical value of voltage adjustment signal, reduce the clock frequency of reference clock signal to control voltage controlled oscillator 710.

For instance, the clock frequency of tentative standard pll clock signal is 480 megahertzes (MHz), and is spaced apart 125 microseconds between start frame token, and the counting of the start frame token within a phase locked-loop unit clock cycle should be 60000.But, under actual state, if the clock frequency of pll clock signal is less than 480MHz, the counting of the start frame token within a phase locked-loop unit clock cycle will be less than 60000, now frequency locking controller need be by the numerical value of heightening voltage adjustment signal, and control voltage controlled oscillator and improve the clock frequency of reference clock signal; Otherwise, if the clock frequency of pll clock signal is greater than 480MHz, the counting of the start frame token within a phase locked-loop unit clock cycle will be greater than 60000, now frequency locking controller need be by the numerical value of turning down voltage adjustment signal, and control voltage controlled oscillator and reduce the clock frequency of reference clock signal.By above-mentioned adjustment mode, the 480MHz that finally can make the clock frequency of pll clock signal level off under standard state.

In addition, described in the second embodiment, the frequency locking controller 736 of the present embodiment for example can produce the voltage adjustment signal FREQ_D of a N position, and the frequency adjusted signal of exporting according to frequency detector 532 increases and decreases the numerical value of this voltage adjustment signal FREQ_D.Then, by digital analog converter 740, this voltage adjustment signal FREQ_D is converted to the voltage variety VA (step S812) of simulation, and adjusts the clock frequency (step S814) of its reference clock signal producing in order to control voltage controlled oscillator 510.Detailed adjustment mode please refer to the second embodiment, does not repeat them here.

Reference clock signal after above-mentioned adjustment can be inputted phase locked-loop unit 720, and the clock frequency of reference clock signal after increasing this and adjust by phase locked-loop unit 720 again, to produce pll clock signal (step S804), and produce pll clock signal by repeating above-mentioned phase locked-loop unit 720, data sink 730 comparison clock signals, digital analog converter 740 changing voltages are adjusted signal, and voltage controlled oscillator 710 is adjusted the step of clock frequency, the clock frequency of the pll clock signal that finally phase locked-loop unit 720 can be produced is locked to the fundamental frequency of the clock signal of input traffic, make this pll clock signal can be used as frequency signal source of clock accurately, and offer data transmitter 750 to send output stream.

It should be noted that, the framework of above-mentioned the second embodiment and the 3rd embodiment also can be incorporated in same data receiving-transmitting system, and can be by detecting start frame to determine adopting which kind of mode to adjust.Wherein, in the time detecting start frame, adopt the path of clock data recovery circuit, the number of the start frame of multiple frames in data flow in the unit of account time, to determine whether to increase and decrease the clock frequency of the reference clock signal that voltage controlled oscillator produced; Otherwise, the path of proportion detector, by the clock frequency of pll clock signal directly and the fundamental frequency of the clock signal of input traffic compare, to determine whether to increase and decrease the clock frequency of the reference clock signal that voltage controlled oscillator produced.

In sum, the method of generation reference clock signal of the present invention and data receiving-transmitting system are the clock signal comparisons by the pll clock signal that phase locked-loop unit is produced and input traffic, to judge that whether pll clock signal is accurate, and by feedback mechanism, judged result is fed back to and produces the voltage controlled oscillator of reference clock signal, the clock frequency of the reference clock signal being produced to adjust.Via comparison, feedback and set-up procedure repeatedly, finally the clock frequency of pll clock signal can be locked to the fundamental frequency of the clock signal of input traffic, and the frequency error of pll clock signal is met standard requirements.Accordingly, the present invention can replace traditional quartz devices by a configurable voltage controlled oscillator in integrated chip, and reduces the cost of manufacture of integrated chip.

Although the present invention discloses as above with embodiment; but it is not in order to limit the present invention; technical field technical staff under any; without departing from the spirit and scope of the present invention; can change arbitrarily or be equal to replacement, being as the criterion therefore protection scope of the present invention is worked as the scope being defined with the application's claim.

Claims (16)

1. a data receiving-transmitting system that produces reference clock signal, comprising:
One voltage controlled oscillator, in order to produce a reference clock signal;
One phase locked-loop unit, connects this voltage controlled oscillator, in order to increase a clock frequency of this reference clock signal, to produce a pll clock signal;
And
One data sink, connect this phase locked-loop unit and this voltage controlled oscillator, in order to receive an input traffic and this pll clock signal, and by a clock signal comparison of this pll clock signal and this input traffic, to export a voltage adjustment signal to this voltage controlled oscillator, this data sink comprises:
One frequency detector, in order to receive this input traffic, and a fundamental frequency of this clock frequency of this pll clock signal and this clock signal of this input traffic relatively, to produce a frequency adjusted signal;
One clock data recovery circuit, receives this input traffic and this pll clock signal, and uses this pll clock signal as with reference to clock, and this input traffic being received to change is a reclocking data flow;
One initial frame decoder, detects and finds out a start frame of each frame in multiple frames of this reclocking data flow, to produce an initial frame signal;
And
One frequency locking controller, in the time that this start frame decoder does not detect this start frame, receive this frequency adjusted signal and this pll clock signal, to produce this voltage adjustment signal, in the time that this start frame decoder detects this start frame, receive described start frame signal and this pll clock signal that this start frame decoder produces, and utilize this pll clock signal to count described start frame signal, to produce this voltage adjustment signal, wherein
The clock frequency of this reference clock signal that this voltage controlled oscillator produces according to this voltage adjustment signal adjustment, to be locked to the clock frequency of this pll clock signal of this phase locked-loop unit generation this fundamental frequency of this clock signal of this input traffic.
2. data receiving-transmitting system according to claim 1, wherein
In the time that this fundamental frequency of this clock signal of this input traffic is greater than the clock frequency of this pll clock signal, this frequency detector is exported this frequency adjusted signal that a logic is high;
And
In the time that this fundamental frequency of this clock signal of this input traffic is less than the clock frequency of this pll clock signal, this frequency detector is exported this frequency adjusted signal of a logic low.
3. data receiving-transmitting system according to claim 2, wherein
In the time receiving high this frequency adjusted signal of this logic, this frequency locking controller is heightened a numerical value of this voltage adjustment signal, improves the clock frequency of this reference clock signal to control this voltage controlled oscillator;
And
In the time receiving this frequency adjusted signal of this logic low, this frequency locking controller is turned down this numerical value of this voltage adjustment signal, reduces the clock frequency of this reference clock signal to control this voltage controlled oscillator.
4. data receiving-transmitting system according to claim 3, wherein this frequency locking controller is by a number of counted described start frame signal and a standard value comparison, wherein
In the time that this number is less than this standard value, heighten a numerical value of this voltage adjustment signal, improve the clock frequency of this reference clock signal to control this voltage controlled oscillator;
And
In the time that this number is greater than this standard value, turn down this numerical value of this voltage adjustment signal, reduce the clock frequency of this reference clock signal to control this voltage controlled oscillator.
5. data receiving-transmitting system according to claim 1, wherein this voltage controlled oscillator comprises according to this voltage adjustment signal, the clock frequency of this produced reference clock signal is improved or reduced a frequency class.
6. data receiving-transmitting system according to claim 5, the frequency gain that wherein this frequency class is this voltage controlled oscillator and the product of a voltage variety.
7. data receiving-transmitting system according to claim 6, also comprises:
One digital analog converter, is disposed between this voltage controlled oscillator and this data sink, and this voltage adjustment signal of changing the output of this data sink is this voltage variety, to adjust the clock frequency of this reference clock signal that this voltage controlled oscillator produced.
8. data receiving-transmitting system according to claim 1, also comprises:
One data transmitter, connects this phase locked-loop unit, receives an output stream and this pll clock signal, and sends this output stream according to this pll clock signal.
9. a method that produces reference clock signal, comprises the following steps:
Utilize a voltage controlled oscillator to produce a reference clock signal;
Increase a clock frequency of this reference clock signal, to produce a pll clock signal;
By a clock signal comparison of this pll clock signal and an input traffic, to export a voltage adjustment signal, comprising:
Receive this input traffic, and a fundamental frequency of this clock frequency of this pll clock signal and this clock signal of this input traffic relatively, to produce a frequency adjusted signal;
Receive this input traffic and this pll clock signal, and use this pll clock signal as with reference to clock, this input traffic being received to change is a reclocking data flow;
Detect and find out a start frame of each frame in multiple frames of this reclocking data flow, to produce an initial frame signal;
And
In the time not detecting this start frame, receive this frequency adjusted signal and this pll clock signal, to produce this voltage adjustment signal, in the time detecting this start frame, receive described start frame signal and this pll clock signal, and utilize this pll clock signal to count described start frame signal, to produce this voltage adjustment signal;
And
Adjust the clock frequency of this reference clock signal that this voltage controlled oscillator produces according to this voltage adjustment signal, the clock frequency of this pll clock signal being produced is locked to this fundamental frequency of this clock signal of this input traffic.
10. method according to claim 9, wherein this fundamental frequency of the clock frequency of this pll clock signal and this clock signal of this input traffic relatively, comprises with the step that produces this frequency adjusted signal:
In the time that this fundamental frequency of this clock signal of this input traffic is greater than the clock frequency of this pll clock signal, this high frequency adjusted signal of output one logic;
And
In the time that this fundamental frequency of this clock signal of this input traffic is less than the clock frequency of this pll clock signal, this frequency adjusted signal of output one logic low.
11. methods according to claim 10, wherein receive this frequency adjusted signal and this pll clock signal, comprise with the step that produces this voltage adjustment signal:
In the time receiving high this frequency adjusted signal of this logic, heighten a numerical value of this voltage adjustment signal, improve the clock frequency of this reference clock signal to control this voltage controlled oscillator;
And
In the time receiving this frequency adjusted signal of this logic low, turn down this numerical value of this voltage adjustment signal, reduce the clock frequency of this reference clock signal to control this voltage controlled oscillator.
12. methods according to claim 11, wherein utilize this pll clock signal to count described start frame signal, comprise with the step that produces this voltage adjustment signal:
By a number of counted described start frame signal and a standard value comparison;
In the time that this number is less than this standard value, heighten a numerical value of this voltage adjustment signal, improve the clock frequency of this reference clock signal to control this voltage controlled oscillator;
And
In the time that this number is greater than this standard value, turn down this numerical value of this voltage adjustment signal, reduce the clock frequency of this reference clock signal to control this voltage controlled oscillator.
13. methods according to claim 9, wherein comprise according to the step that this voltage adjustment signal is adjusted the clock frequency of this reference clock signal that this voltage controlled oscillator produces:
According to this voltage adjustment signal, the clock frequency of this reference clock signal that this voltage controlled oscillator is produced improves or reduces a frequency class.
14. methods according to claim 13, the frequency gain that wherein this frequency class is this voltage controlled oscillator and the product of a voltage variety.
15. methods according to claim 14, wherein by this clock signal comparison of this pll clock signal and this input traffic, after exporting the step of this voltage adjustment signal, also comprise:
Changing this voltage adjustment signal is this voltage variety, to adjust the clock frequency of this reference clock signal that this voltage controlled oscillator produced.
16. methods according to claim 9, wherein in the clock frequency of adjusting this reference clock signal that this voltage controlled oscillator produces according to this voltage adjustment signal, after the clock frequency of this pll clock signal being produced being locked to the step of this fundamental frequency of this clock signal of this input traffic, also comprise:
Send an output stream according to this pll clock signal.
CN201010220056.XA 2010-07-01 2010-07-01 Method for generating reference clock signal and data receiving and transmitting system CN102315849B (en)

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