CN104009756A - Clock pulse data recovery circuit module and data recovery clock pulse generation method - Google Patents
Clock pulse data recovery circuit module and data recovery clock pulse generation method Download PDFInfo
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- CN104009756A CN104009756A CN201310061480.8A CN201310061480A CN104009756A CN 104009756 A CN104009756 A CN 104009756A CN 201310061480 A CN201310061480 A CN 201310061480A CN 104009756 A CN104009756 A CN 104009756A
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Abstract
The invention provides a clock pulse data recovery circuit module. The clock pulse data recovery circuit module comprises a clock pulse data recovery circuit, a frequency comparison circuit and a signal detection circuit. The clock pulse data recovery circuit is used for outputting data recovery string flows and data recovery clock pulses according to input signals and clock pulse signals. The frequency comparison circuit is coupled to the clock pulse data recovery circuit. The frequency comparison circuit is used for comparing a frequency difference between the data recovery clock pulses and the clock pulse signals so as to adjust the frequency of the clock pulse signals according to a comparison result. The signal detection circuit is used for receiving and detecting the input signal and deciding whether to start the frequency comparison circuit according to a detection result. Besides, the invention also brings forward a data recovery clock pulse generation method.
Description
Technical field
The invention relates to a kind of data processing circuit and signal generating method, and particularly relevant for a kind of clock pulse data restore circuit module and data recovered clock method for generating pulse.
Background technology
Generally speaking, at the signal receiving end of data transmission interface, conventionally understand configurable clock generator pulse data restore circuit, it can recover received input signal according to the pulse of data recovered clock, and produces (retimed) data crossfire of reclocking.In some specific specification, for guaranteeing the accuracy of the data that clock pulse data restore circuit recovers, the shake (jitter) of the data crossfire of reclocking can not be excessive.Therefore,, at signal receiving end, the oscillator that collocation phase-locked loop is used is crystal oscillator normally, to meet the requirement of accuracy.The frequency of the pulse reference clock that this crystal oscillator produces must be less than within the scope of certain compared to the error of the frequency of input signal.With third generation USB (Universal Serial Bus3.0; USB3.0) specification is example, and the error between the frequency of pulse reference clock and the frequency of input signal must be less than 300ppm (note: a ppm equal 1,000,000/).Although commercial crystal oscillator can produce frequency error lower than the clock pulse signal of positive and negative 100ppm, and can be used as desirable clock pulse signal source, this crystal oscillator expensive, and can occupy larger circuit board space.
In order to save cost and circuit board space, prior art has proposed to utilize the mode of automatic tracing (auto-tracking) data recovered clock pulse frequency that the pulse reference clock that phase-locked loop accuracy is high is provided.Yet, this kind of mode establishes a communications link at USB in the process of (link), or when low-power mode (low power mode) operates, if still continue the pulse of trace data recovered clock, the accuracy of pulse reference clock frequency will easily be reduced.
Summary of the invention
The invention provides a kind of clock pulse data restore circuit module, capable of dynamic determines whether to carry out frequency tracking (tracking).
The invention provides a kind of data recovered clock method for generating pulse, can determine whether producing the pulse of data recovered clock according to input signal.
The invention provides a kind of clock pulse data restore circuit module, comprise a clock pulse data recovery circuit, a frequency comparison circuit and a signal deteching circuit.Clock pulse data restore circuit is in order to export data recovery crossfire and a data recovered clock pulse according to an input signal and a clock pulse signal.Frequency comparison circuit is coupled to clock pulse data restore circuit.Frequency comparison circuit is in order to the frequency-splitting between the pulse of comparing data recovered clock and clock pulse signal, to adjust the frequency of clock pulse signal according to a comparative result.Signal deteching circuit is coupled to frequency comparison circuit.Signal deteching circuit is in order to receive and to detect input signal, and determines whether starting frequency comparison circuit according to testing result.
In an embodiment of the present invention, above-mentioned signal deteching circuit comprises a first frequency detecting unit and a second frequency detecting unit.Whether first frequency detecting unit comprises the data of a first frequency in order to receive and to detect input signal.Whether second frequency detecting unit comprises that in order to receive and to detect input signal one is not less than the data of a second frequency.Second frequency is greater than first frequency.
In an embodiment of the present invention, when signal deteching circuit detects input signal and comprises the data that are not less than second frequency, start frequency comparison circuit.
In an embodiment of the present invention, when signal deteching circuit detects input signal and comprises the data of first frequency, do not start frequency comparison circuit.
In an embodiment of the present invention, above-mentioned input signal comprises an electrical idle state.When signal deteching circuit detects input signal in electrical idle state, do not start frequency comparison circuit.
In an embodiment of the present invention, above-mentioned clock pulse data restore circuit comprises a clock pulse restore circuit and a data recovery circuit.Clock pulse restore circuit is in order to produce the pulse of data recovered clock according to input signal and clock pulse signal.Data recovery circuit recovers crossfire in order to produce data according to input signal.
In an embodiment of the present invention, above-mentioned clock pulse restore circuit comprises a clock pulse generating circuit and a frequency generating circuit.Clock pulse generating circuit is coupled to frequency generating circuit.Clock pulse generating circuit is in order to produce the pulse of data recovered clock according to input signal and clock pulse signal.Frequency generating circuit is coupled to frequency comparison circuit.Frequency generating circuit is in order to produce clock pulse signal according to a pulse reference clock.Frequency comparison circuit is exported a control signal according to comparative result, produces the frequency of the clock pulse signal that circuit was produced to adjust frequency.
In an embodiment of the present invention, above-mentioned frequency generating circuit comprises that a phase-locked loop circuit and a pulse reference clock produce circuit.Phase-locked loop circuit is coupled to frequency comparison circuit.Phase-locked loop circuit is controlled by control signal, in order to produce clock pulse signal according to control signal and pulse reference clock.Pulse reference clock produces circuit and is coupled to phase-locked loop circuit.Pulse reference clock produces circuit in order to produce and to export pulse reference clock.
In an embodiment of the present invention, above-mentioned clock pulse data restore circuit output data are recovered crossfire and data recovered clock pulse to data processing block.Data processing block comprises a buffer storage circuit and a decoder circuit.Decoder circuit recovers crossfire in order to decoded data.Buffer storage circuit is in order to data recovery storage crossfire.Frequency comparison circuit is coupled to buffer storage circuit.When frequency comparison circuit is activated, buffer storage circuit output data are recovered crossfire to decoder circuit.
In an embodiment of the present invention, above-mentioned clock pulse data restore circuit module also comprises a proof scheme.Proof scheme is coupled to decoder circuit, in order to checking, through the data of decoder circuit decoding, recover crossfire, and surpass after a threshold value in the error bit of finding data recovery crossfire, suspend the operation of the frequency-splitting between frequency comparison circuit comparing data recovered clock pulse and clock pulse signal.
The invention provides a kind of data recovered clock method for generating pulse, comprise the steps.Detect an input signal, to determine whether the frequency-splitting between comparison one data recovered clock pulse and a clock pulse signal according to testing result.Frequency-splitting between the pulse of comparing data recovered clock and clock pulse signal.According to the comparative result of the pulse of data recovered clock and clock pulse signal, adjust the frequency of clock pulse signal.
In an embodiment of the present invention, above-mentioned data recovered clock method for generating pulse also comprises the steps.According to input signal and clock pulse signal produce the pulse of data recovered clock and data recover crossfire at least one of them.
In an embodiment of the present invention, the step of above-mentioned detection input signal comprises the steps.Detect the data whether input signal comprises a first frequency.Detect input signal and whether comprise that one is not less than the data of a second frequency.Second frequency is greater than first frequency.
In an embodiment of the present invention, when input signal being detected and comprise the data that are not less than second frequency, carry out the step of the frequency-splitting between comparing data recovered clock pulse and clock pulse signal.
In an embodiment of the present invention, when input signal being detected and comprise the data of first frequency, do not carry out the step of the frequency-splitting between the pulse of comparing data recovered clock and clock pulse signal.
In an embodiment of the present invention, above-mentioned input signal comprises an electrical idle state.The step that detects input signal comprises that whether detection input signal is in electrical idle state.When input signal being detected in electrical idle state, do not carry out the step that comparing data is recovered the frequency-splitting between crossfire and clock pulse signal.
In an embodiment of the present invention, above-mentioned data recovered clock method for generating pulse also comprises according to a pulse reference clock and produces clock pulse signal.The step of adjusting the frequency of clock pulse signal comprises according to comparative result exports a control signal, to adjust the frequency of clock pulse signal.
In an embodiment of the present invention, above-mentioned data recovered clock method for generating pulse also comprises the steps.Decoded data recovers crossfire.Checking recovers crossfire through the data of decoding, and surpasses after a threshold value in the error bit number of data recovery crossfire, suspends the frequency-splitting between comparing data recovered clock pulse and clock pulse signal.
Based on above-mentioned, in exemplary embodiment of the present invention, the echo signal whether signal deteching circuit meeting basis detects input signal does not start or starts frequency comparison circuit, so capable of dynamic determines whether will carry out the operation of frequency tracking.
For above-mentioned feature and advantage of the present invention can be become apparent, special embodiment below, and coordinate accompanying drawing to be described in detail below.
Accompanying drawing explanation
Figure 1A illustrates the summary calcspar of the clock pulse data restore circuit module of the present invention's one exemplary embodiment;
Figure 1B illustrates the summary calcspar of signal receiving end of the memory storage apparatus of the present invention's one exemplary embodiment;
Fig. 2 and Fig. 3 illustrate respectively the summary oscillogram of the input signal of the different exemplary embodiment of the present invention;
Fig. 4 illustrates the summary calcspar of signal receiving end of the memory storage apparatus of another exemplary embodiment of the present invention;
Fig. 5 illustrates the outline flowchart of the data recovered clock method for generating pulse of the present invention's one exemplary embodiment;
Fig. 6 illustrates the outline flowchart of the data recovered clock method for generating pulse of another exemplary embodiment of the present invention.
Description of reference numerals:
10: data receiver block;
20: data processing block;
22: transformation from serial to parallel circuit;
24: buffer storage circuit;
26: decoder circuit;
100,400: clock pulse data restore circuit module;
110,410: clock pulse data restore circuit;
112,412: clock pulse restore circuit;
118,418: data recovery circuit;
120,420: frequency comparison circuit;
130,430: signal deteching circuit;
132: first frequency detecting unit;
134: second frequency detecting unit;
140: proof scheme;
413: phase-locked loop circuit;
414: frequency generating circuit;
415: pulse reference clock produces circuit;
416: clock pulse generating circuit;
CLK: clock pulse signal;
CLK_REF: pulse reference clock;
CDR_CLK: data recovered clock pulse;
CDR_DATA: data are recovered crossfire;
LFPS: low frequency cycle signal;
DATA: data-signal;
IN_DATA: input signal;
EN: switching signal;
CTRL: control signal;
S500, S510, S520, S530, S600, S610, S620, S630, S640, S650, S660: method step.
Embodiment
Below propose a plurality of embodiment the present invention is described, yet the present invention is not limited only to illustrated a plurality of embodiment.And between embodiment, also allow suitable combination." coupling " word using in this case specification full text (comprising claim) can refer to any direct or indirect connection means.For example, if describe first device in literary composition, be coupled to the second device, should be construed as this first device and can be directly connected in this second device, or this first device can be connected to indirectly by other devices or certain connection means this second device.In addition, " signal " word can refer at least one electric current, voltage, electric charge, temperature, data or any other one or more signal.
Please refer to Figure 1A and 1B, Figure 1A illustrates the summary calcspar of the clock pulse data restore circuit module of the present invention's one exemplary embodiment, and Figure 1B illustrates the summary calcspar of signal receiving end of the memory storage apparatus of the present invention's one exemplary embodiment.The circuit framework of the signal receiving end of this exemplary embodiment comprises data receiver block 10 and data processing block 20.Generally speaking; when memory storage apparatus receives by data transmission interface the input signal IN_DATA transmitting from host computer system or other elements; conventionally can utilize data receiver block 10 first inputted input signal IN_DATA to be carried out to the synchronous processing of data; its object be mainly for make data-signal that input signal IN_DATA carries can with the operating clock impulsive synchronization of signal receiving end, with the data processing block 20 of avoiding rear end, produce mistake when the deal with data.
In this exemplary embodiment, data receiver block 10 comprises clock pulse data restore circuit module 100, uses so that the operating clock impulsive synchronization of the data-signal that input signal IN_DATA carries and signal receiving end.The clock pulse data restore circuit module 100 of this exemplary embodiment comprises clock pulse data restore circuit 110, frequency comparison circuit 120 and signal deteching circuit 130, as shown in Figure 1A.Figure 1B further discloses while being applied in data receiver block 10, the detailed execution mode of clock pulse data restore circuit module 100 inner each circuit blocks.Particularly, clock pulse data restore circuit 110, in order to produce data recovery crossfire CDR_DATA and data recovered clock pulse CDR_CLK according to input signal IN_DATA and inner clock pulse signal thereof, is exported to respectively data processing block 20 and frequency comparison circuit 120.In this example, clock pulse data restore circuit 110 comprises clock pulse data circuit 112 and data recovery circuit 118.Clock pulse data circuit 112 can carry out to input signal IN_DATA the operation of clock pulse recovery (clock recovery), so that data are recovered crossfire CDR_DATA and data recovered clock pulse CDR_CLK operates in comparatively correct frequency.
Frequency comparison circuit 120 is coupled to clock pulse data restore circuit 110.Frequency comparison circuit 120 is in order to the frequency-splitting between the clock pulse signal of comparing data recovery crossfire CDR_DATA and clock pulse restore circuit 112 inside, to adjust the frequency of clock pulse signal according to comparative result.In this example, clock pulse signal is for example by the phase-locked loop of clock pulse restore circuit 112 inside (phase lock loop, PLL) circuit blocks produces, and frequency comparison circuit 120 can utilize control signal CTRL to control PLL circuit blocks, to adjust the frequency of its clock pulse signal being produced.In another exemplary embodiment, the PLL circuit blocks of clock pulse restore circuit 112 inside can be also a circuit module that is independent of clock pulse data restore circuit 110.
Signal deteching circuit 130 is coupled to frequency comparison circuit 120.Signal deteching circuit 130 is in order to detect input signal IN_DATA, and according to testing result, determines whether starting frequency comparison circuit 120 and adjust with the frequency to clock pulse signal.In this example, signal deteching circuit 130 utilizes switching signal EN to come forbidden energy or enables frequency comparison circuit 120.
In this exemplary embodiment, input signal IN_DATA for example mainly can comprise the data of first frequency, the data that are not less than second frequency and electrical idle state.The described data that are not less than second frequency are the targets of following the trail of as frequency comparison circuit 120 in this exemplary embodiment.Therefore, when signal deteching circuit 130 detects the echo signal in input signal IN_DATA, can start frequency comparison circuit 120, so that its output control signal CTRL adjusts the frequency of clock pulse signal.Relative, what detect when signal deteching circuit 130 is the data of the first frequency in input signal IN_DATA, or input signal IN_DATA is when electrical idle state, frequency comparison circuit 120 be can not start, the data of the first frequency of avoiding input signal IN_DATA and the target that the input signal IN_DATA in electrical idle state follows the trail of as frequency comparison circuit 120 usingd.Wherein, in this exemplary embodiment, this first frequency is one to be less than the frequency of second frequency.
In this exemplary embodiment, signal deteching circuit 130 comprises first frequency detecting unit 132 and second frequency detecting unit 134, be coupled to each other, the data that whether comprise the data of first frequency and be not less than second frequency in order to receive and to detect input signal IN_DATA respectively.In this example, the data of first frequency are for example the low frequency cycle signal LFPS (low frequency period signal) of input signal IN_DATA, and first frequency detecting unit 132 can be the squelch detecting circuit (squelch detector) of low frequency.Second frequency composition is the data content of input signal IN_DATA for example, its echo signal when carrying out frequency tracking, and its frequency is generally 5 gigahertz (GHZ)s (Gigahertz, GHz).Therefore,, in this exemplary embodiment, second frequency is greater than first frequency.Second frequency detecting unit 134 can be high speed squelch detecting circuit, in order to detect input signal IN_DATA, whether comprises the data that are not less than second frequency.
On the other hand, after receiving input signal IN_DATA, data recovery crossfire CDR_DATA and data recovered clock pulse CDR_CLK, data recovery circuit 118 can carry out the operation of data recovery (data recovery) to data recovery crossfire CDR_DATA according to input signal IN_DATA and data recovered clock pulse CDR_CLK, and the data recovery crossfire CDR_DATA after processing is transferred to transformation from serial to parallel circuit 22.Then, transformation from serial to parallel circuit 22 exports the data recovery crossfire CDR_DATA that changes into parallel form 24 storages of to buffer storage circuit.Afterwards, data are recovered crossfire CDR_DATA and are exported decoder circuit 26 to again and decode.
In another exemplary embodiment, frequency comparison circuit 120 also can be controlled the accessing operation of buffer storage circuit 24.For example, frequency comparison circuit 120 can be controlled buffer storage circuit 24 and at signal deteching circuit 130, starts the rear just output of frequency comparison circuits 120 data and recover crossfire CDR_DATA and decode to decoder circuit 26.
In this exemplary embodiment, standard as the coffret of the input/output interface of described memory storage apparatus comprises Serial Advanced Technology Attachment (Serial Advanced Technology Attachment, SATA) standard, Institute of Electrical and Electric Engineers (Institute of Electrical and Electronic Engineers, IEEE) 1394 standards, interconnected (the Peripheral Component Interconnect Express of high-speed peripheral, PCI Express) standard, USB (Universal Serial Bus, USB) standard, safe digital (Secure Digital, SD) interface standard, memory stick (Memory Stick, MS) interface standard, multimedia storage card (Multi Media Card, MMC) interface standard, compact flash (Compact Flash, CF) interface standard, integrated form drives electrical interface (Integrated Device Electronics, IDE) standard or other applicable standards.
Fig. 2 and Fig. 3 illustrate respectively the summary oscillogram of the input signal of the different exemplary embodiment of the present invention.Please refer to Fig. 2 and Fig. 3, in this exemplary embodiment, take USB3.0 standard as example, input signal IN_DATA generally includes low frequency cycle signal LFPS (low frequency period signal), data-signal DATA and electrical idle state.Low frequency cycle signal LFPS has the data of first frequency in input signal IN_DATA, it can continuous or discrete mode be distributed in input signal IN_DATA, respectively as shown in Figures 2 and 3.Low frequency cycle signal LFPS is low frequency signal, its cycle approximately between 20 nanoseconds (nanosecond, ns) between 100ns.In this exemplary embodiment, data-signal DATA has the data of second frequency in input signal IN_DATA, frequency comparison circuit 120 is the echo signals when carrying out frequency tracking with data-signal DATA, and its frequency is generally 5 gigahertz (GHZ)s (Gigahertz, GHz).Therefore, when described memory storage apparatus is in the process of establishing of communication connection, or when low-power mode, input signal IN_DATA can comprise low frequency cycle signal LFPS and electrical idle state.The signal deteching circuit 130 of this exemplary embodiment can detect low frequency cycle signal LFPS and the electrical idle state of input signal IN_DATA, and utilizes switching signal EN to carry out temporarily not start frequency comparison circuit 120, the accuracy of following the trail of with sustain pulse frequency.
In this example, when switching signal EN is high level, in order to start frequency comparison circuit 120, otherwise, when switching signal EN is low level, in order to not start frequency comparison circuit 120, the present invention is not limited, in another exemplary embodiment, low level switching signal EN also can be in order to start frequency comparison circuit 120, and the switching signal EN of high level also can be in order to not start frequency comparison circuit 120.In addition,, in this exemplary embodiment, when frequency comparison circuit 120 is activated, signal deteching circuit 130 can be closed, temporarily to decommission.
In addition,, in this exemplary embodiment, clock pulse data restore circuit module 100 also comprises proof scheme 140.Proof scheme 140 also can be in order to suspend the running of frequency comparison circuit 120.Particularly, if after the check of the data empirical tests circuit 140 that decoder circuit 26 decodes, proof scheme 140 is found, when the error bit of the data recovery crossfire CDR_DATA of decoding surpasses a threshold value, now to can be considered data recovery crossfire CDR_DATA and suffer a noise jamming.Therefore,, in order to prevent original stabilized frequency drift of following the trail of rear gained, now proof scheme 140 also can suspend frequency comparison circuit 120, with this, maintain original clock pulse signal.
In addition, in the present invention's one exemplary embodiment, clock pulse data restore circuit module 100 can be applicable in wired connection communication system (wire-linked communication system), and input signal IN_DATA can be serial (serial) data crossfire, clock pulse data restore circuit module 100 can receive input signal IN_DATA by single channel.But the present invention is not as limit, and in another exemplary embodiment, clock pulse data restore circuit module 100 also can be applicable to a wireless communication system, and input signal IN_DATA also can be parallel data crossfire.
Please refer to Fig. 4, Fig. 4 illustrates the summary calcspar of signal receiving end of the memory storage apparatus of another exemplary embodiment of the present invention, and it further discloses the inside structure of clock pulse restore circuit 412.In this exemplary embodiment, clock pulse restore circuit 412 comprises clock pulse generating circuit 416 and frequency generating circuit 414.Frequency generating circuit 414 comprises that phase-locked loop circuit 413 and pulse reference clock produce circuit 415.Wherein, in this exemplary embodiment, pulse reference clock produces that circuit 415 can be Hartley oscillator (Hartley Oscillator), Colpitts oscillator (Colpitts Oscillator), clapp oscillator (Clapp Oscillator) oscillator, phaseshift oscillator, RC oscillator (RC Oscillator), LC oscillator (LC Oscillator) or other are not the oscillator of quartz (controlled) oscillator.Pulse reference clock produces circuit 415 and is coupled to phase-locked loop circuit 413.Pulse reference clock produces circuit 415 in order to produce and to export pulse reference clock CLK_REF to phase-locked loop circuit 413.Wherein, in this exemplary embodiment, because pulse reference clock produces circuit 415, be one not there is the oscillator of quartz (controlled) oscillator, therefore the clock pulse signal CLK that it provides is compared with inaccuracy, still need and utilize the data recovered clock pulse CDR_CLK that clock pulse generating circuit 416 obtains in input signal IN_DATA via frequency comparison circuit 420, it to be proofreaied and correct, then the more accurate clock pulse signal CLK of output voluntarily.So, even if clock pulse restore circuit 412 does not receive an input signal IN_DATA with data-signal DATA, also can the accurate clock pulse signal CLK of output.Phase-locked loop circuit 413 is coupled to frequency comparison circuit 420.Phase-locked loop circuit 413 is controlled by control signal CTRL in order to produce clock pulse signal CLK to clock pulse generating circuit 416 according to pulse reference clock CLK_REF.Clock pulse generating circuit 416 is coupled to frequency generating circuit 414.Clock pulse generating circuit 416 is in order to carry out the operation of clock pulse recovery, to produce data recovered clock pulse CDR_CLK to input signal IN_DATA according to clock pulse signal CLK.In this example, in order to make frequency comparison circuit 420 can carry out the operation of automatic frequency tracking, clock pulse generating circuit 416 can export data recovered clock pulse CDR_CLK to frequency comparison circuit 420, reference as a comparison.
Therefore, in one example of the present invention embodiment, data receiver block 10 receives input signal IN_DATA, and signal deteching circuit 430 detects input signal IN_DATA and whether comprises echo signal, for example, whether comprise the data-signal DATA that is not less than second frequency.If so, signal deteching circuit 430 starts frequency comparison circuit 420 and carries out the operation of frequency automatic tracing.On the other hand, when input signal IN_DATA inputs, data-signal DATA can be transferred to respectively clock pulse restore circuit 412 and data recovery circuit 418, to produce data recovered clock pulse CDR_CLK and data, recovers crossfire CDR_DATA.In addition, in this exposure, the clock pulse signal of phase-locked loop circuit 413 is for example to utilize RC oscillator (RC oscillator) to produce.Clock pulse data restore circuit module 400 is by frequency comparison circuit 420, utilizes the frequency of data recovered clock pulse CDR_CLK to proofread and correct the clock pulse signal CLK of phase-locked loop circuit 413.Its correcting mode comprises adjusts the frequency multiplier multiple of phase-locked loop circuit 413 inside or the frequency of oscillation of frequency generating circuit 414, so that phase-locked loop circuit 413 produces a clock pulse signal CLK comparatively accurately.When data receiver block 10 does not receive data-signal DATA, clock pulse data restore circuit module 400 also can utilize this comparatively accurately clock pulse signal CLK be used as the signal of synchronizing frequency.
Fig. 5 illustrates the outline flowchart of the data recovered clock method for generating pulse of the present invention's one exemplary embodiment.Please refer to Figure 1B and Fig. 5, in this exemplary embodiment, in step S500, signal deteching circuit 130 detects input signal IN_DATA, to determine whether the frequency-splitting between comparing data recovered clock pulse CDR_CLK and clock pulse signal CLK according to testing result.Then, in step S510, the frequency-splitting between frequency comparison circuit 120 comparing data recovered clock pulse CDR_CLK and clock pulse signal CLK.Afterwards, in step S520, frequency comparison circuit 120 is adjusted the frequency of clock pulse signal CLK according to the comparative result of data recovered clock pulse CDR_CLK and clock pulse signal CLK.Again, in step S530, clock pulse data restore circuit 110 according to input signal IN_DATA and clock pulse signal CLK produce data recovered clock pulse CDR_CLK and data recover crossfire CDR_DATA both at least one of them.
Fig. 6 illustrates the outline flowchart of the data recovered clock method for generating pulse of another exemplary embodiment of the present invention.Please refer to Figure 1B and Fig. 6, in this exemplary embodiment, in step S600, first signal deteching circuit 130 detects whether received the echo signal of input signal IN_DATA.In this example, the echo signal of input signal IN_DATA is for example the second frequency composition that frequency is higher, i.e. the data-signal DATA of Fig. 2 or Fig. 3.If this echo signal detected, in step S610, signal deteching circuit 130 can start frequency comparison circuit 120, so that the frequency-splitting between frequency comparison circuit 120 comparing data recovered clock pulse CDR_CLK and clock pulse signal CLK, carry out frequency tracking function, as shown in step S620, thereby in step S630, frequency comparison circuit 120 can be adjusted according to comparative result the frequency of clock pulse signal CLK.Then, in step S660, clock pulse data restore circuit 110 can according to input signal IN_DATA and adjusted clock pulse signal CLK produce data recover crossfire CDR_DATA and data recovered clock pulse CDR_CLK both at least one of them.In this step, the clock pulse signal CLK before adjusted clock pulse signal CLK more originally adjusted is clock pulse signal more accurately.
In addition, in another exemplary embodiment, if after the check of the data empirical tests circuit 140 that decoder circuit 26 decodes, proof scheme 140 is found, when the error bit of the data recovery crossfire CDR_DATA of decoding surpasses a threshold value, now to can be considered data recovery crossfire CDR_DATA and suffer a noise jamming.Therefore,, in order to prevent original stabilized frequency drift of following the trail of rear gained, now proof scheme 140 also can suspend frequency comparison circuit 120, with this, maintain original clock pulse signal.
On the other hand, in step S600, when if signal deteching circuit 130 does not detect the echo signal of input signal IN_DATA, non-echo signal or electrical idle state for example detected, in step S640, signal deteching circuit 130 can not start frequency comparison circuit 120, so that frequency comparison circuit 120 quits work, do not carry out frequency tracking, as shown in step S650.
In addition, the data recovered clock method for generating pulse of the exemplary embodiment that above-mentioned Fig. 5 and Fig. 6 disclose can be obtained enough teachings, suggestion and implementation in the narration of Figure 1A to Fig. 4 embodiment, therefore repeats no more.
In sum, in exemplary embodiment of the present invention, when signal deteching circuit detects the echo signal in input signal, can start frequency comparison circuit, to carry out the function of frequency automatic tracing.Otherwise, when signal deteching circuit detects non-echo signal, can temporarily not start frequency comparison circuit, the accuracy of following the trail of with sustain pulse frequency.
Finally it should be noted that: each embodiment, only in order to technical scheme of the present invention to be described, is not intended to limit above; Although the present invention is had been described in detail with reference to aforementioned each embodiment, those of ordinary skill in the art is to be understood that: its technical scheme that still can record aforementioned each embodiment is modified, or some or all of technical characterictic is wherein equal to replacement; And these modifications or replacement do not make the essence of appropriate technical solution depart from the scope of various embodiments of the present invention technical scheme.
Claims (18)
1. a clock pulse data restore circuit module, is characterized in that, comprising:
One clock pulse data recovery circuit, in order to export data recovery crossfire and a data recovered clock pulse according to an input signal and a clock pulse signal;
One frequency comparison circuit, is coupled to this clock pulse data restore circuit, in order to the frequency-splitting between this data recovered clock pulse and this clock pulse signal relatively, to adjust the frequency of this clock pulse signal according to a comparative result; And
One signal deteching circuit, is coupled to this frequency comparison circuit, in order to receive and to detect this input signal, and determines whether starting this frequency comparison circuit according to this testing result.
2. clock pulse data restore circuit module according to claim 1, is characterized in that, this signal deteching circuit comprises:
Whether one first frequency detecting unit, comprise the data of a first frequency in order to receive and to detect this input signal; And
Whether one second frequency detecting unit, comprise that in order to receive and to detect this input signal one is not less than the data of a second frequency,
Wherein this second frequency is greater than this first frequency.
3. clock pulse data restore circuit module according to claim 2, is characterized in that, when this signal deteching circuit detects the data that this input signal comprises that this is not less than this second frequency, starts this frequency comparison circuit.
4. clock pulse data restore circuit module according to claim 2, is characterized in that, when this signal deteching circuit detects this input signal and comprises the data of this first frequency, does not start this frequency comparison circuit.
5. clock pulse data restore circuit module according to claim 1, is characterized in that, when this signal deteching circuit judges that this input signal is an electrical idle status signal, does not start this frequency comparison circuit.
6. clock pulse data restore circuit module according to claim 1, is characterized in that, this clock pulse data restore circuit comprises:
One clock pulse restore circuit, in order to produce this data recovered clock pulse according to this input signal and this clock pulse signal; And
One data recovery circuit, recovers crossfire in order to produce these data according to this input signal.
7. clock pulse data restore circuit module according to claim 1, is characterized in that, this clock pulse restore circuit comprises:
One clock pulse generating circuit, is coupled to this frequency generating circuit, in order to produce this data recovered clock pulse according to this input signal and this clock pulse signal; And
One frequency generating circuit, is coupled to this frequency comparison circuit, in order to produce this clock pulse signal according to a pulse reference clock,
Wherein this frequency comparison circuit is exported a control signal according to this comparative result, to adjust the frequency of this clock pulse signal that this frequency generating circuit produced.
8. clock pulse data restore circuit module according to claim 7, is characterized in that, this frequency generating circuit comprises:
One phase-locked loop circuit, is coupled to this frequency comparison circuit, is controlled by this control signal, in order to produce this clock pulse signal according to this control signal and this pulse reference clock; And
One pulse reference clock produces circuit, is coupled to this phase-locked loop circuit, in order to produce and to export this pulse reference clock.
9. clock pulse data restore circuit module according to claim 1, it is characterized in that, this clock pulse data restore circuit is exported these data and is recovered crossfire and this data recovered clock pulse to data processing block, this data processing block comprises a buffer storage circuit and a decoder circuit, wherein this decoder circuit recovers crossfire in order to these data of decoding, this buffer storage circuit recovers crossfire in order to store these data, this frequency comparison circuit is coupled to this buffer storage circuit, when this frequency comparison circuit is activated, this buffer storage circuit is exported these data and is recovered crossfire to this decoder circuit.
10. clock pulse data restore circuit module according to claim 9, is characterized in that, also comprises:
One proof scheme, be coupled to this decoder circuit, in order to checking, through these data of this decoder circuit decoding, recover crossfire, and in finding that these data recover the error bit of crossfire and surpass after a threshold value, suspend the relatively operation of the frequency-splitting between this data recovered clock pulse and this clock pulse signal of this frequency comparison circuit.
11. 1 kinds of data recovered clock method for generating pulse, is characterized in that, comprising:
Detect an input signal, to determine whether the frequency-splitting between comparison one data recovered clock pulse and a clock pulse signal according to a testing result;
The frequency-splitting between this data recovered clock pulse and this clock pulse signal relatively; And
According to the comparative result of this data recovered clock pulse and this clock pulse signal, adjust the frequency of this clock pulse signal.
12. data recovered clock method for generating pulse according to claim 11, is characterized in that, also comprise:
According to this input signal and this clock pulse signal produce this data recovered clock pulse and this data recover crossfire at least one of them.
13. data recovered clock method for generating pulse according to claim 11, is characterized in that, the step that detects this input signal comprises:
Detect the data whether this input signal comprises a first frequency; And
Detect this input signal and whether comprise that one is not less than the data of a second frequency,
Wherein this second frequency is greater than this first frequency.
14. data recovered clock method for generating pulse according to claim 13, it is characterized in that, when the data that this input signal comprises that this is not less than this second frequency being detected, carry out the step of the frequency-splitting between relatively this data recovered clock pulse and this clock pulse signal.
15. data recovered clock method for generating pulse according to claim 13, it is characterized in that, when this input signal being detected and comprise the data of this first frequency, do not carry out the step of the frequency-splitting between relatively this data recovered clock pulse and this clock pulse signal.
16. data recovered clock method for generating pulse according to claim 11, is characterized in that, this input signal comprises an electrical idle state, and the step that detects this input signal comprises:
Whether detect this input signal in this electrical idle state,
Wherein, when this input signal being detected in this electrical idle state, do not carry out the step of the frequency-splitting between relatively this data recovered clock pulse and this clock pulse signal.
17. data recovered clock method for generating pulse according to claim 11, is characterized in that, also comprise:
According to a pulse reference clock, produce this clock pulse signal,
The step of wherein adjusting the frequency of this clock pulse signal comprises:
According to this comparative result, export a control signal, to adjust the frequency of this clock pulse signal.
18. data recovered clock method for generating pulse according to claim 12, is characterized in that, also comprise:
These data of decoding are recovered crossfire; And
Checking recovers crossfire through these data of decoding, and surpasses after a threshold value in the error bit number of this data recovery crossfire, suspends the frequency-splitting between relatively this data recovered clock pulse and this clock pulse signal.
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| CN108365845A (en) * | 2017-01-26 | 2018-08-03 | 综合器件技术公司 | Quick response without reference frequency detector |
| CN113078978A (en) * | 2021-03-26 | 2021-07-06 | 杭州加速科技有限公司 | Synchronization method, system and test method for remote multi-ATE semiconductor test equipment |
| CN114362770A (en) * | 2022-01-10 | 2022-04-15 | 中国船舶重工集团公司第七一一研究所 | Data transmitting device, data receiving device, electronic apparatus, and method |
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| CN113078978A (en) * | 2021-03-26 | 2021-07-06 | 杭州加速科技有限公司 | Synchronization method, system and test method for remote multi-ATE semiconductor test equipment |
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| CN104009756B (en) | 2017-10-03 |
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