CN103973299A - Data and clock recovery device - Google Patents
Data and clock recovery device Download PDFInfo
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- CN103973299A CN103973299A CN201310033893.5A CN201310033893A CN103973299A CN 103973299 A CN103973299 A CN 103973299A CN 201310033893 A CN201310033893 A CN 201310033893A CN 103973299 A CN103973299 A CN 103973299A
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Abstract
A data and clock recovery device comprises a clock recovery module and a data recovery module. The clock recovery module comprises an adjustable delay unit, a first sampling unit, a second sampling unit, a first delay unit, a second delay unit and a judgment unit. The adjustable delay unit, the first delay unit and the second delay unit sequentially generate a first delay clock signal, a second delay clock signal and a third delay clock signal for clock signal delay, and the first sampling unit and the second sampling unit respectively sample a clock signal source according to the first delay clock signal and the third delay clock signal so as to extract a first clock state and a second clock state. The judgment unit judges whether the first clock state and the second clock state are in opposite phases or not so as to adjust the adjustable delay time of the adjustable delay unit when the first clock state and the second clock state are in the same phase. The data recovery module performs recovery on data signals according to the second delay clock signal when the first clock state and the second clock state are in opposite phases.
Description
Technical field
The present invention relates to a kind of signal recovery technology, and be particularly related to a kind of data and clock recovery device.
Background technology
Between various computer systems and network communicating system, often need to carry out a large amount of transfer of data.The transmission standard that the technology of transfer of data is different along with different designs and definition, but object is all to make receiving terminal can accurately and rapidly receive the data from transmitting terminal.
In order by holding wire, data to be sent to receiving terminal from transmitting terminal, receiving terminal must be known the data-signal of when sampling from transmitting terminal.For instance, low-voltage differential signal (Low-voltagedifferential signaling, LVDS), in transmission architecture specification, in the clock cycle, by a correspondence number data, the clock signal that therefore receiving terminal need to send according to the transmitting terminal of data correctly receives data according to this.But at data-signal under the situation in high frequency, because clock signal is differential type (differential), in the time that differential type is converted back monofocal (single) by receiving terminal wish, the error producing due to late effect easily cannot be alignd clock signal with data-signal.Under the inaccurate situation of clock signal, receiving terminal by thereby cannot be correct data-signal is recovered.
Therefore, how designing new data and clock recovery device, to overcome above-mentioned problem, is an industry problem demanding prompt solution for this reason.
Summary of the invention
Therefore, one aspect of the present invention is a kind of data and clock recovery (recovery) device to be provided, to comprise: clock recovery module and data recovery module.Clock recovery module comprises: adjustable delay unit, the first sampling unit, the first delay cell, the second delay cell, the second sampling unit and judging unit.Adjustable delay unit receive clock signal, clock signal is postponed to produce the first delay clock signals according to the adjustable delay time, wherein clock signal produces according to signal source of clock, and has time of delay between signal source of clock and clock signal.The first sampling unit according to the first delay clock signals to clock signal source sampling to extract the first clock status.The first delay cell postpones to produce the second delay clock signals to the first delay clock signals.The second delay cell postpones to produce the 3rd delay clock signals to the second delay clock signals.The second sampling unit in order to according to the 3rd delay clock signals to clock signal source sampling to extract second clock state.Judging unit judges whether the first clock status and second clock state are anti-phase, the adjustable delay time of adjustable delay unit is adjusted in the first clock status and second clock state as same phase time.Data recovery module is recovered data-signal according to the second delay clock signals in the time that the first clock status and second clock state are anti-phase.
According to one embodiment of the invention, be wherein low state and second clock state while being low state when judging unit judges the first clock status, adjust the adjustable delay time that increases.Be high state and second clock state while being high state when judging unit judges the first clock status, downgrade the adjustable delay time.Be low state and second clock state while being high state when judging unit judges the first clock status, data recovery module is recovered data-signal according to the second delay clock signals.
According to another embodiment of the present invention, be low state and second clock state while being low state when judging unit judges the first clock status, downgrade the adjustable delay time.Be wherein high state and second clock state while being high state when judging unit judges the first clock status, adjust the adjustable delay time that increases.Be high state and second clock state while being low state when judging unit judges the first clock status, data recovery module is recovered data-signal according to the second delay clock signals.
According to further embodiment of this invention, wherein data and clock recovery device also comprise delay locked loop module (delay locked loop; DLL), make to produce multiple phase-shifted clock signals according to the second delay clock signals, data recovery module is recovered data-signal according to phase-shifted clock signals in fact.
According to yet another embodiment of the invention, data and clock recovery device also comprise differential single-ended (the differential to single) circuit that turns, and signal source of clock is differential form, to be converted to the clock signal with single-ended format via the differential single-end circuit that turns.
Application the invention has the advantages that by data and clock recovery device, clock recovery module carries out after delay in various degree clock signal, with postpone signal to clock signal source sampling, and the clock signal state obtaining according to sampling, judge the edge of signal source of clock, further judge that the physical location of signal source of clock proofreaies and correct with the side-play amount to clock signal, and reach easily above-mentioned object.
Brief description of the drawings
For above and other object of the present invention, feature, advantage and embodiment can be become apparent, the description of the drawings is as follows:
Fig. 1 is during the present invention one implements, the calcspar of data and clock recovery device;
Fig. 2 A to Fig. 2 D is respectively in one embodiment of the invention, the oscillogram of signal source of clock, clock signal, the first delay clock signals, the second delay clock signals and the 3rd delay clock signals; And
Fig. 3 is in one embodiment of the invention, the second delay clock signals and the according to this oscillogram of the phase-shifted clock signals of generation.
[main element symbol description]
1: data and clock recovery device 10: clock recovery module
100: 102: the first sampling units of adjustable delay unit
106: the second delay cell of 104: the first delay cell
108: the second sampling units 110: judging unit
112: the differential single-end circuit 114 that turns: delay locked loop module
12: data recovery module
Embodiment
Please refer to Fig. 1.Fig. 1 is during the present invention one implements, the calcspar of data and clock recovery (recovery) device 1.Data and clock recovery device 1 comprise: clock recovery module 10 and data recovery module 12.
Clock recovery module 10 comprises: adjustable delay unit 100, the first sampling unit 102, the first delay cell 104, the second delay cell 106, the second sampling unit 108 and judging unit 110.
Adjustable delay unit 100 receive clock signal CK.In the present embodiment, clock signal C K is by differential single-ended (the differential to single) circuit 112 that turns, by originally converting for differential signal source of clock CKP/CKN.In other embodiments, clock signal C K also can receive other forms of signal source of clock from other possible circuit, and not by differential form is limit.Adjustable delay unit 100, by according to a default adjustable delay time ADT, postpones to produce the first delay clock signals CKD1 to clock signal C K.The first delay cell 104 can postpone to produce the second delay clock signals CKD2 again to the first delay clock signals CKD1.And the second delay cell 106 can postpone to produce the 3rd delay clock signals CKD3 to the second delay clock signals CKD2.
Referring to Fig. 2 A to Fig. 2 D.Fig. 2 A to Fig. 2 D is respectively in one embodiment of the invention, the oscillogram of signal source of clock CKP/CKN, clock signal C K, the first delay clock signals CKD1, the second delay clock signals CKD2 and the 3rd delay clock signals CKD3.
Due in the present embodiment, clock signal C K converts by the differential single-end circuit 112 that turns.Therefore, this differential single-end circuit 112 that turns, by DT time of delay causing as shown in Figure 2 A, makes the phase place of clock signal C K and signal source of clock CKP/CKN also inconsistent.The data recovery module 12 that the former data-signal DATA that should receive according to the time ordered pair of signal source of clock CKP/CKN recovers, cannot correctly recover data-signal DATA according to the clock signal C K postponing after conversion.Due to this time of delay, DT is unknown, therefore, needs effective method to be detected and proofreaies and correct.
By design of the present invention, the first sampling unit 102 can be according to the first delay clock signals CKD1, and to signal source of clock, CKP/CKN samples, to extract the first clock status STATE1.The second sampling unit 104 is in order to sample to extract second clock state STATE2 according to the 3rd delay clock signals CKD3 to signal source of clock CKP/CKN.
In different embodiment, the first sampling unit 102 and the second sampling unit 104 can utilize rising edge or trailing edge to sample to signal source of clock CKP/CKN.In the present embodiment, the first sampling unit 102 and the second sampling unit 104 are to utilize rising edge to sample to signal source of clock CKP/CKN.The first delay cell 104 and the second delay cell 106, through under suitable design, can be controlled time of delay, make only have minimum gap between the first delay clock signals CKD1, the second delay clock signals CKD2 and the 3rd delay clock signals CKD3.Therefore, the edge (edge) of the first delay clock signals CKD1 and the 3rd delay clock signals CKD3, with the edge of the second delay clock signals CKD2 by very close and be positioned at the both sides, edge of the second delay clock signals CKD2.
Judging unit 110 further judges whether the first clock status STATE1 and second clock state STATE2 are anti-phase.As shown in Figure 2 A, judging unit 110 is by judgement the first clock status STATE1 and second clock state STATE2 is low state (0,0) and be homophase.Therefore, judging unit 110 will learn between the first clock status STATE1 and second clock state STATE2 do not have the edge of signal source of clock CKP/CKN.
Judging unit 110, judging that the first clock status STATE1 and second clock state STATE2 are same phase time, is adjusted the adjustable delay time ADT to adjustable delay unit 100.In the present embodiment, judging unit 110 will increase adjustable delay time ADT, so that the first delay clock signals CKD1 relative time clock signal CK carries out the delay of longer time.
After adjustable delay time ADT after adjustable delay unit 100, the first delay cell 104 and the second delay cell 106 are according to new adjustment postpones again, the sampled result that the first sampling unit 102 and the second sampling unit 104 carry out according to the first delay clock signals CKD1 and the 3rd delay clock signals CKD3 is still same phase time, adjustable delay unit 100 will continue adjustable delay time ADT to adjust, until as shown in 2B figure, till when sampled result reaches anti-phase (0,1).Now, clock phase is positioned at the second delay clock signals CKD2 between the first delay clock signals CKD1 and the 3rd delay clock signals CKD3, equates with position, the edge essence of signal source of clock CKP/CKN.More exactly, adjust the second delay clock signals CKD2 of gained according to the mode of the present embodiment, be actually signal source of clock CKP/CKN and differ a whole clock cycle.
Should be noted, use " essence an equates " word herein, in the setting representing due to time of delay of the first delay cell 104 and the second delay cell 106, may affect the accuracy of sampling, and cause a little error, and make the phasetophase of the second delay clock signals CKD2 and signal source of clock CKP/CKN, have slightly but admissible error, and not fully equate.
Therefore, by above-mentioned mode, clock recovery module 10 can predict the phase place of signal source of clock CKP/CKN, so that the second delay clock signals CKD2 that data recovery module 12 can be exported according to the first delay cell 104 carries out recovery routine correctly to data-signal DATA.
Similarly, in another embodiment, the sampled result that the first sampling unit 102 and the second sampling unit 104 carry out according to the first delay clock signals CKD1 and the 3rd delay clock signals CKD3 may be as shown in Figure 2 C, for being the homophase of high state (1,1).Now, adjustable delay unit 100 can downgrade adjustable delay time ADT, so that the first delay clock signals CKD1 relative time clock signal CK has the delay of short period, and progressively approach the position, edge of signal source of clock CKP/CKN, until sampled result is anti-phase (0,1) till, to reach effect of correction.
Should be noted, in other embodiments, the first sampling unit 102 and the second sampling unit 104 also can be sampled to signal source of clock CKP/CKN according to the trailing edge of the first delay clock signals CKD1 and the 3rd delay clock signals CKD3, and after being judged by judging unit 110, control according to this adjustable delay time ADT of adjustable delay unit 100.Taking Fig. 2 D as example, the first sampling unit 102 and the second sampling unit 104 are homophase (1,1) according to the trailing edge of the first delay clock signals CKD1 and the 3rd delay clock signals CKD3 to the result of signal source of clock CKP/CKN sampling.Now, judging unit 110 is adjustable increasing adjustable delay time ADT, until till sampled result is anti-phase (1,0).And if sampled result is homophase (0,0), judging unit 110 can downgrade adjustable delay time ADT, until till sampled result is anti-phase (1,0).In the result of sampling, while being anti-phase, data recovery module 12 also can, according to the second delay clock signals CKD2 that now the first delay cell 104 is exported, be carried out recovery routine correctly to data-signal DATA.
Please refer to Fig. 3, Fig. 3 is in one embodiment of the invention, the second delay clock signals CKD2 and the phase-shifted clock signals CKP1, the CKP2 that produce according to this ..., CKPN oscillogram.In one embodiment, the second delay clock signals CKD2 that the first delay cell 104 is exported can via a delay locked loop module 114 as shown in Figure 1 produce multiple phase-shifted clock signals CKP1, CKP2 ..., after CKPN, provide to data recovery module 12 and carry out data recovery.Therefore, as low-voltage differential signal (Low-voltage differential signaling, LVDS) in transmission architecture specification, in the clock cycle by a correspondence number data, due to the data frequency of data-signal DATA be signal source of clock CKP/CKN clock frequency N doubly, phase-shifted clock signals CKP1, CKP2 that data recovery module 12 can produce according to delay locked loop module 114 ..., CKPN carries out data recovery.Should be noted, data of the present invention and clock recovery device 1 also can be applicable in other transmission architecture, are not limited to above low-voltage differential signal transmission architecture of giving an example.
Therefore, the present invention can, by clock recovery module 10 to producing the clock signal C K postponing and proofread and correct via the differential single-end circuit 112 that turns, make to become the second delay clock signals CKD2 of Single-end output and the signal source of clock CKP/CKN of differential form is homophase.Data recovery module 12 can correctly be carried out recovery routine to data-signal DATA according to this.
Although the present invention with execution mode openly as above; so it is not in order to limit the present invention, those skilled in the art, without departing from the spirit and scope of the present invention; when being used for a variety of modifications and variations, therefore protection scope of the present invention is when being as the criterion depending on appended claims confining spectrum.
Claims (9)
1. data and a clock recovery device, comprises:
One clock recovery module, comprises:
One adjustable delay unit, in order to receive a clock signal, this clock signal is postponed to produce one first delay clock signals according to the adjustable delay time, wherein this clock signal produces according to a signal source of clock, and has a time of delay between this signal source of clock and this clock signal;
One first sampling unit, in order to according to this first delay clock signals to this clock signal source sampling to extract one first clock status;
One first delay cell, postpones to produce one second delay clock signals to this first delay clock signals;
One second delay cell, postpones to produce one the 3rd delay clock signals to this second delay clock signals;
One second sampling unit, in order to according to the 3rd delay clock signals to this clock signal source sampling to extract a second clock state; And
One judging unit, judges whether this first clock status and this second clock state are anti-phase, this adjustable delay time of this adjustable delay unit is adjusted in this first clock status and this second clock state as same phase time; And
One data recovery module, recovers a data-signal according to this second delay clock signals while being anti-phase at this first clock status and this second clock state.
2. data as claimed in claim 1 and clock recovery device, is wherein low state and this second clock state while being low state when this judging unit judges this first clock status, adjusts this adjustable delay time that increases.
3. data as claimed in claim 2 and clock recovery device, is wherein high state and this second clock state while being high state when this judging unit judges this first clock status, downgrades this adjustable delay time.
4. data as claimed in claim 3 and clock recovery device, be wherein low state and this second clock state while being high state when this judging unit judges this first clock status, this data recovery module is recovered this data-signal according to this second delay clock signals.
5. data as claimed in claim 1 and clock recovery device, is wherein low state and this second clock state while being low state when this judging unit judges this first clock status, downgrades this adjustable delay time.
6. data as claimed in claim 5 and clock recovery device, is wherein high state and this second clock state while being high state when this judging unit judges this first clock status, adjusts this adjustable delay time that increases.
7. data as claimed in claim 6 and clock recovery device, be wherein high state and this second clock state while being low state when this judging unit judges this first clock status, this data recovery module is recovered this data-signal according to this second delay clock signals.
8. data as claimed in claim 1 and clock recovery device, also comprises a delay locked loop module (delay locked loop; DLL), make to produce multiple phase-shifted clock signals according to this second delay clock signals, this data recovery module is recovered this data-signal according to described phase-shifted clock signals in fact.
9. data as claimed in claim 1 and clock recovery device, also comprise differential single-ended (the differential to single) circuit that turns, this signal source of clock is a differential form, to be converted to this clock signal with a single-ended format via this differential single-end circuit that turns.
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| CN201310033893.5A CN103973299A (en) | 2013-01-29 | 2013-01-29 | Data and clock recovery device |
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| CN201310033893.5A CN103973299A (en) | 2013-01-29 | 2013-01-29 | Data and clock recovery device |
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| CN103973299A true CN103973299A (en) | 2014-08-06 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN107395198A (en) * | 2017-07-28 | 2017-11-24 | 北京集创北方科技股份有限公司 | A kind of clock data recovery device and method |
| CN108352838A (en) * | 2015-10-28 | 2018-07-31 | 华为技术有限公司 | High-jitter-tolerance without reference frequency detector |
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| JP2006287484A (en) * | 2005-03-31 | 2006-10-19 | Kawasaki Microelectronics Kk | Clock data recovery circuit |
| CN1883153A (en) * | 2003-11-20 | 2006-12-20 | 爱德万测试株式会社 | Clock recovery circuit and communication device |
| US20110169540A1 (en) * | 2010-01-14 | 2011-07-14 | Ian Kyles | Clock and data recovery for burst-mode serial signals |
| US20120033774A1 (en) * | 2010-08-06 | 2012-02-09 | Sony Corporation | CDR circuit, reception apparatus, and communication system |
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| US20030091139A1 (en) * | 2001-09-18 | 2003-05-15 | Jun Cao | System and method for adjusting phase offsets |
| CN1883153A (en) * | 2003-11-20 | 2006-12-20 | 爱德万测试株式会社 | Clock recovery circuit and communication device |
| JP2006287484A (en) * | 2005-03-31 | 2006-10-19 | Kawasaki Microelectronics Kk | Clock data recovery circuit |
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| US20120033774A1 (en) * | 2010-08-06 | 2012-02-09 | Sony Corporation | CDR circuit, reception apparatus, and communication system |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108352838A (en) * | 2015-10-28 | 2018-07-31 | 华为技术有限公司 | High-jitter-tolerance without reference frequency detector |
| CN108352838B (en) * | 2015-10-28 | 2020-09-11 | 华为技术有限公司 | High jitter tolerant reference-less frequency detector |
| CN107395198A (en) * | 2017-07-28 | 2017-11-24 | 北京集创北方科技股份有限公司 | A kind of clock data recovery device and method |
| CN107395198B (en) * | 2017-07-28 | 2023-10-13 | 北京集创北方科技股份有限公司 | Clock data recovery device and method |
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Application publication date: 20140806 |