CN103092258A - Clock generation circuit self-correction system and clock generation circuit self-correction method - Google Patents
Clock generation circuit self-correction system and clock generation circuit self-correction method Download PDFInfo
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- CN103092258A CN103092258A CN2013100328399A CN201310032839A CN103092258A CN 103092258 A CN103092258 A CN 103092258A CN 2013100328399 A CN2013100328399 A CN 2013100328399A CN 201310032839 A CN201310032839 A CN 201310032839A CN 103092258 A CN103092258 A CN 103092258A
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Abstract
The invention provides a clock generation circuit self-correction system and a clock generation circuit self-correction method. The clock generation circuit self-correction system comprises a hardware logic module, a register module connected with the hardware logic module, a clock generation circuit module connected with the hardware logic module and the register module, and a storage module connected with the register module in a two-way mode. The hardware logic module generates search data and transmits the search data to the register module, and the search data is used as configuration parameters of the clock generation circuit module. The register module outputs register data to the clock generation circuit module, and a system clock signal is generated, and is transmitted to the hardware logic module. Comparison is carried out between the system clock signal and an external reference clock signal, when requirements of accuracy are not satisfied, correction is carried out to the search data to generate new search data, and the next round of correction is carried out until the requirements of accuracy are satisfied, the hardware logic module stops correction, and meanwhile the search data is stored in the storage module. The clock generation circuit self-correction system and the clock generation circuit self-correction method are capable of automatically reducing error of a clock generation circuit in an electronic system to a required error range.
Description
[technical field]
The present invention relates to integrated circuit fields, relate in particular to and can be automatically the error of the clock generation circuit in electronic system be reduced to clock generation circuit self correcting system and bearing calibration thereof in desired error range.
[background technology]
The clock signal of using in integrated circuit fields needs very high degree of accuracy usually, can guarantee that just communication is normal.Existing clock generation circuit alignment technique is the Chinese patent of CN200410086408.1 as the patent No., and the main algorithm of counting that adopts is realized proofreading and correct, and generally need to complete correct operation by control module such as CPU or MCU.
The defective that has the existence of clock generation circuit alignment technique now mainly contains: the first, lack checking computations mechanism, cause verifying whether the clock accuracy after its correction satisfies system requirements; The second, lack Data Control and storage, cause correction data easily to lose, poor reliability; Three, as long as lack the intervention of CPU or MCU, can't complete correction, namely system does not possess self-correcting capability.
[summary of the invention]
For the problems referred to above, the purpose of this invention is to provide and a kind ofly can be automatically the error of the clock generation circuit in electronic system be reduced to clock generation circuit self correcting system and bearing calibration thereof in desired error range.
A kind of clock generation circuit self correcting system, it comprises:
The hardware logic module, it receives external reference clock signal;
Register module, its be connected the hardware logic module and connect;
The clock generation circuit module, its be connected hardware logic module and described register module and connect; And
Memory module, its be connected the two-way connection of register module;
described hardware logic module produces search data and transfers to described register module as the configuration parameter of oscillator in described clock generation circuit module, described register module according to described search data output register data to described clock generation circuit module, described clock generation circuit module produces clock signal of system and transfers to described hardware logic module, described hardware logic module compares described clock signal of system and described external reference clock signal, when the clock frequency of described oscillator output does not satisfy accuracy requirement, described hardware logic module is proofreaied and correct described search data and is produced new search data and carry out next round and proofread and correct, until the clock frequency of described oscillator output is when satisfying accuracy requirement, described hardware logic module stops proofreading and correct, and this moment, search data was stored in described memory module.
In the present invention's one better embodiment, described hardware logic module is proofreaied and correct described search data and is comprised the value that increases described search data and the value that reduces described search data.
In the present invention's one better embodiment, described register module is the register of variable bit width, and it deposits described search data in the different moment.
In the present invention's one better embodiment, described memory module is nonvolatile memory.
In the present invention's one better embodiment, described clock generation circuit self correcting system further comprises data transmission module, described data transmission module is arranged between described register module and described memory module, its be connected the respectively two-way connection of register module and described memory module, described memory module by described data transmission module be connected the two-way connection of register module.
In the present invention's one better embodiment, described external reference clock signal inputs to described hardware logic module by the external clock generator.
The present invention provides a kind of bearing calibration of clock generation circuit self correcting system in addition, and it comprises the following steps:
Produce search data;
The frequency size of comparison system clock signal and external reference clock signal stops proofreading and correct and storing correction data if frequency error satisfies accuracy requirement, otherwise judges that described clock signal of system is still too slow too soon with respect to described external reference clock signal;
If described clock signal of system is too fast with respect to described external reference clock signal, reduce described search data, if described clock signal of system is too slow with respect to described external reference clock signal, increase described search data;
Enter the correction of next round after time-delay.
In the present invention's one better embodiment, described search data produces and transfers to register module as the configuration parameter of oscillator in the clock generation circuit module by the hardware logic module.
In the present invention's one better embodiment, described correction data is to make the frequency of the clock signal of system of oscillator output in the clock generation circuit module satisfy the value of the search data of accuracy requirement with respect to the frequency of described external reference clock signal.
In the present invention's one better embodiment, described external reference clock signal inputs to described hardware logic module by the external clock generator.
With respect to prior art, described clock generation circuit self correcting system is passed through hardware logic module, register module and clock generation circuit module wherein, utilize described bearing calibration, can be automatically the error of the clock generation circuit in the respective electronic system be reduced in the desired error precision scope of this electronic system, and corrected value is kept in wherein memory module, thus, can be after described clock generation circuit self correcting system to be completed correction, this electronic system its clock generation circuit after at every turn powering on can provide high-precision clock signal.
Above-mentioned explanation is only the general introduction of technical solution of the present invention, for can clearer understanding technological means of the present invention, and can be implemented according to the content of instructions, and for above and other objects of the present invention, feature and advantage can be become apparent, below especially exemplified by embodiment, and the cooperation accompanying drawing, be described in detail as follows.
[description of drawings]
The composition diagram of the clock generation circuit self correcting system that Fig. 1 provides for first embodiment of the invention.
The composition diagram of the clock generation circuit self correcting system that Fig. 2 provides for second embodiment of the invention.
The workflow diagram of the bearing calibration of the clock generation circuit self correcting system that Fig. 3 provides for third embodiment of the invention.
[embodiment]
In order to make purpose of the present invention, technical scheme and advantage clearer, below in conjunction with drawings and Examples, the present invention is further elaborated.Should be appreciated that specific embodiment described herein only in order to explain the present invention, is not intended to limit the present invention.
See also Fig. 1, first embodiment of the invention provides a kind of clock generation circuit self correcting system 100, and it comprises hardware logic module (search reg) 10, register module (reg) 20, clock generation circuit module (osc) 30 and memory module (mem) 40.
The input signal of described hardware logic module 10 is the clock signal of system osc_clk of external reference clock signal ref_clk and 30 outputs of described clock generation circuit module, output signal is search data nxt_reg, and search data nxt_reg is transferred to described register module 20.in the present embodiment, described hardware logic module 10 is utilized certain searching algorithm, search data nxt_reg is exported to described register module 20, configuration parameter as the oscillator of described clock generation circuit module 30 (figure indicates), then monitor the clock signal of system osc_clk that described oscillator produces, and by certain method, described clock signal of system osc_clk and described external reference clock signal ref_clk are compared, until some search data nxt_reg make the frequency error of the clock signal of system osc_clk of described oscillator output satisfy accuracy requirement, at this moment, the value of this search data nxt_reg is correction data (result), it transfers to described memory module 40 and is stored in described memory module 40.Be that described search data nxt_reg is revised in described hardware logic module 10 circulations, to proofread and correct the clock signal of system osc_clk of described clock generation circuit module 30 outputs, make the frequency error of described clock signal of system osc_clk satisfy accuracy requirement, and obtain correction data (result).
Be understandable that, obtain in the process of correction data (result), described hardware logic module 10 relates to searching algorithm and the frequency accuracy comparison algorithm of search data nxt_reg.wherein, the searching algorithm of search data nxt_reg can produce an initial value, then the comparative result of the clock frequency by described external reference clock signal ref_clk and described clock signal of system osc_clk, judge whether to need to increase or reduce the value of described search data nxt_reg, if comparative result does not satisfy accuracy requirement proofreaies and correct next time, namely increase or reduce the new search data nxt_reg of described search data nxt_reg generation and carry out the search of a new round, until the comparative result of described clock signal of system ref_clk and described external reference clock signal ref_clk satisfies accuracy requirement., increase or the value that reduces described search data nxt_reg can adopt dichotomy or successively add one and subtracts an operation herein, specifically can select as required.the frequency accuracy comparison algorithm is the method for the clock frequency of more described external reference clock signal ref_clk and described clock signal of system osc_clk, rising edge or the negative edge that can utilize high-frequency clock to adopt the low frequency clock add a counting, through stopping counting after the known time, relatively value and the precalculated standard value of counter judge whether precision meets the demands, another comparative approach is to adopt respectively counter that described external reference clock signal ref_clk and described clock signal of system osc_clk are counted, stop counting after after a while, relatively whether the value of two counters satisfies accuracy requirement, because described external reference clock signal ref_clk and described clock signal of system osc_clk are asynchronous clock signals, so can not directly compare the value of two counters, usually can utilize Gray code conversion, then the value after Gray code is made a call to two rows synchronous, Gray code is binary code again, and then compare, and then judge whether comparative result meets the demands.
Described register module 20 be connected hardware logic module 10 and connect, its input signal is the search data nxt_reg of described hardware logic module 10 generations and the data mem2re that transmits from described memory module 40, and output signal is register data new_reg and data re2mem.Described register data new_reg is input to described clock generation circuit module 30, and described data re2mem is input to described memory module 40.In the present embodiment, described register module 20 is register, its bit wide can change as required, deposit the value of described search data nxt_reg and data mem2re in the different moment, and exporting described register data new_reg to described clock generation circuit module 30, re2mem is to described memory module 40 for the output data.
Be understandable that, described register data new_reg is that described register module 20 produces according to the described search data nxt_reg that receives.
Described clock generation circuit module 30 be connected hardware logic module 10 and described register module 20 and all connect, itself and described hardware logic module 10 and described register module 20 consist of one-way circulations.The input signal of described clock generation circuit module 30 is the register data new_reg of described register module 20 outputs, and output signal be the clock signal of system osc_clk of oscillator generation wherein.Described clock signal of system osc_clk inputs to described hardware logic module 10.Described clock generation circuit module 30 produces the different clock signal of system osc_clk of frequency according to different register data new_reg.
Described memory module 40 be connected the two-way connection of register module 20, its input signal is the data re2mem of described register module 20 outputs, output signal is data mem2re.In the present embodiment, described memory module 40 is nonvolatile memory, can store steadily in the long term data, and when described memory module 40 power down, the data of its storage can not lost yet.
Be understandable that, the data re2mem that described register module 20 exports described memory module 40 to is described correction data result, and thus, described correction data result can be stored in described memory module 40.Be that described correction data result can transmit between described memory module 40 and described register module 20.Proofread and correct first by after need described correction data result by being transferred to described memory module 40 from described register module 20, need to be described correction data result by being transferred to described register module 20 from described memory module 40 when powering on later at every turn.In the present embodiment, the transmission of described correction data result between described register module 20 and described memory module 40 realizes by software.Certainly, and be confined to this, between described register module 20 and described memory module 40, the transmission of data-signal also can realize by hardware, as shown in Figure 2, the clock generation circuit self correcting system 200 that second embodiment of the invention provides further comprises data transmission module (move control) 50, described data transmission module 50 is arranged between described register module 20 and described memory module 40, its be connected the 40 two-way connections respectively of register module 20 and described memory module.
In the present embodiment, described register module 20 output data re2mc are to described data transmission module 50, the data me2mc that the input signal of described data transmission module 50 is described data re2mc and exports from described memory module 40, output signal is the data mc2me that transfers to the data mc2re of described register module 20 and transfer to described memory module 40.
Be understandable that, in the present embodiment, described clock generation circuit self correcting system 200 realizes the transmission of described correction data result between described memory module 40 and described register module 20 by described data transmission module 50.At this moment, proofread and correct first by rear described correction data result and be transferred to described memory module 40 by described data transmission module 50 from described register module 20, and when powering on thereafter, described correction data result is transferred to described register module 20 by described data transmission module 50 from described memory module 40 at every turn.
See also Fig. 3, third embodiment of the invention provides the bearing calibration of described clock generation circuit self correcting system 100, and it comprises the following steps:
S101, generation search data.
In the present embodiment, described hardware logic module 10 produces search data nxt_reg, and export described register module 20 to, configuration parameter as oscillator in described clock generation circuit module 30, form register data new_reg signal by described register module 20 according to described search data nxt_reg again, and be transferred to described clock generation circuit module 30, the oscillator output system clock signal osc_clk of described clock generation circuit module 30, and transfer to described hardware logic module 10.
The frequency size of S103, more described clock signal of system and external reference clock signal.
In the present embodiment, the frequency of described hardware logic module 10 comparison system clock signal osc_clk and described external reference clock signal ref_clk size.
Whether S104, determination frequency error satisfy accuracy requirement.
If the frequency error of described clock signal of system osc_clk and described external reference clock signal ref_clk satisfies accuracy requirement enters step S105A, otherwise enter step S105B.
Be understandable that, described external reference clock signal ref_clk inputs to described hardware logic module 10 by the external clock generator.
S105A, stop proofreading and correct, and the storage correction data.
In the present embodiment, making the frequency of the clock signal of system osc_clk of described oscillator output is correction data result with respect to the value that the frequency of described external reference clock signal ref_clk satisfies the search data nxt_reg of accuracy requirement, and described correction data result transfers to described memory module 40 and stores.
S105B, the judgement described clock signal of system still too slow too soon with respect to described external reference clock signal.
in the present embodiment, frequency error according to described clock signal of system osc_clk and described external reference clock signal ref_clk, judge that described clock signal of system osc_clk is too soon or too slow with respect to described external reference clock signal ref_clk, and correspondingly revise the value of search data nxt_reg, if described clock signal of system osc_clk is too fast with respect to described external reference clock signal ref_clk, enter step S107A, if described clock signal of system osc_clk is too slow with respect to described external reference clock signal ref_clk, enter step S107B.
S107A, reduce described search data.
Be understandable that, reducing new search data nxt_reg that described search data nxt_reg produces will make clock signal of system osc_clk that described clock generation circuit module 30 produces near described external reference clock signal ref_clk, thus, can reduce the frequency error of described clock signal of system osc_clk and described external reference clock signal ref_clk, and then satisfy accuracy requirement.
S107B, the described search data reg of increase.
Be understandable that, increasing new search data nxt_reg that described search data nxt_reg produces will make clock signal of system osc_clk that described clock generation circuit module 30 produces near described external reference clock signal ref_clk, thus, can reduce the frequency error of described clock signal of system osc_clk and described external reference clock signal ref_clk, and then satisfy accuracy requirement.
Enter the correction of next round after S109, time-delay.
Be understandable that, due to described clock generation circuit module 30 after obtaining new register data new_reg value, need a period of time just can settle out, thus, after obtaining new register data new_reg value, need to wait for a period of time, namely begin again to produce the nxt_reg signal after the time-delay.
Be understandable that, exist different concrete time delay to different clock generation circuits, need to determine by emulation.
Be understandable that, the described clock generation circuit self correcting system 200 that second embodiment of the invention provides can adopt described bearing calibration equally.
compared to prior art, described clock generation circuit self correcting system 100(provided by the invention and described clock generation circuit self correcting system 200) hardware logic module 10 by wherein, register module 20 and clock generation circuit module 30, utilize described bearing calibration, can be automatically the error of the clock generation circuit in the respective electronic system be reduced in the desired error precision scope of this electronic system, and corrected value is kept in described memory module 40, thus, can be after described clock generation circuit self correcting system 100 be completed correction, this electronic system clock generation circuit after at every turn powering on can provide high-precision clock signal.
The above is only preferred embodiment of the present invention, not in order to limiting the present invention, all any modifications of doing within the spirit and principles in the present invention, is equal to and replaces and improvement etc., within all should being included in protection scope of the present invention.
Claims (10)
1. a clock generation circuit self correcting system, is characterized in that, described clock generation circuit self correcting system comprises:
The hardware logic module, it receives external reference clock signal;
Register module, its be connected the hardware logic module and connect;
The clock generation circuit module, its be connected hardware logic module and described register module and connect; And
Memory module, its be connected the two-way connection of register module;
described hardware logic module produces search data and transfers to described register module as the configuration parameter of oscillator in described clock generation circuit module, described register module according to described search data output register data to described clock generation circuit module, described clock generation circuit module produces clock signal of system and transfers to described hardware logic module, described hardware logic module compares described clock signal of system and described external reference clock signal, when the clock frequency of described oscillator output does not satisfy accuracy requirement, described hardware logic module is proofreaied and correct described search data and is produced new search data and carry out next round and proofread and correct, until the clock frequency of described oscillator output is when satisfying accuracy requirement, described hardware logic module stops proofreading and correct, and this moment, search data was stored in described memory module.
2. clock generation circuit self correcting system as claimed in claim 1, is characterized in that, described hardware logic module is proofreaied and correct described search data and comprised the value that increases described search data and the value that reduces described search data.
3. clock generation circuit self correcting system as claimed in claim 1, is characterized in that, described register module is the register of variable bit width, and it deposits described search data in the different moment.
4. clock generation circuit self correcting system as claimed in claim 1, is characterized in that, described memory module is nonvolatile memory.
5. clock generation circuit self correcting system as claimed in claim 1, it is characterized in that, described clock generation circuit self correcting system further comprises data transmission module, described data transmission module is arranged between described register module and described memory module, its be connected the respectively two-way connection of register module and described memory module, described memory module by described data transmission module be connected the two-way connection of register module.
6. clock generation circuit self correcting system as claimed in claim 1, is characterized in that, described external reference clock signal inputs to described hardware logic module by the external clock generator.
7. the bearing calibration of a clock generation circuit self correcting system, is characterized in that, described bearing calibration comprises the following steps:
Produce search data;
The frequency size of comparison system clock signal and external reference clock signal stops proofreading and correct and storing correction data if frequency error satisfies accuracy requirement, otherwise judges that described clock signal of system is still too slow too soon with respect to described external reference clock signal;
If described clock signal of system is too fast with respect to described external reference clock signal, reduce described search data, if described clock signal of system is too slow with respect to described external reference clock signal, increase described search data;
Enter the correction of next round after time-delay.
8. the bearing calibration of clock generation circuit self correcting system as claimed in claim 7, is characterized in that, described search data produces and transfer to register module as the configuration parameter of oscillator in the clock generation circuit module by the hardware logic module.
9. the bearing calibration of clock generation circuit self correcting system as claimed in claim 7, it is characterized in that, described correction data is to make the frequency of the clock signal of system of oscillator output in the clock generation circuit module satisfy the value of the search data of accuracy requirement with respect to the frequency of described external reference clock signal.
10. the bearing calibration of clock generation circuit self correcting system as claimed in claim 7, is characterized in that, described external reference clock signal inputs to described hardware logic module by the external clock generator.
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| CN201310032839.9A CN103092258B (en) | 2013-01-28 | 2013-01-28 | Clock generation circuit self correcting system and bearing calibration thereof |
| PCT/CN2013/088846 WO2014114146A1 (en) | 2013-01-28 | 2013-12-09 | Self-correcting system for clock-generating circuit and correcting method thereof |
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| CN201310032839.9A CN103092258B (en) | 2013-01-28 | 2013-01-28 | Clock generation circuit self correcting system and bearing calibration thereof |
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| WO2014114146A1 (en) * | 2013-01-28 | 2014-07-31 | 深圳市汇顶科技股份有限公司 | Self-correcting system for clock-generating circuit and correcting method thereof |
| CN104184470A (en) * | 2014-09-01 | 2014-12-03 | 福州瑞芯微电子有限公司 | Automatic resetting device and method for PLL modification |
| CN107820678A (en) * | 2017-09-27 | 2018-03-20 | 深圳市汇顶科技股份有限公司 | Pulsewidth amendment circuit, pulsewidth modification method and electronic equipment |
| CN109394193A (en) * | 2018-11-27 | 2019-03-01 | 西安交大辰方科技有限公司 | A kind of method of ambulatory blood pressure logger real-time clock calibration |
| CN110492848A (en) * | 2019-08-15 | 2019-11-22 | 成都锐成芯微科技股份有限公司 | The number adjustment device and its method of adjustment of RC oscillator |
| CN110729984A (en) * | 2018-07-17 | 2020-01-24 | 中芯国际集成电路制造(北京)有限公司 | Clock signal generating circuit and electronic equipment |
| CN110729985A (en) * | 2018-07-17 | 2020-01-24 | 中芯国际集成电路制造(北京)有限公司 | Clock signal generating circuit and electronic equipment |
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| US20060122799A1 (en) * | 2004-10-01 | 2006-06-08 | Yi-Chang Chen | Method and device for clock calibration |
| CN101170349A (en) * | 2006-10-23 | 2008-04-30 | 大唐移动通信设备有限公司 | Real time clock calibration circuit |
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Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2014114146A1 (en) * | 2013-01-28 | 2014-07-31 | 深圳市汇顶科技股份有限公司 | Self-correcting system for clock-generating circuit and correcting method thereof |
| CN104184470A (en) * | 2014-09-01 | 2014-12-03 | 福州瑞芯微电子有限公司 | Automatic resetting device and method for PLL modification |
| CN104184470B (en) * | 2014-09-01 | 2017-04-19 | 福州瑞芯微电子股份有限公司 | Automatic resetting device and method for PLL modification |
| CN107820678A (en) * | 2017-09-27 | 2018-03-20 | 深圳市汇顶科技股份有限公司 | Pulsewidth amendment circuit, pulsewidth modification method and electronic equipment |
| WO2019061077A1 (en) * | 2017-09-27 | 2019-04-04 | 深圳市汇顶科技股份有限公司 | Pulse width modification circuit, pulse width modification method, and electronic apparatus |
| CN110729984A (en) * | 2018-07-17 | 2020-01-24 | 中芯国际集成电路制造(北京)有限公司 | Clock signal generating circuit and electronic equipment |
| CN110729985A (en) * | 2018-07-17 | 2020-01-24 | 中芯国际集成电路制造(北京)有限公司 | Clock signal generating circuit and electronic equipment |
| CN110729984B (en) * | 2018-07-17 | 2023-12-22 | 中芯国际集成电路制造(北京)有限公司 | Clock signal generation circuit and electronic equipment |
| CN109394193A (en) * | 2018-11-27 | 2019-03-01 | 西安交大辰方科技有限公司 | A kind of method of ambulatory blood pressure logger real-time clock calibration |
| CN109394193B (en) * | 2018-11-27 | 2021-04-23 | 西安交大辰方科技有限公司 | Method for calibrating real-time clock of dynamic blood pressure recorder |
| CN110492848A (en) * | 2019-08-15 | 2019-11-22 | 成都锐成芯微科技股份有限公司 | The number adjustment device and its method of adjustment of RC oscillator |
Also Published As
| Publication number | Publication date |
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| WO2014114146A1 (en) | 2014-07-31 |
| CN103092258B (en) | 2016-08-24 |
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