WO2019061077A1

WO2019061077A1 - Pulse width modification circuit, pulse width modification method, and electronic apparatus

Info

Publication number: WO2019061077A1
Application number: PCT/CN2017/103686
Authority: WO
Inventors: 张孟文
Original assignee: 深圳市汇顶科技股份有限公司
Priority date: 2017-09-27
Filing date: 2017-09-27
Publication date: 2019-04-04
Also published as: CN107820678A; CN107820678B

Abstract

A pulse width modification circuit, pulse width modification method, and electronic apparatus, configured to solve an existing problem in which a pulse width of a clock signal received by a digital clock does not meet a requirement. The pulse width modification circuit comprises: a delay module (101) configured to perform delay processing on an input clock signal according to a delay control parameter, so as to obtain a delayed clock signal; a logical operation module (102) configured to perform a logical operation on the input clock signal and the delayed clock signal to modify a pulse width of the input clock signal, so as to obtain an output clock signal; and a feedback module (103) configured to determine, according to a pulse width and a target pulse width of the output clock signal, the delay control parameter, and to feed the delay control parameter back to the delay module. A clock signal having various pulse widths can be automatically obtained by means of the above-described pulse width modification process, thus meeting signal pulse width requirements of a digital clock in different situations.

Description

Pulse width correction circuit, pulse width correction method and electronic device

Technical field

The present application relates to signal processing technologies, and in particular, to a pulse width correction circuit, a pulse width correction method, and an electronic device.

Background technique

Quartz crystal oscillator, also known as quartz resonator, referred to as crystal oscillator, is made of quartz crystal sheet with piezoelectric effect. This quartz crystal flake generates mechanical vibration when subjected to an applied alternating electric field. When the frequency of the alternating electric field is the same as the natural frequency of the quartz crystal, the vibration becomes very strong, which is the reaction of the crystal resonance characteristic.

Quartz crystal oscillator is a high-precision and high-stability oscillator, which is widely used in various types of oscillation circuits such as color TVs, computers, remote controllers, etc., and for frequency generators in communication systems to generate clock signals for data processing equipment. . The quartz crystal oscillator can provide the original clock signal for the digital clock, and its output is usually a sine wave or a signal in the form of an approximate sine wave, but the signal of the digital clock is a signal in the form of a rectangular wave, so in order to send the original clock signal to the digital When the clock is used, it is necessary to form a sine wave into a rectangular wave.

However, in some high frequency (tens of MHz) applications, the digital clock has certain requirements on the pulse width of the clock signal, and in the process of forming a sinusoidal wave into a rectangular wave, it is difficult to control the pulse width, especially In the case of low noise requirements while providing a certain noise margin, the control of the pulse width becomes more difficult. Therefore, how to make the pulse width of the clock signal meet the requirements of the digital clock has become an urgent problem to be solved.

Summary of the invention

The present application provides a pulse width correction circuit, a pulse width correction method, and an electronic device to solve the problem that the pulse width of the clock signal received by the existing digital clock cannot meet the requirements.

According to an aspect of the present application, a pulse width correction circuit is provided, including:

a delay module, configured to delay processing the input clock signal according to the delay control parameter to obtain a delayed clock signal;

a logic operation module, configured to logic the input clock signal and the delayed clock signal Performing an operation to correct a pulse width of the input clock signal to obtain an output clock signal;

And a feedback module, configured to determine the delay control parameter according to a pulse width of the output clock signal and a target pulse width, and feed back the delay control parameter to the delay module.

Optionally, the feedback module is further configured to determine a relationship between a pulse width of the output clock signal and a target pulse width, and generate a decision power according to a relationship between a pulse width of the output clock signal and a target pulse width. And determining a delay control parameter based on the determined electrical signal and feeding back the delay control parameter to the delay module.

Optionally, the feedback module includes:

a determining unit, configured to generate a decision electrical signal according to an electrical signal proportional to a pulse width of the output clock signal and a reference electrical signal; wherein the reference electrical signal is determined according to the target pulse width;

And a registering unit, configured to determine a delay control parameter according to the determined electrical signal, and feed back the delay control parameter to the delay module.

Optionally, the determining unit is a comparator, and the comparator is configured to compare an electrical signal proportional to a pulse width of the output clock signal with a reference electrical signal and determine a decision electrical signal.

Optionally, the register unit is a successive approximation register, and the successive approximation register is configured to modify the latched delay control parameter in a successive approximation manner according to the decision electrical signal, and the modified delay control parameter Feedback to the delay module.

Optionally, the feedback module further includes: a pulse width detecting unit, configured to detect a pulse width of the output clock signal, and acquire an electrical signal proportional to a pulse width of the output clock signal.

Optionally, the registering unit is further configured to: when determining that a pulse width of the output clock signal reaches a target pulse width, output an end signal to the pulse width detecting unit and/or the determining unit;

The pulse width detecting unit is further configured to: close the self circuit after receiving the end signal;

The determining unit is further configured to close the circuit after receiving the end signal.

Optionally, the logic operation module is further configured to perform a logical AND operation or a logical OR operation on the input clock signal and the delayed clock signal to obtain the output clock signal.

Optionally, the delay module includes m-channel n-stage delay units, and the m-channel n-stage delay units are sequentially connected in series, and the m-channel n-stage delay unit is configured to input the clock signal according to the delay control parameter. The m-channel n-stage delay processing is performed to obtain an m-channel delayed clock signal; wherein the m and the n are integers greater than or equal to 1.

Optionally, the circuit further includes: a frequency dividing module, configured to perform frequency division processing on the input clock signal to obtain a frequency division clock signal;

The feedback module is further configured to: when the high level of the divided clock signal arrives, according to The pulse width of the output clock signal and the target pulse width determine a delay control parameter and feed back the delay control parameter to the delay module.

In accordance with another aspect of the present application, an electronic device is provided, including a pulse width correction circuit as described above.

According to still another aspect of the present application, a pulse width correction method is provided, including:

Delaying the input clock signal according to the delay control parameter to obtain a delayed clock signal;

Performing a logic operation on the input clock signal and the delayed clock signal to perform pulse width correction on the input clock signal to obtain an output clock signal;

Determining a delay control parameter according to a pulse width of the output clock signal and a target pulse width, and feeding back the delay control parameter.

Optionally, the step of determining a delay control parameter according to a pulse width of the output clock signal and a target pulse width, and feeding back the delay control parameter, includes:

Determining a relationship between a pulse width of the output clock signal and a target pulse width, generating a decision electrical signal according to a relationship between a pulse width of the output clock signal and a target pulse width, and determining a delay control according to the determined electrical signal Parameters and feedback the delay control parameters.

Generating a decision electrical signal according to an electrical signal proportional to a pulse width of the output clock signal and a reference electrical signal; wherein the reference electrical signal is determined according to the target pulse width;

Determining a delay control parameter based on the decision electrical signal and feeding back the delay control parameter.

Optionally, the step of generating a decision electrical signal according to the electrical signal proportional to the pulse width of the output clock signal and the reference electrical signal comprises:

An electrical signal proportional to the pulse width of the output clock signal is compared to a reference electrical signal and a decision electrical signal is determined.

Optionally, the step of determining a delay control parameter according to the decision electrical signal and feeding back the delay control parameter includes:

The latched delay control parameter is corrected in a successive approximation according to the decision electrical signal, and the corrected delay control parameter is fed back.

Optionally, before the step of generating the determining electrical signal according to the electrical signal proportional to the pulse width of the output clock signal and the reference electrical signal, the method further includes:

Detecting a pulse width of the output clock signal to obtain an electrical signal proportional to a pulse width of the output clock signal.

Optionally, the step of determining the delay control parameter according to the pulse width of the output clock signal and the target pulse width, and feeding back the delay control parameter, further includes:

Outputting an end signal when determining that a pulse width of the output clock signal reaches a target pulse width;

After receiving the end signal, stopping performing the operation of detecting a pulse width of the output clock signal to acquire an electrical signal proportional to a pulse width of the output clock signal; and/or,

After receiving the end signal, the operation of generating the decision electrical signal based on the electrical signal proportional to the pulse width of the output clock signal and the reference electrical signal is stopped.

Optionally, the step of performing logic operation on the input clock signal and the delayed clock signal to perform pulse width correction on the input clock signal to obtain an output clock signal includes:

And performing a logical AND operation or a logical OR operation on the input clock signal and the delayed clock signal to obtain the output clock signal.

Optionally, the step of delay processing the input clock signal according to the delay control parameter to obtain a delayed clock signal includes:

Performing m-way n-stage delay processing on the input clock signal according to the delay control parameter to obtain an m-channel delayed clock signal; wherein the m and the n are integers greater than or equal to 1.

Optionally, the method further includes: performing frequency division processing on the input clock signal to obtain a frequency division clock signal;

Determining the delay control parameter according to the pulse width of the output clock signal and the target pulse width, and feeding back the delay control parameter, comprising: when the high level of the divided clock signal arrives, according to the The pulse width of the clock signal and the target pulse width are output, the delay control parameter is determined, and the delay control parameter is fed back.

In the present application, the delayed clock signal is obtained by delay processing the input clock signal, and then the input clock signal and the delayed clock signal are logically operated to correct the pulse width of the input clock signal, so that the pulse width of the output clock signal is obtained after the correction. Finally reach the target pulse width. Therefore, the present application can automatically obtain clock signals of various pulse widths through the above-mentioned pulse width correction process, thereby satisfying the requirements of the digital clock on the signal pulse width in various situations.

DRAWINGS

1 is a structural block diagram of a pulse width correction circuit according to Embodiment 1 of the present application;

2 is a structural block diagram of a pulse width correction circuit according to Embodiment 2 of the present application;

3 is a schematic structural diagram of a pulse width correction circuit according to Embodiment 3 of the present application;

4 is a circuit diagram of an n-stage delay unit according to Embodiment 3 of the present application;

5 is a circuit diagram of a logic operation module according to Embodiment 3 of the present application;

6 is a schematic diagram of logical OR operation of an input clock signal and a delayed clock signal according to Embodiment 3 of the present application;

7 is a schematic diagram of logically ANDing an input clock signal and a delayed clock signal according to Embodiment 3 of the present application;

8 is a circuit diagram of a pulse width detecting unit according to Embodiment 3 of the present application;

9 is a schematic diagram of a correction process for correcting a pulse width of an input clock signal from less than 50% to 50% according to Embodiment 3 of the present application;

10 is a flow chart of steps of a pulse width correction method according to Embodiment 4 of the present application;

FIG. 11 is a flow chart of steps of a pulse width correction method according to Embodiment 5 of the present application.

Detailed ways

In order to make the object, the features and the advantages of the embodiments of the present application more obvious and easy to understand, the technical solutions in the embodiments of the present application are clearly and completely described in the following with reference to the accompanying drawings in the embodiments of the present application. The described embodiments are only a part of the embodiments of the embodiments of the present application, and not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative efforts are within the scope of protection of the embodiments of the present application.

Embodiment 1

Embodiments of the present application can be applied to a shaping circuit after a quartz crystal oscillator. In digital clock applications, a quartz crystal oscillator produces an original clock signal that is shaped by a shaping circuit to form a rectangular wave signal from a sinusoidal signal. In the embodiment of the present application, in order to solve the problem that the pulse width of the rectangular wave signal obtained by the shaping cannot meet the requirement, after the original clock signal is formed into a rectangular wave signal, the pulse width correction circuit further performs pulse width on the rectangular wave signal. Corrections such as widening or narrowing to achieve the desired pulse width.

Referring to FIG. 1, a block diagram of a pulse width correction circuit according to a first embodiment of the present application is shown.

The pulse width correction circuit of this embodiment includes the following modules:

The delay module 101 is configured to perform delay processing on the input clock signal according to the delay control parameter to obtain a delayed clock signal.

In this embodiment, the delay control parameter may include a time delay in delay processing of the input clock signal, the delay control parameter being determined by the feedback module described below and fed back to the delay module.

In this embodiment, the input clock signal is derived from a signal obtained by shaping a sine wave signal generated by a quartz crystal oscillator, which may be a rectangular wave signal.

The input clock signal (that is, the rectangular wave signal described above) is input to the delay module, and the delay clock is used to delay the input clock signal, and the delay processing causes the high level delay of the input clock signal to appear for a period of time, and the delay processing is obtained. Delaying the clock signal, the length of the delay indicates the presence of a high level, the longer the delay time, the later the high level appears. Conversely, the shorter the delay time, the earlier the high level appears, and the length of the delay. The pulse width of the input clock signal is related to the difference between the target pulse widths.

In this embodiment, the reason why the input clock signal is subjected to delay processing is to correct the pulse width of the input clock signal by logically calculating the input clock signal and other clock signals whose clock phases are different from the input clock signal. And by delay processing the input clock signal, other clock signals whose clock phase is different from the input clock signal can be obtained.

In this embodiment, the delay module is, for example, a circuit structure constructed by a plurality of delay subunits.

The logic operation module 102 is configured to perform logic operations on the input clock signal and the delayed clock signal to perform pulse width correction on the input clock signal to obtain an output clock signal.

When the clock signal with different clock phases is logically operated, the pulse width of the clock signal changes. Therefore, the input clock signal and the delayed clock signal are logically operated to obtain an output clock signal, and the output clock signal is low-voltage due to a logic operation, and a part of the input clock signal is turned into a low level. Flat, or part of the low level will become high level, so the pulse width of the input clock signal is corrected by the logic operation process, and the output clock signal is obtained by performing pulse width correction on the input clock signal for this time. signal.

In this embodiment, the logical operations are, for example, logical OR or logical AND.

In this embodiment, the logic module is, for example, a circuit structure constructed by a NAND gate.

The feedback module 103 is configured to determine a delay control parameter according to a pulse width of the output clock signal and a target pulse width, and feed back the delay control parameter to the delay module.

After the correction of the logic operation module, the output clock signal is obtained, and then the feedback module determines the delay control parameter according to the relationship between the pulse width of the output clock signal and the target pulse width, so that the delay module and the logic operation module continue to perform the input clock signal. The pulse width is corrected until the pulse width of the output clock signal reaches the target pulse width.

The relationship between the pulse width of the output clock signal and the target pulse width can be expressed by the difference between the two, for example, when the difference between the pulse width of the output clock signal and the target pulse width is larger, the delay control parameter includes The greater the delay time, the more the difference between the pulse width of the output clock signal and the target pulse width The delay time included in the delay control parameter is smaller.

In this embodiment, the feedback module is, for example, a circuit structure constructed by a pulse width detecting circuit, a comparator, and a register.

In the embodiment of the present application, the delayed clock signal is obtained by delay processing the input clock signal, and then the input clock signal and the delayed clock signal are logically operated, thereby correcting the pulse width of the input clock signal, so as to obtain the output clock signal after the correction. The pulse width eventually reaches the target pulse width. Therefore, the embodiment of the present application can automatically obtain clock signals of various pulse widths through the above-mentioned pulse width correction process, thereby satisfying the requirements of the digital clock on the signal pulse width in various situations.

Embodiment 2

Referring to FIG. 2, a block diagram of a pulse width correction circuit according to a second embodiment of the present application is shown.

The delay module 201 is configured to delay processing the input clock signal according to the delay control parameter to obtain a delayed clock signal.

The delay control parameter includes how long the delay needs to be obtained, and the delay control parameter is obtained by a feedback module described later, which will be specifically introduced in the following feedback module. The delay module delays the input clock signal by the time indicated by the delay control parameter to obtain a delayed clock signal.

In this embodiment, the related description of the delay processing is similar to the first embodiment.

The logic operation module 202 is configured to perform logic operations on the input clock signal and the delayed clock signal to perform pulse width correction on the input clock signal to obtain an output clock signal.

In the embodiment of the present application, the logic operation module 202 is further configured to perform a logical AND operation or a logical OR operation on the input clock signal and the delayed clock signal to obtain an output clock signal. For example, in a specific application scenario, by logically ANDing the input clock signal and the delayed clock signal, a low level is obtained by logically ANDing the low level and the high level, so that part of the input clock signal is high. Leveling to a low level, thereby narrowing the pulse width of the input clock signal; for example, in another specific application scenario, by logically ORing the input clock signal with the delayed clock signal, due to low level and high power A logic OR operation is performed to obtain a high level, so that a portion of the low level of the input clock signal becomes a high level, thereby achieving widening of the pulse width of the input clock signal. For the specific operation, the logic operation module may be determined according to the operation control parameter, and the operation control parameter is used to indicate which logic operation is performed, and the operation control parameter is obtained by the feedback module described later, which will be specifically in the subsequent feedback module. Introduction.

The feedback module 203 is configured to determine a relationship between a pulse width of the output clock signal and a target pulse width, and a root A decision electrical signal is generated according to a relationship between a pulse width of the output clock signal and a target pulse width, a delay control parameter is determined according to the determined electrical signal, and the delay control parameter is fed back to the delay module.

In this embodiment, the feedback module 203 may include the following units:

The pulse width detecting unit 2031 is configured to detect a pulse width of the output clock signal and acquire an electrical signal proportional to a pulse width of the output clock signal.

The determining unit 2032 is configured to generate a decision electrical signal according to the electrical signal proportional to the pulse width of the output clock signal and the reference electrical signal; wherein the reference electrical signal is determined according to the target pulse width.

In a preferred form, decision unit 2032 is a comparator for comparing an electrical signal proportional to the pulse width of the output clock signal with a reference electrical signal to determine a decision electrical signal.

In order to more conveniently compare the pulse width of the output clock signal with the target pulse width, in the embodiment of the present application, the pulse width and the target pulse width of the output clock signal are respectively converted into electrical signals related thereto, that is, as described above. The pulse width of the output clock signal is converted into an electrical signal proportional to it, the target pulse width is converted into a reference electrical signal, and then the comparison between the electrical signals is performed, and the process is simpler.

The registering unit 2033 is configured to determine a delay control parameter according to the determined electrical signal, and feed back the delay control parameter to the delay module.

In a preferred mode, the register unit 2033 is a successive approximation register for correcting the latched delay control parameter in a successive approximation according to the decision electrical signal, and feeding back the modified delay control parameter to the delay. Module. Specifically, a delay control parameter is latched in the successive approximation register, the delay control parameter includes a plurality of binary bits, and the successive approximation register receives the decision electrical signal outputted by the decision unit, and the decision electrical signal is before the latched The clocked decision electrical signals are compared. If the two are the same, the successive approximation register looks up the binary bit of 1 from the latched delay control parameter and sets the next binary bit of the found binary bit to 1; If the two are different, the successive approximation register looks for a binary bit of 1 from the latched delay control parameter, finds the binary position as 0, and sets the next binary bit of the found binary bit to 1; The successive approximation register does not latch the decision electrical signal after receiving the decision electrical signal output by the decision unit, and directly sets the highest position of the delay control parameter to 1.

In the embodiment of the present application, the feedback module 203 is further configured to determine an operation control parameter according to a pulse width of the output clock signal of the first clock cycle and a target pulse width, and feed back the operation control parameter to the logic operation module. Specifically, the decision electrical signal is generated according to the pulse width of the output clock signal of the first clock cycle and the target pulse width, the operational control parameter is determined according to the determined electrical signal, and the operational control parameter is fed back to the logical operation module. Specifically, if the decision electrical signal indicates that the electrical signal proportional to the pulse width of the output clock signal is less than the reference electrical signal, determining the operational control parameter indication to perform a logical OR An operation; if the decision electrical signal indicates that the electrical signal proportional to the pulse width of the output clock signal is greater than the reference electrical signal, determining that the operational control parameter indicates a logical AND operation.

In a preferred manner, the register unit 2033 is further configured to output an end signal to the pulse width detecting unit and/or the determining unit when determining that the pulse width of the output clock signal reaches the target pulse width. Here, "and/or" means that only the end signal can be output to the pulse width detecting unit, or only the end signal can be output to the decision unit, and the end signal can be output to the pulse width detecting unit and the decision unit. The registering unit may determine whether the pulse width of the output clock signal reaches the target pulse width according to the latched delay control parameter, and the delay control parameter includes a plurality of binary bits. When each binary bit is corrected, the pulse of the output clock signal may be determined. The width reaches the target pulse width. The pulse width detecting unit 2031 is further configured to turn off the self circuit after receiving the end signal. The determining unit 2032 is further configured to close the circuit after receiving the end signal.

After the pulse width of the output clock signal reaches the target pulse width, the functions of the pulse width detecting unit and the determining unit need not be performed, so that at least one of the pulse width detecting unit and the determining unit can be turned off, thereby further saving the embodiment of the present application. The power consumption of the pulse width correction circuit.

In a preferred mode, the pulse width correction circuit of the embodiment of the present application further includes: a frequency dividing module 204, configured to perform frequency division processing on the input clock signal to obtain a frequency-divided clock signal; and a feedback module, further used to divide the frequency When the high level of the clock signal arrives, the delay control parameter is determined according to the pulse width of the output clock signal and the target pulse width, and the delay control parameter is fed back to the delay module.

For some slow response pulse width detecting units, the frequency dividing module may be added, and the input clock signal is input to the frequency dividing module, and the frequency dividing module divides the input clock signal according to the set frequency dividing coefficient, and the obtained frequency dividing frequency is obtained. The clock signal is output to a feedback module, which is used to indicate when the feedback module performs related operations. For the setting of the frequency division coefficient, those skilled in the art can set any suitable value according to the actual situation of the response speed of the pulse width detecting unit. For example, if the response speed of the pulse width detecting unit is slow, the frequency dividing coefficient is set. If the response speed of the pulse width detecting unit is fast, the frequency dividing coefficient is set to be small. The specific value is not limited in the embodiment of the present application.

The embodiment of the present application can correct the pulse width of the input clock signal to the required pulse width according to the requirements of the digital clock, and the correction is easier to control and more accurate. Moreover, the power consumption of the circuit can be further reduced by turning off part of the circuit after the correction is completed.

Embodiment 3

Referring to FIG. 3, a schematic structural diagram of a pulse width correction circuit according to Embodiment 3 of the present application is shown.

The delay module 301 includes an m-channel n-stage delay unit (n-stage delay unit 1-n-stage delay unit m), and the m-channel n-stage delay unit is configured to perform m-path on the input clock signal (A0) according to the delay control parameter. The stage delay processing results in an m-way delayed clock signal (A1-Am). The m-channel n-stage delay units are connected in series, and the input clock signal is input to the first-stage n-stage delay unit 1, and the output of the first-stage n-stage delay unit 1 is input to the second-channel n-stage delay unit 2, and the second path The output of the n-stage delay unit 2 is input to the third-stage n-stage delay unit 3, and so on, and each of the n-stage delay units delays the respective inputs in accordance with the delay control parameters. Wherein, m and n are integers greater than or equal to 1. For a specific value of m and n, a person skilled in the art can set any suitable value according to the actual situation, and the larger the m and n is, the more accurate the correction result is. The specific numerical values of m and n are not limited.

Referring to FIG. 4, a circuit diagram of an n-stage delay unit of Embodiment 3 of the present application is shown. The n-stage delay unit includes n clock buffers (CB0-CBn-1), n capacitors (C0-Cn-1), and n switches (S0-Sn-1), n capacitors (C0-Cn-1) All are connected to a logic 0 level, a clock buffer and a capacitor form an RC circuit, each RC circuit is connected in series, and each RC circuit is controlled by a corresponding switch, wherein the B[0] control switch S0 of the successive approximation register , B[1] controls switch S1, and so on, and B[n-1] controls switch Sn-1. The input clock signal is input from the clock buffer CB0, and the delayed clock signal is output from the clock buffer CBn-1. In the embodiment of the present application, in order to facilitate the control, the delay of each level may be set to increase by a factor of two.

The logic operation module 302 is configured to perform logic operations on the input clock signal A0 and the m-channel delay clock signal (A1-Am) according to the operation control parameter to perform pulse width correction on the input clock signal to obtain an output clock signal Y.

Referring to FIG. 5, a circuit diagram of a logic operation module according to Embodiment 3 of the present application is shown. The logic operation module includes two AND gates (AND gate 1 and AND gate 2) and two OR gates (or gate 1 and OR gate 2), input clock signal A0 and m way delay clock signal A1-Am as AND gate 1 and The input of the OR gate 1, the output of the OR gate 1 and the operational control parameter S as the input of the AND gate 2, the output of the AND gate 1 and the output of the AND gate 2 as the input of the OR gate 2, or the output of the OR gate 2 is the output clock signal Y. The Boolean expression of the logical budget module may be Y=(A0|A1...|Am)&S|A0&A1...&Am, performing a logical OR operation when S=1, and performing a logical AND operation when S=0. It should be noted that a plurality of Boolean expressions can implement the function in a specific implementation, and the specific form of the Boolean expression is not limited in the embodiment of the present application.

Referring to FIG. 6, a schematic diagram of logically ORing an input clock signal and a delayed clock signal according to Embodiment 3 of the present application is shown. In the figure, t is the delay time, S=1, Y=A0|A1|A2|A3, and the input clock signal A0 and the delayed clock signal A1-A3 are logically ORed, and the obtained output clock signal Y The pulse width is wider than the input clock signal A0.

Referring to FIG. 7, a schematic diagram of logically ANDing an input clock signal and a delayed clock signal is shown in Embodiment 3 of the present application. In the figure, t is the delay time, S=0, Y=A0&A1&A2&A3, the input clock signal A0 and the delayed clock signal A1-A3 are logically ANDed, and the obtained output clock signal Y is narrower than the pulse width of the input clock signal A0. .

The pulse width detecting unit 303 is configured to detect a pulse width of the output clock signal Y and acquire a voltage Vpw proportional to a pulse width of the output clock signal.

Referring to FIG. 8, a circuit diagram of a pulse width detecting unit of Embodiment 3 of the present application is shown. The pulse width detecting unit includes a clock buffer CB, a resistor R and a capacitor C. The pulse width detecting unit is equivalent to a low pass filter, and the input clock signal is used as an input of the clock buffer CB, and the output of the clock buffer CB and the resistor R are One end is connected, the other end of the resistor R is connected to one end of the capacitor C, the other end of the capacitor C is connected to a logic 0 level, and the voltage Vpw is outputted between the resistor R and the capacitor C. In order to obtain the voltage Vpw, the embodiment of the present application can set the time constant of the clock buffer CB to be much longer than (at least 10 times more) the period of the input clock signal.

The voltage comparator 304 is configured to compare the voltage Vpw proportional to the pulse width of the output clock signal with the reference voltage Vr to determine the decision voltage Vcp. In the embodiment of the present application, the reference voltage Vr can be obtained according to the following formula: Vr=J(Vh-Vl), where J is the target pulse width, Vh is the logic level of the clock signal, and Vl is the logic level of the clock signal. For a specific circuit structure of the voltage comparator, a person skilled in the art can set any applicable structure according to the actual situation, and the embodiment of the present application will not be described in detail herein.

The n+1 bit successive approximation register 305 is configured to modify the latched delay control parameter in a successive approximation according to the decision voltage Vcp, and feed back the modified delay control parameter to the delay module. And determining the operation control parameter S according to the decision voltage of the first clock cycle, and feeding back the operation control parameter S to the logic operation module.

The output parameter of the n+1 bit successive approximation register includes n+1 binary bits (B[n:0]), wherein the successive approximation register outputs the highest bit B[n] as an operation control parameter to the logic operation module, and other bits B[n-1:0] is output as a delay control parameter to the n-stage delay unit. For a specific circuit structure of the successive approximation register, a person skilled in the art can set any applicable structure according to the actual situation, and the embodiment of the present application will not be described in detail herein.

The frequency divider 306 is configured to perform frequency division processing on the input clock signal according to the set frequency division coefficient, and output the obtained frequency division clock signal to the n+1 bit successive approximation register. When the high level of the divided clock signal arrives, the n+1 bit successive approximation register is instructed to begin the corresponding operation. For the divider The physical circuit structure, any suitable structure can be set by a person skilled in the art according to the actual situation, and the embodiments of the present application are not described in detail herein.

In order to facilitate the understanding of the working principle of the embodiment of the present application, the following is a modification process of correcting the pulse width of the input clock signal from less than 50% to 50% by taking m=3 and n=3 as examples. Set the delay time of 1-3 steps to 1td, 2td, 4td, td is the unit delay time, the reference voltage Vr=(Vh-Vl)/2, where Vh is the logic level of the clock signal, and Vl is the clock signal. The logic level is 0, and the division ratio of the divider is set to 1 (no division), and the pulse width detection module can be established in one clock cycle.

Referring to FIG. 9, a schematic diagram of a correction process for correcting the pulse width of the input clock signal from less than 50% to 50% is shown in the third embodiment of the present application.

In the initial case, the output of the successive approximation register is all 0, all switches in the n-stage delay unit are turned on, and the m-channel n-stage delay unit has no delay.

In the first clock cycle, since there are no delays in the m-channel n-stage delay units, the clock phases of A0-A3 are the same, and the output clock signal Y is exactly equal to the input clock signal A0. Then, the output clock signal Y is detected by the pulse width detecting unit to obtain a voltage Vpw proportional thereto. Since the pulse width of the output clock signal is less than 50%, the voltage comparator compares the voltage Vpw with the reference voltage Vr to obtain Vpw<Vr, and thus The voltage comparator outputs a decision voltage Vcp=1, and the successive approximation register sets the highest bit B[3] to 1, then B[3:0] is a 4-bit binary 4'b1000, and the decision voltage Vcp=1 is latched.

In the second clock cycle, since Vcp=1, the successive approximation register sets the second highest bit B[2], then B[3:0] is the 4-bit binary 4'b1100, so the delay of A1-A3 is 4td. , 8td, 12td, A0-A4 are performed or operated such that the pulse width of the output clock signal Y is wider than the input clock signal A0. Then, the output clock signal Y is detected by the pulse width detecting unit to obtain a voltage Vpw proportional thereto. Since the pulse width of the output clock signal is greater than 50%, the voltage comparator compares the voltage Vpw with the reference voltage Vr to obtain Vpw>Vr, and thus The voltage comparator outputs a decision voltage Vcp=0, and the successive approximation register latches the decision voltage Vcp=0.

In the third clock cycle, since Vcp=0, the successive approximation register sets B[2] to 0 and B[1] to 1, then B[3:0] is 4-bit binary 4'b1010, so A1- The delay of A3 is 2td, 4td, 6td, and A0-A4 is performed or operated. Then, the output clock signal Y is detected by the pulse width detecting unit to obtain a voltage Vpw proportional thereto. Since the pulse width of the output clock signal is greater than 50%, the voltage comparator compares the voltage Vpw with the reference voltage Vr to obtain Vpw>Vr, and thus The voltage comparator outputs a decision voltage Vcp=0, and the successive approximation register latches the decision voltage Vcp=0.

In the 4th clock cycle, since Vcp=0, the successive approximation register sets B[1] to 0, which will be B[0]. When set to 1, B[3:0] is a 4-bit binary 4'b1001, so the delays of A1-A3 are 1td, 2td, 3td, respectively, and A0-A4 is ORed. Then, the output clock signal Y is detected by the pulse width detecting unit to obtain a voltage Vpw proportional thereto. Since the pulse width of the output clock signal is less than 50%, the voltage comparator compares the voltage Vpw with the reference voltage Vr to obtain Vpw<Vr, and thus The voltage comparator outputs a decision voltage Vcp=1, and the successive approximation register latches the decision voltage Vcp=1. Moreover, in the clock cycle successive approximation register to determine that each binary bit has been corrected, it can be determined that the pulse width of the output clock signal reaches the target pulse width, and then continues to input the parameter according to B[3:0]=1001. The pulse width of the clock signal is corrected.

The embodiment of the present application provides a new circuit structure, which implements correction of the pulse width of the input clock signal according to the requirement of the digital clock, and delays the input clock signal by the multi-channel multi-stage delay unit, so that the correction is more accurate. . Embodiments of the present application can automatically and accurately correct the pulse width to an expected value with little increase in power consumption.

In addition, an embodiment of the present application further provides an electronic device including the pulse width correction circuit described in the foregoing embodiment. The electronic device obtains a delayed clock signal by delay processing the input clock signal, and performs a logic operation on the input clock signal and the delayed clock signal to correct the pulse width of the input clock signal, so that the pulse of the output clock signal is obtained after the correction. The width eventually reaches the target pulse width. Therefore, the pulse width correction process can obtain clock signals of various pulse widths, thereby meeting the requirements of the digital clock on the signal pulse width in various situations.

Embodiment 4

Referring to FIG. 10, a flow chart of steps of a pulse width correction method according to Embodiment 4 of the present application is shown.

The pulse width correction method of the embodiment of the present application includes the following steps:

Step 1001: delay processing the input clock signal according to the delay control parameter to obtain a delayed clock signal.

In step 1002, the input clock signal and the delayed clock signal are logically operated to correct the pulse width of the input clock signal to obtain an output clock signal.

Step 1003: Determine a delay control parameter according to a pulse width of the output clock signal and a target pulse width, and feed back the delay control parameter.

Embodiment 5

Referring to FIG. 11, a flow chart of steps of a pulse width correction method according to Embodiment 5 of the present application is shown.

Step 1101: delay processing the input clock signal according to the delay control parameter to obtain a delayed clock signal.

In a preferred mode, step 1101 includes performing m-way n-stage delay processing on the input clock signal according to the delay control parameter to obtain an m-channel delayed clock signal.

In step 1102, the input clock signal and the delayed clock signal are logically operated to correct the pulse width of the input clock signal to obtain an output clock signal.

In a preferred manner, step 1102 includes performing a logical AND or logical OR operation on the input clock signal and the delayed clock signal to obtain an output clock signal.

Step 1103, performing frequency division processing on the input clock signal to obtain a frequency division clock signal.

Step 1104: When the high level of the divided clock signal arrives, the delay control parameter is determined according to the pulse width of the output clock signal and the target pulse width, and the delay control parameter is fed back.

It should be noted that the step 1104 described below refers to a process of determining a delay control parameter according to the pulse width of the output clock signal and the target pulse width, and feeding back the delay control parameter.

In the embodiment of the present application, the step 1104 specifically includes: determining a relationship between a pulse width of the output clock signal and a target pulse width, and generating a decision electrical signal according to a relationship between a pulse width of the output clock signal and a target pulse width, and The delay control parameter is determined according to the determined electrical signal, and the delay control parameter is fed back.

In a preferred mode, step 1104 includes: detecting a pulse width of the output clock signal, acquiring an electrical signal proportional to a pulse width of the output clock signal; and calculating an electrical signal proportional to a pulse width of the output clock signal and a reference electrical signal And generating a decision electrical signal; wherein the reference electrical signal is determined according to the target pulse width; determining the delay control parameter according to the determined electrical signal, and feeding back the delay control parameter.

The step of generating a decision electrical signal according to the electrical signal proportional to the pulse width of the output clock signal and the reference electrical signal specifically includes: comparing the electrical signal proportional to the pulse width of the output clock signal with the reference electrical signal, Determine the decision electrical signal. The step of determining the delay control parameter according to the determined electrical signal and feeding back the delay control parameter comprises: correcting the latched delay control parameter in a successive approximation according to the determined electrical signal, and feeding back the corrected delay control parameter.

In a preferred manner, step 1104 further includes: determining that the pulse width of the output clock signal arrives When the target pulse width is output, the end signal is output; after receiving the end signal, the execution of detecting the pulse width of the output clock signal is performed, and an operation of obtaining an electrical signal proportional to the pulse width of the output clock signal is performed; and/or, at the end of the reception After the signal, the operation of generating the decision electrical signal based on the electrical signal proportional to the pulse width of the output clock signal and the reference electrical signal is stopped.

The device embodiments described above are merely illustrative, wherein the modules described as separate components may or may not be physically separate, and the components displayed as modules may or may not be physical modules, ie may be located A place, or it can be distributed to multiple network modules. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of the embodiment. Those of ordinary skill in the art can understand and implement without deliberate labor.

Through the description of the above embodiments, those skilled in the art can clearly understand that the various embodiments can be implemented by means of software plus a necessary general hardware platform, and of course, by hardware. Based on such understanding, portions of the above technical solutions that contribute substantially or to the prior art may be embodied in the form of a software product that may be stored in a computer readable storage medium, the computer readable record The medium includes any mechanism for storing or transmitting information in a form readable by a computer (eg, a computer). For example, a machine-readable medium includes read only memory (ROM), random access memory (RAM), magnetic disk storage media, optical storage media, flash storage media, electrical, optical, acoustic, or other forms of propagation signals (eg, carrier waves) , an infrared signal, a digital signal, etc., etc., the computer software product comprising instructions for causing a computer device (which may be a personal computer, server, or network device, etc.) to perform the various embodiments or portions of the embodiments described Methods.

Finally, it should be noted that the above embodiments are only used to explain the technical solutions of the embodiments of the present application, and are not limited thereto; although the present application is described in detail with reference to the foregoing embodiments, those skilled in the art should understand that The technical solutions described in the foregoing embodiments may be modified, or some of the technical features may be equivalently replaced; and the modifications or substitutions do not deviate from the spirit of the technical solutions of the embodiments of the present application. range.

Claims

A pulse width correction circuit, characterized in that the circuit comprises:

a delay module, configured to delay processing the input clock signal according to the delay control parameter to obtain a delayed clock signal;

a logic operation module, configured to perform logic operation on the input clock signal and the delayed clock signal to perform pulse width correction on the input clock signal to obtain an output clock signal;

And a feedback module, configured to determine the delay control parameter according to a pulse width of the output clock signal and a target pulse width, and feed back the delay control parameter to the delay module.
The circuit according to claim 1, wherein the feedback module is further configured to determine a relationship between a pulse width of the output clock signal and a target pulse width, according to a pulse width and a target of the output clock signal The relationship between the pulse widths generates a decision electrical signal and determines a delay control parameter based on the decision electrical signal and feeds back the delay control parameter to the delay module.
The circuit of claim 1 wherein said feedback module comprises:

a determining unit, configured to generate a decision electrical signal according to an electrical signal proportional to a pulse width of the output clock signal and a reference electrical signal; wherein the reference electrical signal is determined according to the target pulse width;

And a registering unit, configured to determine a delay control parameter according to the determined electrical signal, and feed back the delay control parameter to the delay module.
The circuit according to claim 3, wherein said decision unit is a comparator for comparing an electrical signal proportional to a pulse width of said output clock signal with a reference electrical signal and determining a decision electric signal.
The circuit of claim 3 wherein said register unit is a successive approximation register, said successive approximation register operative to modify the latched delay control parameter in a successive approximation based on said decision electrical signal, and The corrected delay control parameter is fed back to the delay module.
The circuit of claim 3, wherein the feedback module further comprises:

And a pulse width detecting unit configured to detect a pulse width of the output clock signal and acquire an electrical signal proportional to a pulse width of the output clock signal.
The circuit according to claim 6, wherein the registering unit is further configured to output an end signal to the pulse width detecting unit and/or when determining that a pulse width of the output clock signal reaches a target pulse width The decision unit;

The pulse width detecting unit is further configured to: close the self circuit after receiving the end signal;

The determining unit is further configured to close the circuit after receiving the end signal.
The circuit according to claim 1, wherein the logic operation module is further configured to perform a logical AND operation or a logical OR operation on the input clock signal and the delayed clock signal to obtain the output clock signal. .
The circuit according to claim 1, wherein said delay module comprises m-way n-stage delay units, said m-channel n-stage delay units being connected in series,

The m-channel n-stage delay unit is configured to perform m-way n-stage delay processing on the input clock signal according to the delay control parameter to obtain an m-channel delayed clock signal;

Wherein m and the n are integers greater than or equal to 1.
The circuit of claim 1 wherein:

The circuit further includes: a frequency dividing module, configured to perform frequency division processing on the input clock signal to obtain a frequency divided clock signal;

The feedback module is further configured to: when a high level of the divided clock signal arrives, determine a delay control parameter according to a pulse width of the output clock signal and a target pulse width, and feed back the delay control parameter to The delay module.
An electronic device comprising the pulse width correction circuit according to any one of claims 1 to 10.
A pulse width correction method, the method comprising:

Delaying the input clock signal according to the delay control parameter to obtain a delayed clock signal;

Performing a logic operation on the input clock signal and the delayed clock signal to perform pulse width correction on the input clock signal to obtain an output clock signal;

Determining a delay control parameter according to a pulse width of the output clock signal and a target pulse width, and feeding back the delay control parameter.
The method according to claim 12, wherein the step of determining a delay control parameter according to a pulse width of the output clock signal and a target pulse width, and feeding back the delay control parameter comprises:

Determining a relationship between a pulse width of the output clock signal and a target pulse width, generating a decision electrical signal according to a relationship between a pulse width of the output clock signal and a target pulse width, and determining a delay control according to the determined electrical signal Parameters and feedback the delay control parameters.
The method according to claim 12, wherein the step of determining a delay control parameter according to a pulse width of the output clock signal and a target pulse width, and feeding back the delay control parameter comprises:

Generating a decision electrical signal according to an electrical signal proportional to a pulse width of the output clock signal and a reference electrical signal; wherein the reference electrical signal is determined according to the target pulse width;

Determining a delay control parameter based on the decision electrical signal and feeding back the delay control parameter.
The method according to claim 14, wherein said step of generating a decision electrical signal based on an electrical signal proportional to a pulse width of said output clock signal and a reference electrical signal comprises:

An electrical signal proportional to the pulse width of the output clock signal is compared to a reference electrical signal and a decision electrical signal is determined.
The method according to claim 14, wherein the step of determining a delay control parameter according to the decision electrical signal and feeding back the delay control parameter comprises:

The latched delay control parameter is corrected in a successive approximation according to the decision electrical signal, and the corrected delay control parameter is fed back.
The method according to claim 14, wherein before the step of generating the decision electrical signal based on the electrical signal proportional to the pulse width of the output clock signal and the reference electrical signal, the method further comprises:

Detecting a pulse width of the output clock signal to obtain an electrical signal proportional to a pulse width of the output clock signal.
The method according to claim 17, wherein the step of determining a delay control parameter and feeding back the delay control parameter according to a pulse width of the output clock signal and a target pulse width, further comprising:

Outputting an end signal when determining that a pulse width of the output clock signal reaches a target pulse width;

After receiving the end signal, stopping performing the operation of detecting a pulse width of the output clock signal to acquire an electrical signal proportional to a pulse width of the output clock signal; and/or,

After receiving the end signal, the operation of generating the decision electrical signal based on the electrical signal proportional to the pulse width of the output clock signal and the reference electrical signal is stopped.
The method according to claim 12, wherein said step of logically operating said input clock signal and said delayed clock signal to perform pulse width correction on said input clock signal to obtain an output clock signal ,include:

And performing a logical AND operation or a logical OR operation on the input clock signal and the delayed clock signal to obtain the output clock signal.
The method according to claim 12, wherein the step of delaying the input clock signal according to the delay control parameter to obtain a delayed clock signal comprises:

Performing m-way n-stage delay processing on the input clock signal according to the delay control parameter to obtain an m-channel delayed clock signal; wherein the m and the n are integers greater than or equal to 1.
The method of claim 12, wherein the method further comprises:

Performing frequency division processing on the input clock signal to obtain a frequency division clock signal;

Determining the delay control parameter according to the pulse width of the output clock signal and the target pulse width, and feeding back the delay control parameter, comprising: when the high level of the divided clock signal arrives, according to the The pulse width of the clock signal and the target pulse width are output, the delay control parameter is determined, and the delay control parameter is fed back.