CN105389612A - Circuit and method for realizing reverse link frequency in electronic tag chip - Google Patents

Abstract

The invention, which belongs to the technical field of radio frequency identification, particularly relates to a circuit and method for realizing a reverse link frequency in an electronic tag chip. The circuit structure consists of a clock generating circuit, a power consumption management circuit, a command parsing circuit and a frequency dividing circuit. The clock generating circuit is used for generating a clock signal; the power consumption management circuit is used for generating a control signal; the command parsing circuit provides a reverse link rate factor and inputs the factor into the frequency dividing circuit for processing; and the frequency dividing circuit outputs a reverse link frequency. The method includes the steps that: S1, after power-on and reset operations of a tag chip circuit, the clock generating circuit outputs a main clock; S2, when the command parsing circuit receives a query command, a parameter in the query command is parsed to obtain a reverse link rate factor; and S3, the frequency dividing circuit carries out integer frequency dividing under control of a power consumption management module to obtain a reverse link frequency. The realization process is simple and less resources are consumed. Besides, a low power consumption requirement in the passive ultra-high-frequency tag chip design is met.

Description

A kind of circuit for realizing reverse link frequencies in electronic label chip and method

Technical field

The invention belongs to technical field of RFID, being specifically related to a kind of circuit for realizing reverse link frequencies in electronic label chip and method.

Technical background

In recent years, the feature such as super high frequency radio frequency recognition technology has far distance automatic identification, performance reads multiple label, can repeatedly read and write, the memory capacity of data is large, easy to use, reliable, is just entering the high speed development stage under the promotion of countries in the world.Because the cost of passive tag chip is constantly reducing, the application threshold of super high frequency radio frequency recognition technology is also in reduction, its range of application progressively relates to car application from early stage, expand the national economy fields such as modern logistics, ecommerce, the production automation and military management to, become a kind of technology of the supreme arrogance of a person with great power.In order to develop super high frequency radio frequency recognition technology better, and rank among the prostatitis of world development, China has put into effect standard---and super high frequency radio frequency identification national standard " infotech radio-frequency (RF) identification 800/900/MHz air interface protocol " (hereinafter referred to national standard), promotes the development of super high frequency radio frequency recognition technology.In super high frequency radio frequency identification national standard " infotech radio-frequency (RF) identification 800/900MHz air interface protocol ", regulation is made to label reverse link (that is: label is to read write line) communication frequency.Reverse link frequencies is too high or too low, exceeds frequency error range, violates the requirement meeting protocol conformance, and the communication of label chip and read write line must occur mistake.Solve the problem of implementation of reverse link frequencies in passive HF radio-frequency (RF) identification (UHFRFID) label chip, be key one ring ensureing that label chip can normally work, its performance obtains certain lifting on this basis.

Summary of the invention

For above-mentioned technical matters, the present invention proposes a kind of circuit for realizing reverse link frequencies in electronic label chip and method, ensure that the stability of reverse link frequencies, concrete technical scheme is as follows:

A kind of circuit realizing reverse link frequencies in electronic label chip, comprise clock generation circuit, power consumption management circuit, command analysis circuit and frequency dividing circuit, the control signal that described clock generation circuit clocking, described power consumption management circuit produce, described command analysis circuit provide the reverse link rate factor to be input in frequency dividing circuit respectively and process, and export reverse link frequencies by frequency dividing circuit.

Present invention also offers a kind of method realizing reverse link frequencies in electronic label chip, adopt the above-mentioned circuit realizing reverse link frequencies in electronic label chip, comprise the following steps:

(S1) after realizing the circuit electrification reset of reverse link frequencies in electronic label chip, clock generation circuit is started working, the major clock (T of output _cLK), command analysis circuit is in the state of wait-receiving mode order;

(S2) when receiving querying command, command analysis circuit is started working, and obtains the reverse link rate factor by the parameter of resolving in querying command;

(S3) frequency dividing circuit is under the control of power managed module, according to the reverse link rate factor, obtain divide ratio in conjunction with the reference time (Tc) in forward link and calibration symbol two (Cal_2), carry out integral frequency divisioil, obtain reverse link frequencies.

The detailed process of described step (S3) is: clock generation circuit provides major clock T _clk, command analysis circuit provides reverse link factor K, and frequency dividing circuit produces Frequency Dividing Factor n, obtains Reverse Link Clock T according to following formula _bLF=n × T _clk, obtain reverse link frequencies BLF=1/T _bLF.

The method applied in the present invention, has the following advantages relative to existing technology: 1. fully take into account the personal error, quantization error, frequency division error etc. that exist in implementation procedure, closer to the practical work process of label chip.2. implementation procedure is simple, resource consumption is few, less demanding to clock accuracy, and not needing additionally increases clock calibration circuit, has high stability, meets the low-power consumption requirement in the design of passive ultra-high frequency label chip in addition.3., compared in existing design, reduce clock jitter by designing high-precision clock circuit, and then realize reverse link communication speed.The present invention adopts a kind of circuit for realizing reverse link frequencies in electronic label chip and method, less demanding to major clock precision, even if when not having clock calibration circuit to calibrate major clock, also the stability of reverse link frequencies can be guaranteed, reverse frequency error does not exceed in the scope of regulation, and reverse link communication is normally carried out.

Accompanying drawing explanation

Fig. 1 is realizing circuit structural representation of the present invention;

Fig. 2 is the process flow diagram of implementation method in the present invention.

Embodiment

Below, the present invention will be described with specific embodiment by reference to the accompanying drawings.

As shown in Figure 1, a kind of circuit realizing reverse link frequencies in label chip, comprises clock generation circuit, power consumption management circuit, command analysis circuit and frequency dividing circuit four circuit.Clock generation circuit provides major clock T _clk, power managed module produces control signal en_div, and command analysis module provides reverse link rate factor K, produces reverse link frequencies BLF after these signal input frequency dividing circuits.

Clock generation circuit: clock generation circuit belongs to Analog Circuit Design part, the clock frequency that power consumption and circuit due to digital circuit adopt is directly proportional, and in usual design process, needs to design enough low frequency clocks, can reduce power consumption; In addition, because ensureing that read write line is to the communication of label and the normal work of forward link and the requirement of protocol conformance, frequency again can not be too low.In the present embodiment, electronic label chip adopts the clock of 1.92MHz.Due to not high to major clock accuracy requirement, clock generation circuit adopts the common type such as relaxation osillator, and its clock frequency produced is subject to the impact of the factors such as process deviation, temperature, voltage, and deviation is ± 20%;

Power consumption management circuit: power consumption management circuit belongs to Design of Digital Circuit part, object control effectively to the enable signal of each built-up circuit, makes resource optimization, lower power consumption;

Command analysis circuit: command analysis circuit belongs to Design of Digital Circuit part, plays an auxiliary effect in the present invention, extracts and preserves parameter in querying command (QUERY);

Frequency dividing circuit: frequency dividing circuit belongs to Design of Digital Circuit part is the core in the present invention; The divide ratio (n) obtained according to what follows implementation method is to the output major clock (T of clock generation circuit _clk) carry out frequency division, obtain reverse link frequencies (BLF).

As shown in Figure 2, the present invention also provides a kind of method realizing reverse link frequencies in label chip,

(1) after circuit electrification reset, clock generation circuit is started working, the major clock (T of output _clk), circuit is in the state of wait-receiving mode order;

(2) when receiving the QUERY order that the external world sends over, command analysis circuit is started working, and obtains the reverse link rate factor (K) by the parameter of resolving in QUERY order.According to the regulation to the reverse link communication frequency of label in national standard, when read write line sends QUERY order, circulation of startup once being made an inventory, starts the frame format of querying command (QUERY) as table 1.

The detailed process of described step (S2) is: the querying command binary representation such as received for (101001000000000000001111111111111111) _b, subscript b represents scale-of-two; The order that command analysis circuit represents by the frame format in table 1: command code (8), condition (2), session (2), target (1), TRext (1), the reverse link rate factor (4), codes selection (2), verification (16), extract reverse link rate factor K.

Table 1 starts the frame format of querying command

In frame format, each data field is defined as follows:

1) command code: adopt the form of scale-of-two (b) to represent, start the frame format of querying command;

2) condition: specify and participate in the matching condition circulated of this time making an inventory, 4 kinds of value implications are described as follows:

21) 00 _b: all labels participate in;

22) 01 _b: match flag is 1 _blabel participate in;

23) 10 _b: match flag is 0 _blabel participate in;

24) 11 _b: retain.

3) session: the session number at circulation place of making an inventory;

4) target: mark of making an inventory, the implication of two kinds of values is as follows:

41) 0 _b: make an inventory and be masked as 0 _b;

42) 1 _b: make an inventory and be masked as 1 _b.

5) TR _ext: preamble signal indicates, and the implication of two kinds of values is as follows:

51) 0 _b: reverse link lead code is without targeting signal;

52) 1 _b: reverse link lead code has targeting signal.

6) the reverse link rate factor: determine reverse link frequencies (BLF), specifically in table 2;

7) codes selection: the mode of regulation reverse link code;

8) check code: the result that redundant cyclic verification (CRC-16) calculates.

The reverse link rate factor (K) in inquiry (QUERY) order is mainly used, for generation of reverse link frequencies in this method.

(3) frequency dividing circuit is under the control of power managed module, according to the reverse link rate factor, in conjunction with T reference time in forward link _cwith calibration symbol two T _cal2obtain divide ratio (n), and carry out integral frequency divisioil, obtain Reverse Link Clock.And then make passive ultra-high frequency radio-frequency (RF) identification reverse link communication frequency meet regulation in national standard.Concrete grammar is as follows:

Reverse link frequencies is determined by the reverse link rate factor (K) data field in querying command, and occurrence is as table 2.

Table 2 reverse link frequencies

Electronic label chip not only will support all reverse link frequencies of national Specification (namely in table 2), the reverse link frequencies error that also will meet on corresponding frequency is-20% ~+20%, so just can ensure normally carrying out of reverse link communication.This be major clock precision not high when, carry out a challenge of low power dissipation design.The method of reverse link frequencies proposed by the invention, meets frequency error (FT), makes a concrete analysis of as follows:

By table 2, obtain the standard value BLF of reverse link frequencies _prifor

BLF _pri＝1/T _pri＝320kHz(1)

Wherein T _prirepresent the Reverse Link Clock of standard.Specify in national standard, T _c=6.25 μ s or 12.5 μ s.In conjunction with T reference time in forward link _cconversion can obtain.

1) T is worked as _cduring=6.25 μ s, in ideal conditions, had by formula (1):

$320kHz=\frac{2}{T_C}---\left(2\right)$

Therefore clock period (the T of reverse link can be obtained _bLF) be

$T_{BLF}=\frac{1}{320kHz\×K}---\left(3\right)$

Adopt the calibration symbol two (T of forward link lead code _cal2) come predominant frequency (f _clk) calibrate, if N is the value that system clock counts to get calibration symbol two, the standard value N of N ^nomfor:

T _cal2＝2T _C(4)

N ^nom＝2T _C×f _clk(5)

Namely $f_{clk}=\frac{N^{nom}}{2T_C}---\left(6\right)$

Had by formula (2) and formula (5):

$\frac{f_{clk}}{320kHz}=\frac{N^{nom}}{4}---\left(7\right)$

Convolution (3) and (6) can obtain:

$T_{BLF}=\frac{N^{nom}}{4\×K}\×T_{clk}---\left(8\right)$

Wherein, T _bLFfor Reverse Link Clock, T _clkfor major clock.

Analyze this formula known, Reverse Link Clock can by system master clock through frequency division to, the standard value n of divide ratio n ^nomfor:

$n^{nom}=\frac{N^{nom}}{4\×K}---\left(9\right)$

In ideal conditions, the major clock that clock generation circuit produces is T _clk=1.92MHz, supposes that the command analysis reverse link factor is out K=1/5, then frequency dividing circuit obtains divide ratio according to formula (5) and formula (9) is n=30.

In a practical situation, in national standard, the error in length of regulation calibration symbol two be ± 1%, considers to there is counting error and calibration symbol error in length, and therefore the calibration count value N of symbol two and standard value can deviations to some extent.Be the value less than normal of count value below with value bigger than normal

$N_{min}^{nom}=2T_C\×0.99\×f_{clk}---\left(10\right)$

$N_{max}^{nom}=2T_C\×1.01\×f_{clk}---\left(11\right)$

Reverse clock is obtained, if adopt the method for integral frequency divisioil to realize after frequency division is carried out to system clock. divide ratio rounds (round), and consider quantization error, therefore n also exists maximal value n _maxwith minimum value n _min, then have

$n_{min}=round\left(\frac{N_{\min }^{nom}}{4\×K}\right)---\left(12\right)$

$n_{max}=round\left(\frac{N_{max}^{nom}}{4\×K}\right)---\left(13\right)$

Can the reverse link frequencies in the label chip course of work ensure normally carrying out of label chip reverse link communication, determined, know that its scope is ± 20%, had by definition by table 2 by reverse link frequencies error (FrequencyError, FE)

$\left|FE\right|=\left|T_{BLF}^{nom}-{\mathrm{nT}}_{clk}\right|/T_{BLF}---\left(14\right)$

Wherein the Reverse Link Clock of standard, is calculated by formula (15) and gets.

$T_{BLF}^{nom}=\frac{1}{{\mathrm{BLF}}_{pri}}---\left(15\right)$

Consider to there is quantization error, counting error, then have

$\left|FE1\right|=\left|T_{BLF}^{nom}-n_{min}{T}_{clk}\right|/T_{BLF}---\left(16\right)$

Therefore through type (16) can obtain the maximal value of FE:

|FE| _max＝max{|FE1|,|FE2|}(17)

The quantization error occurred in implementation procedure, counting error, frequency division error are taken into account, divide ratio is made to obtain more close to reality, reverse link frequencies has stability, and the impact of reverse link frequencies error not by clock accuracy in certain scope, meets the demands.

2) T is worked as _cduring=12.5 μ s, in ideal conditions, had by formula (1):

$320kHz=\frac{4}{T_C}---\left(18\right)$

Adopt the calibration symbol two (T of forward link lead code _cal2) come predominant frequency (f _clk) calibrate, if N is the value that system clock counts to get calibration symbol two, the standard value of N is:

T _cal2＝2T _C(19)

N ^nom＝2T _C×f _clk(20)

In like manner, then can have

$T_{BLF}=\frac{N^{nom}}{8\×K}\×T_{clk}---\left(21\right)$

$n^{nom}=\frac{N^{nom}}{8\×K}---\left(22\right)$

In ideal conditions, the major clock that clock generation circuit produces is T _clk=1.92MHz, supposes that the command analysis reverse link factor is out K=1/5, then frequency dividing circuit obtains divide ratio according to formula (20) and (22) is n=30.

Similarly, reverse link frequencies has stability, and the impact of reverse link frequencies error (FE) not by clock accuracy in certain scope, meets the demands.

Through above-mentioned analysis, the present invention is a kind of Method and circuits for realizing super high frequency radio frequency identification label chip reverse link frequencies.The method proposed in invention meets the requirement of super high frequency radio frequency identification national standard, it is characterized in that in conjunction with T reference time in forward link _cwith calibration symbol two T _cal2, obtain the integer division coeffi of 1.92MHz frequency, meet the constraint condition of reverse link frequencies error (FE) in national standard simultaneously.Method is based on circuit realiration, and main circuit will have clock generation circuit, power consumption management circuit, command analysis circuit and frequency dividing circuit.Frequency dividing circuit is the core that method realizes, and other circuit play auxiliary effect, and the process of specific implementation is carried out according to the flow process of Fig. 2:

(1) after electronic label chip electrification reset, clock generation circuit is started working, clock generation circuit adopts the form of relaxation osillator, its clock frequency produced is subject to the impact of the factors such as process deviation, temperature, voltage, if do not have extra clock calibration circuit, clock frequency may be higher or on the low side.Consider deviation, the frequency of output is f, is about 1.92MHz ± 20%, and then chip enters the state of wait-receiving mode order;

(2) when label receives the QUERY order that read write line sends over, command analysis circuit receives the control signal of power managed module, start working, obtain the reverse link rate factor (K) by the parameter of resolving in QUERY order, what should remind is that the reverse link rate factor upgrades along with the renewal of parameter in QUERY order;

(3) frequency dividing circuit is under the control of power managed module, realizes the method proposed in invention, meets the condition of reverse link communication.As Fig. 1, clock generation circuit provides major clock (T _clk), command analysis circuit provides the reverse link factor (K), and frequency dividing circuit produces Frequency Dividing Factor (n), according to above-mentioned methods analyst, has T _bLF=n × T _clk, finally, export reverse link frequencies (BLF).

Should be understood that; although the embodiment that the present invention provides; and be not used to limit the present invention; in order to satisfied local and specific requirement; those skilled in the relevant art can not depart from the spirit and scope of the present invention situation; certain modifications and changes are made to solution described above, all belongs to protection scope of the present invention.

Claims (3)

1. one kind for realizing the circuit of reverse link frequencies in electronic label chip, it is characterized in that, comprise clock generation circuit, power consumption management circuit, command analysis circuit and frequency dividing circuit, the control signal that described clock generation circuit clocking, described power consumption management circuit produce, described command analysis circuit provide the reverse link rate factor to be input in frequency dividing circuit respectively and process, and export reverse link frequencies by frequency dividing circuit.

2. realize a method for reverse link frequencies in electronic label chip, adopting as claimed in claim 1 for realizing the circuit of reverse link frequencies in electronic label chip, it is characterized in that, comprise the following steps:

(S1) after realizing the circuit electrification reset of reverse link frequencies in label chip, clock generation circuit is started working, the major clock of output, and circuit is in the state of wait-receiving mode order;

(S2) when receiving querying command, command analysis circuit is started working, and obtains the reverse link rate factor by the parameter of resolving in querying command;

(S3) frequency dividing circuit is under the control of power managed module, according to the reverse link rate factor, obtains divide ratio, carry out integral frequency divisioil, obtain reverse link frequencies in conjunction with the reference time in forward link and calibration symbol two.

3. a kind of method realizing reverse link frequencies in label chip as claimed in claim 2, it is characterized in that, the detailed process of described step (S3) is: clock generation circuit provides major clock T _clk, command analysis circuit provides reverse link factor K, and frequency dividing circuit produces Frequency Dividing Factor n, obtains reverse link frequencies T according to formula _bLF=n × T _clk, obtain reverse link frequencies BLF=1/T _bLF.