CN114936112B - Control method of passive ultrahigh frequency electronic tag chip digital baseband processor - Google Patents
Control method of passive ultrahigh frequency electronic tag chip digital baseband processor Download PDFInfo
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1004—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's to protect a block of data words, e.g. CRC or checksum
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/12—Synchronisation of different clock signals provided by a plurality of clock generators
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
- G06K7/00—Methods or arrangements for sensing record carriers, e.g. for reading patterns
- G06K7/10—Methods or arrangements for sensing record carriers, e.g. for reading patterns by electromagnetic radiation, e.g. optical sensing; by corpuscular radiation
- G06K7/10009—Methods or arrangements for sensing record carriers, e.g. for reading patterns by electromagnetic radiation, e.g. optical sensing; by corpuscular radiation sensing by radiation using wavelengths larger than 0.1 mm, e.g. radio-waves or microwaves
- G06K7/10297—Methods or arrangements for sensing record carriers, e.g. for reading patterns by electromagnetic radiation, e.g. optical sensing; by corpuscular radiation sensing by radiation using wavelengths larger than 0.1 mm, e.g. radio-waves or microwaves arrangements for handling protocols designed for non-contact record carriers such as RFIDs NFCs, e.g. ISO/IEC 14443 and 18092
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- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D30/00—Reducing energy consumption in communication networks
- Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks
Abstract
The invention provides a control method of a passive ultrahigh frequency electronic tag chip digital baseband processor, which comprises the steps that a radio frequency analog front end, a decoder, a clock chip and a latch form the digital baseband processor; the control method is characterized by comprising the following steps: acquiring demodulation data of a radio frequency analog front end, and performing clock synchronization on the demodulation data through a clock chip to acquire primary processing data; decoding the primary processing data through a decoder, and latching the decoded data through a latch to acquire secondary processing data; and performing parameter check on the secondary processing data, performing CRC check on the data subjected to the parameter check, and generating read data after the check is successful. The invention can reduce the dynamic power consumption of the electronic tag chip by checking the parameters of the demodulated data.
Description
Technical Field
The invention relates to the technical field of radio frequency identification, in particular to a control method of a passive ultrahigh frequency electronic tag chip digital baseband processor.
Background
At present, the hot problem of research on ultrahigh frequency tags is low cost and low power consumption, and a method for reducing the cost in design is to reduce the area of a chip as much as possible, and the power consumption is also an important index for reflecting the quality of an ultrahigh frequency electronic tag, and particularly for passive electronic tags, the lower the power consumption is, the more the power consumption is, the longer the distance can be, for example, patent CN 201410040751-passive RFID electronic tag digital baseband processor provided by the invention can simultaneously reset all modules of the digital baseband processor under the condition that a reset input signal provided by a radio frequency analog front end reset circuit is effective, after the reset is completed, all module circuits are uniformly and directly in a working state until the digital baseband processor is powered off, all module circuits in the working state of the digital baseband processor consume power, and the power consumption of the digital baseband processor is too large; in addition, the invention patent CN 201711372819-a low power consumption architecture system of ultrahigh frequency passive RFID digital baseband, wherein the digital baseband processor architecture of the electronic tag adopts either a finite state machine structure divided according to functions or a CPU structure based on CISC instruction set; however, in both of these structures, the particularity of the electronic tag that requires extremely low power consumption is not considered in the division, and usually, a plurality of modules cooperate and operate simultaneously, so that a large instantaneous power consumption is generated.
Disclosure of Invention
The invention provides a control method of a passive ultrahigh frequency electronic tag chip digital baseband processor, which is used for solving the problems of high power consumption and unclear data flow direction of the digital baseband processor.
A control method of a passive ultrahigh frequency electronic tag chip digital baseband processor comprises the steps that the digital baseband processor is composed of a radio frequency analog front end, a decoder, a clock chip and a latch; the control method comprises the following steps:
acquiring demodulation data of a radio frequency analog front end, and performing clock synchronization on the demodulation data through a clock chip to acquire primary processing data;
decoding the primary processing data through a decoder, and latching the decoded data through a latch to acquire secondary processing data;
and performing parameter check on the secondary processing data, performing CRC check on the data subjected to parameter check, and generating read data after the check is successful.
Further: the method for acquiring the demodulation data of the radio frequency analog front end and performing clock synchronization on the demodulation data through a clock chip to acquire primary processing data comprises the following steps:
judging whether the digital baseband processor is reset or not, acquiring a clock signal input by a radio frequency analog front end after the digital baseband processor is reset according to a judgment result, and carrying out frequency division processing on the clock signal;
performing time delay processing on the clock signal subjected to frequency division processing to obtain a reset signal of the global multiplexing counter;
and receiving demodulation data of a wireless radio frequency signal at a radio frequency analog front end according to the reset signal of the global multiplexing counter, synchronizing the demodulation data by a clock reset method, and determining primary processing data.
Further: the decoding the primary processing data through a decoder, and latching the decoded data through a latch to obtain secondary processing data, includes:
performing command analysis on the primary processing data, and determining a command type and a requirement to be processed; wherein, the first and the second end of the pipe are connected with each other,
the command types include at least: inquiry response command, character confirmation command, time slot parameter command, selection command, read command and write command;
judging the waveform position of the primary processing data according to the command type and the requirement to be processed, determining the waveform position, decoding according to the waveform of the waveform position, and determining command parameters; wherein, the first and the second end of the pipe are connected with each other,
the decoding process at least comprises two counters which are a first counter and a second counter respectively;
the first counter is used for counting the number of bits of the received parameters;
the second counter is used for counting the length of each bit in the receiving parameters;
storing the command parameters by a multiplexing sharing method; wherein the content of the first and second substances,
the multiplexing sharing method is to adopt a time-sharing multiplexing latch to store command parameters at any time.
Further: the parameter checking the secondary processing data, performing CRC checking on the parameter checked data, and generating read data after the CRC checking is successful includes:
determining a high-order priority order according to the secondary processing data, serially sending the secondary processing data to a register according to the high-order priority order to perform CRC (cyclic redundancy check) in a shifting mode, and determining a shifting result;
when the shift result shows that the secondary processing data is successfully shifted, acquiring a result value of an output end of the register; wherein the content of the first and second substances,
and when each bit of the result value at the output end of the register is zero, judging that the CRC passes the check, and outputting the secondary processing data as read data.
And further: the analyzing the primary processing data to determine the command type and the requirement to be processed comprises the following steps:
performing instruction judgment on each bit of data in the primary processing data, and determining the judgment result of each bit of data;
when the judgment result shows that the instruction is not acquired, determining the instruction state of the data, and storing the instruction state;
when the judgment result shows that the instruction is obtained, determining the digit of the data, and carrying out digit labeling on the data to determine labeled data;
determining corresponding storage command parameters according to the label data, acquiring corresponding command data streams according to the storage command parameters, comparing the command data streams with preset command data streams, determining whether the command data streams corresponding to the label data are in error, and acquiring a comparison result;
when the comparison result shows that the command data stream has errors, acquiring state machine parameters and resetting the state machine parameters;
and when the comparison result shows that the command data stream has no errors, starting a command data stream analysis mechanism, acquiring sub-command parameters corresponding to the command data stream, and determining a corresponding command type and a requirement to be processed according to the sub-command parameters.
Further: the determining the waveform position comprises:
acquiring waveform change data corresponding to the primary processing data, monitoring the waveform change data, and determining a waveform monitoring result;
and when the waveform monitoring result shows that the rising edge of the waveform is detected, determining the position of the parameter.
Further: the performing parameter check on the secondary processing data, performing CRC check on the parameter checked data, and generating read data after the check is successful, further includes:
acquiring a frame header and a command parameter corresponding to the secondary processing data, performing parameter check on the frame header and the command parameter, and determining a parameter check result; wherein the content of the first and second substances,
the parameter checking result comprises: the exception parameter does not exist and exists;
judging whether the secondary processing data has a receiving error condition according to the parameter checking result;
when the judgment result shows that the parameter checking result has a receiving error, determining an error type; wherein, the first and the second end of the pipe are connected with each other,
the error types include: setting a flag bit to be wrong, not updating a time slot counter, not updating a Q value, and skipping a chip;
and executing a corresponding error repair scheme according to the error type.
And further: the executing the corresponding error recovery scheme according to the error type includes:
when the error type corresponds to a flag bit setting error, acquiring a reader-writer sending instruction, matching the sending instruction with an internal preset storage value by the electronic tag, determining a matching result, and when the matching result shows that the matching is successful, setting the flag bit according to the sending instruction;
when the error type is not updated correspondingly to the time slot counter, determining an initial environment type, when the initial environment type is a multi-tag environment, generating a random number, storing the random number into the time slot counter, monitoring a tag response value of the time slot counter, and when the tag response value is zero, generating a new random number and sending the new random number to a reader-writer; wherein the content of the first and second substances,
the initial environment types include: single-label environments and multi-label environments;
when the error type corresponds to that the Q value is not updated, sending a non-zero Q value through a reader-writer to update the Q value;
when the error type corresponds to that the chip jumps, acquiring a tag state value and reader-writer response time, storing the tag state value, acquiring a storage result, judging whether the reader-writer response time is greater than a preset time threshold, if the reader-writer response time is not greater than the preset time threshold, acquiring a command sent by reading and writing to compare command parameters, and jumping the tag state according to a preset rule according to the comparison result.
Further: the performing parameter check on the secondary processing data, performing CRC check on the parameter checked data, and generating read data after the check is successful, further includes:
performing FPGA verification on the read data subjected to CRC; wherein the content of the first and second substances,
the FPGA verification process comprises the following steps:
adding constraint types according to the time sequence information in the read data, and determining a first check result; wherein the content of the first and second substances,
the constraint types include: timing constraints, grouping constraints, area constraints, pin constraints, proprietary constraints;
the timing constraints are periodically set for data;
the grouping constraint is achieved by grouping clocks;
the pin constraint is realized by acquiring input and output signals and transmitting the input and output signals to an FPGA output pin;
the special constraint is realized by setting a special virtual path for data;
monitoring the input and output waveforms of the digital baseband processor through an oscilloscope based on the first checking result, comparing the input and output waveforms with a preset input and output waveform threshold range, and determining a comparison result;
and when the comparison result shows that the input and output waveforms of the digital baseband processor are within a preset input and output waveform threshold range, judging that the read data time sequence is consistent.
Further: the clock synchronization of the clock chip is also provided with a plurality of clock domains; wherein, the first and the second end of the pipe are connected with each other,
the clock domain includes: clk _ m clock domain, clk _ tpp clock domain, clk _ BLF clock domain;
the clk _ m is provided by an analog radio frequency front end for a system main clock;
the clk _ TPP is a TPP coded data clock, and the decoding module decodes the TPP coded data to obtain the TPP coded data and is used for processing command parameters;
the clk _ BLF is the tag reverse link clock, generated by the DIV module, used to recover the data.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and drawings.
The technical solution of the present invention is further described in detail by the accompanying drawings and embodiments.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention and not to limit the invention. In the drawings:
fig. 1 is a schematic flow chart of a control method of a passive ultrahigh frequency electronic tag chip digital baseband processor according to an embodiment of the present invention;
fig. 2 is a schematic flow chart illustrating clock synchronization for demodulated data in a control method of a passive ultrahigh frequency electronic tag chip digital baseband processor according to an embodiment of the present invention;
fig. 3 is a schematic flow chart of a frame for latching decoded data by a latch in a control method of a passive ultrahigh frequency electronic tag chip digital baseband processor according to an embodiment of the present invention.
Detailed Description
The preferred embodiments of the present invention will be described in conjunction with the accompanying drawings, and it will be understood that they are described herein for the purpose of illustration and explanation and not limitation.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions, and "plurality" means two or more unless specifically limited otherwise. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus.
Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.
The invention relates to a control method of a passive ultrahigh frequency electronic tag chip digital baseband processor, which comprises a digital baseband processor consisting of a radio frequency analog front end, a decoder, a clock chip and a latch; as shown in fig. 1, the control method includes:
acquiring demodulation data of a radio frequency analog front end, and performing clock synchronization on the demodulation data through a clock chip to acquire primary processing data;
decoding the primary processing data through a decoder, and latching the decoded data through a latch to acquire secondary processing data;
and performing parameter check on the secondary processing data, performing CRC check on the data subjected to the parameter check, and generating read data after the check is successful.
The technical scheme is to solve the problem that the power consumption of a passive ultrahigh frequency electronic tag chip digital baseband processor in the prior art is too high, an RFID tag can be divided into an active tag, a passive tag and a semi-active tag according to energy supply, a battery is adopted in the active tag for supplying power, the reading and writing distance can reach the farthest, but the corresponding cost is higher, the service life of the battery is greatly reduced due to the fact that the battery is in a constantly opened state, the energy of the passive tag comes from a radio frequency carrier wave sent by a reader-writer, a radio frequency signal is converted into direct current energy through an internal rectifying unit, then the energy is supplied to an internal circuit, a control switch circuit containing voltage is arranged in the semi-active tag, the battery supply voltage is cut off when the battery does not work, the battery supply voltage is opened when the battery works, but the radio frequency field intensity corresponding to the semi-active tag is weaker, the identification distance is also shorter, in addition, the RFID tag can be divided into a low frequency state, a high frequency state and a microwave state, the low frequency tag works by adopting an inductive coupling principle, the technology is relatively mature, and the RFID tag is widely used in the market, and the problem that the standard frequency band is unified, the traffic jam and the like;
when the passive ultrahigh frequency electronic tag is implemented, the ultrahigh frequency works in an electromagnetic backscattering coupling mode, so that the working time sequence gating of the passive ultrahigh frequency electronic tag chip is subjected to hierarchical gating by a radio frequency analog front end demodulation data and an asynchronous design method: the invention comprises clock synchronous processing, latch processing of a latch and CRC (cyclic redundancy check) validation, and carries out secondary gating, and hierarchical gating reduces the working state of a digital baseband processor in the prior art when carrying out data processing, namely, whether the latch, the clock or the validation is in the prior art, so that the invention combines a low-power consumption design theory, applies a low-power consumption data processing mode to an electronic tag chip, and in addition, except for low-power consumption devices such as the latch, the clock signal of the invention carries out asynchronous counting through an asynchronous clock chip, and further reduces the power consumption by adopting a decoder for multiplexing, green coding and the like, and processes coded data instead of directly processing data.
The beneficial effects of the above technical scheme are: in the technical scheme, the passive ultrahigh frequency electronic tag is adopted, and the clock synchronization can be realized, so that batch demodulation can be performed. The batch reading capability is improved, and hundreds of label object information can be collected at a distance of 10 meters; secondly, the low cost of the tag is realized, the ultrahigh frequency antenna is small and is made of aluminum and other metal alloys, so that the passive electronic tag is low in power consumption, long in working distance and high in sensitivity.
Further, as shown in fig. 2, the acquiring demodulation data of the radio frequency analog front end, performing clock synchronization on the demodulation data through a clock chip, and acquiring primary processing data includes:
judging whether the digital baseband processor is reset or not, acquiring a clock signal input by a radio frequency analog front end after the digital baseband processor is reset according to a judgment result, and carrying out frequency division processing on the clock signal;
performing time delay processing on the clock signal subjected to frequency division processing to obtain a reset signal of the global multiplexing counter;
and receiving demodulation data of a wireless radio frequency signal at a radio frequency analog front end according to the reset signal of the global multiplexing counter, synchronizing the demodulation data by a clock reset method, and determining primary processing data.
In the prior art, the digital baseband comprises three working states, namely a receiving state, a processing state and a sending state, wherein the three states are respectively operated and controlled by three independent modules, so that the overall power consumption is high;
when the invention is implemented, three working states are embedded into a general function module to judge whether a digital baseband is reset, and after the digital baseband is reset, a system clock input by an analog front end is subjected to frequency division, inversion and time delay through a clock reset module to generate reset signals of a clock tree framework and a global multiplex counter of the whole system; when the analog front end demodulated data is transmitted, the data is synchronized through a clock reset module and then is sent to a decoding module for decoding, the decoded data is latched by a latch in a receiving latch module and the analysis of command parameters is completed, parameter check and CRC check are simultaneously carried out after each bit of data is decoded, the validity of each parameter in a frame header and a command is checked in the parameter check process, the check result and a received signal are sent to a control block, the control block completes corresponding processing according to the analyzed command parameters and the condition of whether the command parameters have the receiving error, the processing comprises the overturning of a chip flag bit, the updating of a time slot counter, the jumping of a state machine, the reading and writing of EERPOM and the like, the data needing to be returned is sent to a sending state machine module through the counting of communication delay T1 time specified by a protocol, the FM0 coding or Miller coding mode is determined according to M parameters in a Query instruction stored in a receiving buffer, whether the CRC check needs to be adopted is judged, if the CRC check needs to be added, CRC5 or 16 is added behind the returned data, a frame tail code and a series of CRC tail codes are added to form a frame stream, and a specific frame header is returned to the analog front end, and the analog front end is returned.
The beneficial effects of the above technical scheme are: according to the technical scheme, the data flow direction is clearer due to the fact that the working states of the digital baseband are embedded into a general module, power consumption is reduced due to time-sharing gating, command parameters are analyzed through decoding and latching, integrity of data signals is kept, the working time of the digital baseband is divided into different stages, and gating is facilitated to reduce power consumption.
Example 3:
in one embodiment, as shown in fig. 3, the decoding the primary processing data by a decoder, and latching the decoded data by a latch to obtain the secondary processing data includes:
performing command analysis on the primary processing data, and determining a command type and a requirement to be processed; wherein the content of the first and second substances,
the command types include at least: inquiry response command, character confirmation command, time slot parameter command, selection command, read command and write command;
judging the waveform position of the primary processing data according to the command type and the requirement to be processed, determining the waveform position, decoding according to the waveform of the waveform position, and determining command parameters; wherein the content of the first and second substances,
the decoding process at least comprises two counters which are a first counter and a second counter respectively;
the first counter is used for counting the number of bits of the received parameters;
the second counter is used for counting the length of each bit in the receiving parameters;
storing the command parameters by a multiplexing sharing method; wherein the content of the first and second substances,
the multiplexing sharing method is to adopt a time-sharing multiplexing latch to store command parameters at any time.
The above technical solution is to improve the efficiency and the rate of obtaining the target parameter, because the function of the decoder in the prior art mainly is to distinguish the binary code with a specific meaning and convert the binary code into the control signal, the decoder in the technical solution needs to implement two functions: judging the position of the waveform, namely acquiring the type of the target parameter received by the current waveform position; the waveform of the position is decoded, because the decoder needs to realize two functions, the decoder at least needs to comprise two counters, one is used for counting the number of bits of the received parameter, and the other is used for counting the length of each bit.
The beneficial effects of the above technical scheme are: in the technical scheme, at least two counters are added in the decoder, so that different functions can be realized when different stages are facilitated, in addition, the rising edge of the waveform is captured through the pulse detection circuit, the state of the waveform is favorably and rapidly judged, and the efficiency and the speed for acquiring the target parameters are improved.
Example 4:
in one embodiment, the performing parameter check on the secondary processing data, performing CRC check on the parameter checked data, and generating read data after the check is successful includes:
according to the secondary processing data, determining a high-order priority order, serially transmitting the secondary processing data to a register according to the high-order priority order to perform CRC in a shifting mode, and determining a shifting result;
when the shift result shows that the secondary processing data is successfully shifted, acquiring a result value of an output end of the register; wherein the content of the first and second substances,
and when each bit of the result value at the output end of the register is zero, judging that the CRC passes the check, and outputting the three-level processing data as read data.
In the actual implementation: if cyclic redundancy check is carried out, the problems of high cost and high power consumption exist, in order to reduce the cost and the power consumption of the digital baseband processor of the electronic tag chip, a cyclic redundancy check circuit is usually included, and when the storage capacities in registers are different, the check accuracy rate can be reduced;
when the invention is implemented, two redundancy check circuits, namely CRC-5 and CRC-16 circuits are arranged in a cyclic redundancy check unit, a 5-bit shift register and a 16-bit shift register are respectively adopted in the two circuits to realize the check and CRC calculation of data, when the CRC-5 works, the 5-bit register is preloaded to 01001, then a clock is started, input data is serially sent to the register for shifting according to the principle of high-bit priority, the high-bit priority is a byte sequence, sequencing is carried out according to the address of the byte, the high-bit byte is taken as the preferential byte sequence, so that more accurate shifting is convenient, when all input data are loaded, if the register outputs Q [4: the CRC-5 check passes when both 0] ends are 0, and when calculating CRC-5, it is still necessary to load the register to 01001 first, and send the input data, and finally the register Q [4: the latch value at the 0] end is the calculated value of CRC-5; when CRC-16 works, firstly, a 16-bit register is preloaded to FFFFh, then a clock is opened, input data is sent to the register according to a high-bit priority principle, and when the input data are all loaded, if the output end Q [15: when 0 is 1DOFH, the verification passes. When calculating CRC-16, the register is still preloaded as FFFFh first, then the clock is turned on to feed the data in, and when the data is loaded, Q [15:0] each bit is inverted to obtain the calculated value of CRC-16.
The beneficial effects of the above technical scheme are: according to the technical scheme, the two CRC circuits are arranged in the cyclic redundancy check module, so that different requirements of data in a chip can be met, and the storage and check efficiency and accuracy are improved.
Example 5:
further: the analyzing the primary processing data to determine the command type and the requirement to be processed comprises:
performing instruction judgment on each bit of data in the primary processing data, and determining the judgment result of each bit of data;
when the judgment result shows that the instruction is not acquired, determining the instruction state of the data, and storing the instruction state;
when the judgment result shows that the instruction is obtained, determining the digit of the data, and carrying out digit labeling on the data to determine labeled data;
determining corresponding storage command parameters according to the label data, acquiring corresponding command data streams according to the storage command parameters, comparing the command data streams with preset command data streams, determining whether the command data streams corresponding to the label data are wrong or not, and acquiring a comparison result;
when the comparison result shows that the command data stream has errors, acquiring state machine parameters and resetting the state machine parameters;
and when the comparison result shows that the command data stream has no errors, starting a command data stream analysis mechanism, acquiring sub-command parameters corresponding to the command data stream, and determining a corresponding command type and a requirement to be processed according to the sub-command parameters.
The implementation principle of the invention is as follows: the data is firstly analyzed through the command before being decoded, the corresponding command type is judged, and corresponding processing is started according to the corresponding command type. Therefore, in the command parsing process, according to the decoded value of each bit, the command data stream is stored and parsed through the register, when each bit of data in the command arrives, the data is judged, if the command can be judged according to the bit, command parameters are stored and are Green coded, the whole process is finished, if the data can be judged through the bit, the command data stream is in error, the whole state machine is immediately judged in error and reset, if the decoded data according to the bit cannot be judged which command is, the state is stored firstly, when the next decoded data arrives, the state stored before is combined to judge which of the two former two conditions is, and if the decoded data cannot be analyzed, the state of the bit is stored continuously until the command can be analyzed.
In the specific implementation, when the power consumption of the digital baseband processor is calculated, the method can be divided intoStatic power consumption and dynamic power consumption, when a circuit is in a stable state, leakage current is easy to appear, the power consumption with leakage current consumption is the static power consumption, and the static power consumption is assumed to be
The dynamic power consumption is that when the circuit works and the MOS tube in the chip is in an open state at the same time, the power consumption of the circuit caused by short circuit is the dynamic power consumption, and the dynamic power consumption is assumed to be
Then the power consumption consumed by the circuit can be expressed as:
wherein the content of the first and second substances,
represents the total power consumed in the circuit,
representing the static power consumption consumed in the circuit,
representing the dynamic power consumption consumed in the circuit,
the switching power consumption generated by charging and discharging of the capacitor is represented;
the reason for generating static power consumption in the analysis circuit is mainly caused by leakage current, wherein the leakage current comprises reverse bias current of a diode on a drain electrode of a transistor in a chip
Leakage current due to threshold characteristics of transistors in the chip when the circuit element is in an off state
Then the static power consumption in the circuit can be expressed as:
wherein, the first and the second end of the pipe are connected with each other,
representing the static power consumption consumed in the circuit,
which represents the value of the voltage of the power supply,
representing the diode reverse biased current on the drain of the transistor in the chip,
representing leakage current due to threshold characteristics of transistors in the chip;
analyzing the reason of dynamic power consumption in the circuit, because the signal needs to spend a certain time in the rising process, in this period of time, a complete conduction path is formed in the circuit, so that the circuit is in a transient short-circuit state, and the average current of the short-circuit can be expressed as
The corresponding dynamic power consumption may be expressed as:
wherein, the first and the second end of the pipe are connected with each other,
representing the dynamic power consumption consumed in the circuit,
the value of the voltage of the power supply is represented,
an average current representing a short circuit;
the MOS tube can generate charge and discharge effects in the switching process, and when the MOS tube is conducted, the power supply voltage
To the load capacitance
Charging, when the output port of the chip is converted from low level signal to high level signal, the load capacitor is charged
Is pulled to voltage
Then, the electric energy consumed by the MOS transistor in the whole process is:
wherein the content of the first and second substances,
represents the switch power consumption generated by the charging and discharging of the capacitor,
which is indicative of the value of the load capacitance,
which is representative of the voltage of the power supply,
the frequency of charging the load capacitor is shown, and when the output port of the chip is converted from a low level signal to a high level signal, the load capacitor is charged
Is pulled to voltage
The amount of electric charge to be charged is
The energy consumed corresponds to
；
According to the technical scheme, the command data stream is stored and analyzed by the register, so that the use space of a data baseband is saved, the running speed of the digital baseband processor is increased, command analysis is performed on data before decoding, command parameters are acquired quickly, whether errors occur in the data stream can be judged according to the command parameters, and the recovery efficiency of the state machine is improved.
Example 6:
and further: the determining the waveform position comprises:
acquiring waveform change data corresponding to the primary processing data, monitoring the waveform change data, and determining a waveform monitoring result;
and when the waveform monitoring result shows that the rising edge of the waveform is detected, determining the position of the parameter.
The implementation principle of the invention is as follows: in the technical scheme, when each bit of parameter is counted, the precision of a counting clock and the number of counted bits are obtained, the counting precision mainly depends on the shortest counting time, and the number of bits depends on the longest counting time;
the beneficial effects of the above technical scheme are: according to the technical scheme, the length of the parameter is counted by adopting the frequency division of the system clock, the requirement of the digit of the data is met, and the dynamic power consumption of the digital baseband processor is reduced.
Example 7:
and further: the performing parameter check on the secondary processing data, performing CRC check on the parameter checked data, and generating read data after the check is successful, further includes:
acquiring frame headers and command parameters corresponding to the secondary processing data, performing parameter check on the frame headers and the command parameters, and determining a parameter check result; wherein the content of the first and second substances,
the parameter checking result comprises: the exception parameter does not exist and exists;
judging whether the secondary processing data has a receiving error condition according to the parameter checking result;
when the judgment result shows that the parameter checking result has a receiving error, determining an error type; wherein the content of the first and second substances,
the error types include: setting a flag bit error, not updating a time slot counter, not updating a Q value, and skipping a chip;
and executing a corresponding error repair scheme according to the error type.
The implementation principle of the invention is as follows: when the functions of the digital baseband processor need to complete the setting of a flag bit, the updating of a time slot counter in an inventory process, the updating of a Q value and the skipping state of a chip, a frame header and a command parameter corresponding to data are firstly acquired, parameter checking is carried out according to the frame header and the command parameter, and when the error state of a parameter checking result is determined, the type of an error is judged when the error state of the parameter checking result is determined;
the beneficial effects of the above technical scheme are: according to the technical scheme, the frame header and the command parameters of the data are checked at first, and the data state is not directly tested, so that the efficiency of parameter checking is improved, the waste of time is reduced, and the operation efficiency of the digital baseband processor is improved.
Example 8:
and further: the executing the corresponding error recovery scheme according to the error type includes:
when the error type corresponds to a flag bit setting error, acquiring a reader-writer sending instruction, matching the sending instruction with an internal preset storage value by the electronic tag, determining a matching result, and when the matching result shows that the matching is successful, setting a flag bit according to the sending instruction;
when the error type is not updated correspondingly to the time slot counter, determining an initial environment type, when the initial environment type is a multi-tag environment, generating a random number, storing the random number into the time slot counter, monitoring a tag response value of the time slot counter, and when the tag response value is zero, generating a new random number and sending the new random number to a reader-writer; wherein the content of the first and second substances,
the initial environment types include: single-label environments and multi-label environments;
when the error type corresponds to that the Q value is not updated, sending a non-zero Q value through a reader-writer to update the Q value;
when the error type corresponds to that the chip jumps, acquiring a tag state value and reader-writer response time, storing the tag state value, acquiring a storage result, judging whether the reader-writer response time is greater than a preset time threshold, if the reader-writer response time is not greater than the preset time threshold, acquiring a command sent by reading and writing to compare command parameters, and jumping the tag state according to a preset rule according to the comparison result.
The implementation principle of the invention is as follows: in the technical scheme, when the flag bit is set, in order to enable the reader-writer to quickly obtain the desired tag in the multi-tag selection and inventory processes, two types of marking units inside the tag are specified by a protocol: the method comprises the steps that a checked mark and a selected mark are marked, all labels support 4 sessions (S1, S2, S3 and S4), a reader-writer can communicate with labels related to one session, the reader-writer selection label is realized by sending a select instruction, the label compares whether the content of a mask sent in the instruction is matched with an internal stored value, and then the value of a specific marker bit is changed by an action parameter; when the Q value and the time slot counter are updated, a Query command with a non-zero Q value is sent by the reader-writer, a random number is generated in a preset range by a tag in the same session and zone bit environment and is stored in the time slot counter, and a new random number is generated and sent back to the reader-writer when the tag response of the time slot counter is zero; when the tag state jumps, firstly, the tag state value needs to be stored, then different jumps are realized according to the protocol in different states according to the type of a received command, firstly, whether the tag is killed is judged, then, whether T2 time is exceeded or not is judged, T2 is the response time of a reader-writer specified by the protocol, if the requirement of T2 timing is met, the tag compares command parameters according to the command sent by the reader-writer, and the matched tag correspondingly jumps according to the protocol according to the current state;
in specific implementation, the passive ultrahigh frequency electronic tag in the technical scheme is far away from the reader-writer and works in a radiation far field region of the reader-writer antenna, and the transmitting power of the reader-writer is assumed to be
The antenna gain of the reader/writer is
Then the distance reader-writer can be calculated as
The corresponding power densities at (1) are:
wherein the content of the first and second substances,
indicating a distance reader-writer as
The power density value corresponding to the position of (a),
which represents the transmission power of the reader/writer,
the gain of the antenna of the reader/writer is indicated,
a distance value representing the distance from the reader/writer,
the effective transmitting power of the antenna of the reader-writer is represented;
the matching factor of the antenna in the passive ultrahigh frequency electronic tag chip is
The power that the digital baseband processor in the electronic tag chip can receive
Expressed as:
wherein the content of the first and second substances,
representing the amount of power that the digital baseband processor is capable of receiving,
shows the matching factor of the antenna in the passive UHF electronic label chip,
the flux density ratio of the power of the output end of the tag antenna and the power of the electromagnetic wave transmitted by the reader-writer is expressed,
indicating a distance reader-writer as
The power density value corresponding to the position of (a),
the gain of the electronic tag antenna is represented, and when the matching factor of the antenna in the passive ultrahigh-frequency electronic tag chip is 1, the tag antenna obtains the maximum power;
the beneficial effects of the above technical scheme are: according to the technical scheme, the setting of the zone bit, the updating of the counting process time slot counter, the updating of the Q value and the state skipping of the chip are realized in the digital baseband processor, the dynamic power consumption of the baseband processor is favorably reduced, the data speed is improved, the maximum output power value of the tag is favorably acquired by calculating the energy transmission process in the passive ultrahigh frequency electronic tag chip, and the running efficiency of the digital baseband processor is favorably improved.
Further: the performing parameter check on the secondary processing data, performing CRC check on the data subjected to parameter check, and generating read data after the check is successful, further comprising:
performing FPGA verification on the read data subjected to CRC; wherein the content of the first and second substances,
the FPGA verification process comprises the following steps:
adding constraint types according to the time sequence information in the read data, and determining a first check result; wherein the content of the first and second substances,
the constraint types include: timing constraints, grouping constraints, area constraints, pin constraints, proprietary constraints;
the timing constraints are periodically set for data;
the grouping constraint is achieved by grouping clocks;
the pin constraint is realized by acquiring input and output signals and transmitting the input and output signals to an FPGA output pin;
the special constraint is realized by setting a special virtual path for data;
monitoring the input and output waveforms of the digital baseband processor through an oscilloscope based on the first checking result, comparing the input and output waveforms with a preset input and output waveform threshold range, and determining a comparison result;
and when the comparison result shows that the input and output waveforms of the digital baseband processor are within a preset input and output waveform threshold range, judging that the read data time sequence is consistent.
In actual implementation: when the quality of the electronic tag chip is detected, a performance test method is generally performed through software, verification is not performed on an actual device, a difference exists between an actual application environment and a simulation environment, and the simulation time is limited;
when the invention is implemented, FPGA verification is carried out on an electronic tag chip, a clock and a power-on reset signal of a digital baseband processor are generated by an external device aiming at coding of a reader-writer end command and a decoding task of received data, the performance of the electronic tag is detected under the condition of meeting a time sequence, in addition, the constraint is very important for the correct wiring and the time sequence check of the FPGA, and the constraint type comprises the following steps: timing constraint, grouping constraint, area constraint, pin constraint, proprietary constraint, and finally, directly using an original clock without using a gated clock by modifying a clock structure;
the beneficial effects of the above technical scheme are: according to the technical scheme, through the encoding aiming at the command of the reader-writer end and the decoding task of the received data, the jump of key signals inside a chip can be observed, the verification efficiency is improved, in addition, the wiring correctness checking efficiency is improved through adding constraint, and the power consumption is reduced through simplifying a clock structure.
Example 10:
further: the clock synchronization of the clock chip is also provided with a clock domain; wherein the content of the first and second substances,
the clock domain includes: clk _ m clock domain, clk _ tpp clock domain, clk _ BLF clock domain;
the clk _ m is provided by an analog radio frequency front end for a system main clock;
the clk _ TPP is a TPP coded data clock, and the decoding module decodes the TPP coded data to obtain the TPP coded data and is used for processing command parameters;
the clk _ BLF is the tag reverse link clock, generated by the DIV module, used to recover the data. The implementation principle of the invention is as follows: the digital baseband in the technical scheme adopts the principle of multi-clock domain, different working modules work under different clock frequencies, communication synchronization is facilitated by setting a clk _ m clock domain, data received by a decoding module is data decoded by a radio frequency analog front end, in order to achieve communication synchronization, an adopted working clock is a clk _ m clock of data synchronization decoded by the radio frequency analog front end, a DIV module uses a main clock clk _ m to generate a reverse link clock which is related to the coding form of the received data, therefore, the clk _ TPP synchronous with TPP coding data is used as the working clock, and the reverse link clock clk _ BLF is used as the working clock in order to simplify the design of the digital baseband; in the actual implementation of the passive ultrahigh frequency electronic tag chip digital baseband processor, an initialization module, a decoding module, a command query module, a receiving module, a main state machine module, a sending module, a coding module, a memory control module, a frequency division module, a power consumption management module and a clock domain module are further arranged in the structure, wherein the power consumption management module is used for controlling clock input signals of the modules, acquiring the working states of the modules and determining turn-off signals according to the working states;
the beneficial effects of the above technical scheme are: according to the technical scheme, different working modules work at different clock frequencies, so that the main clock frequency of the system is kept unchanged, the dynamic power consumption of the submodule is reduced by reducing the working frequency of the submodule, the overturning activity of the circuit can be reduced, and the frequency of instantaneous change is reduced.
As will be appreciated by one skilled in the art, embodiments of the present invention may be provided as a method, system, or computer program product. Accordingly, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, optical storage, and the like) having computer-usable program code embodied therein.
The present invention has been described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (8)
1. A control method of a passive ultrahigh frequency electronic tag chip digital baseband processor comprises the steps that a radio frequency analog front end, a decoder, a clock chip and a latch form the digital baseband processor; the control method is characterized by comprising the following steps:
acquiring demodulation data of a radio frequency analog front end, and performing clock synchronization on the demodulation data through a clock chip to acquire primary processing data;
decoding the primary processing data through a decoder, and latching the decoded data through a latch to acquire secondary processing data;
performing parameter check on the secondary processing data, performing CRC (cyclic redundancy check) check on the data subjected to the parameter check, and generating read data after the check is successful;
the acquiring of the demodulation data of the radio frequency analog front end, performing clock synchronization on the demodulation data through a clock chip, and acquiring primary processing data includes:
judging whether the digital baseband processor is reset or not, acquiring a clock signal input by a radio frequency analog front end after the digital baseband processor is reset according to a judgment result, and carrying out frequency division processing on the clock signal;
performing time delay processing on the clock signal subjected to frequency division processing to obtain a reset signal of the global multiplexing counter;
receiving demodulation data of a wireless radio frequency signal at a radio frequency analog front end according to a reset signal of the global multiplexing counter, synchronizing the demodulation data by a clock reset method, and determining primary processing data;
the decoding the primary processing data through a decoder, and latching the decoded data through a latch to obtain secondary processing data, includes:
performing command analysis on the primary processing data, and determining a command type and a requirement to be processed; wherein the content of the first and second substances,
the command types include at least: inquiry response command, character confirmation command, time slot parameter command, selection command, read command and write command;
judging the waveform position of the primary processing data according to the command type and the requirement to be processed, determining the waveform position, decoding according to the waveform of the waveform position, and determining command parameters; wherein the content of the first and second substances,
the decoding process at least comprises two counters, namely a first counter and a second counter;
the first counter is used for counting the number of bits of the received parameters;
the second counter is used for counting the length of each bit in the receiving parameters;
storing the command parameters by a multiplexing sharing method; wherein, the first and the second end of the pipe are connected with each other,
the multiplexing sharing method adopts a time-sharing multiplexing latch to store command parameters at any time.
2. The method as claimed in claim 1, wherein the step of performing parameter check on the secondary processing data, performing CRC check on the parameter checked data, and generating read data after the CRC check is successful comprises:
determining a high-order priority order according to the secondary processing data, serially sending the secondary processing data to a register according to the high-order priority order to perform CRC (cyclic redundancy check) in a shifting mode, and determining a shifting result;
when the shift result shows that the secondary processing data is successfully shifted, acquiring a result value of an output end of the register; wherein the content of the first and second substances,
and when each bit of the result value at the output end of the register is zero, judging that the CRC check is passed, and outputting the secondary processing data as read data.
3. The method for controlling the digital baseband processor of the passive ultrahigh frequency electronic tag chip according to claim 1, wherein the step of performing command analysis on the primary processing data to determine the command type and the requirement to be processed comprises the following steps:
performing instruction judgment on each bit of data in the primary processing data, and determining the judgment result of each bit of data;
when the judgment result shows that the instruction is not acquired, determining the instruction state of the data, and storing the instruction state;
when the judgment result shows that the instruction is obtained, determining the digit of the data, and carrying out digit labeling on the data to determine labeled data;
determining corresponding storage command parameters according to the label data, acquiring corresponding command data streams according to the storage command parameters, comparing the command data streams with preset command data streams, determining whether the command data streams corresponding to the label data are wrong or not, and acquiring a comparison result;
when the comparison result shows that the command data stream has errors, acquiring state machine parameters and resetting the state machine parameters;
and when the comparison result shows that the command data stream has no errors, starting a command data stream analysis mechanism, acquiring sub-command parameters corresponding to the command data stream, and determining a corresponding command type and a requirement to be processed according to the sub-command parameters.
4. The method of claim 1, wherein the determining the waveform location comprises:
acquiring waveform change data corresponding to the primary processing data, monitoring the waveform change data, and determining a waveform monitoring result;
and when the waveform monitoring result shows that the rising edge of the waveform is detected, determining the position of the parameter.
5. The method as claimed in claim 1, wherein the step of performing parameter check on the secondary processing data, performing CRC check on the parameter checked data, and generating read data after the check is successful, further comprises:
acquiring frame headers and command parameters corresponding to the secondary processing data, performing parameter check on the frame headers and the command parameters, and determining a parameter check result; wherein, the first and the second end of the pipe are connected with each other,
the parameter checking result comprises: the exception parameter does not exist and exists;
judging whether the secondary processing data has a receiving error condition according to the parameter checking result;
when the judgment result shows that the parameter checking result has a receiving error, determining an error type; wherein the content of the first and second substances,
the error types include: setting a flag bit to be wrong, not updating a time slot counter, not updating a Q value, and skipping a chip;
and executing a corresponding error repair scheme according to the error type.
6. The method as claimed in claim 5, wherein said performing a corresponding error recovery scheme according to said error type comprises:
when the error type corresponds to a flag bit setting error, acquiring a reader-writer sending instruction, matching the sending instruction with an internal preset storage value by the electronic tag, determining a matching result, and when the matching result shows that the matching is successful, setting the flag bit according to the sending instruction;
when the error type is not updated correspondingly to the time slot counter, determining an initial environment type, when the initial environment type is a multi-tag environment, generating a random number, storing the random number into the time slot counter, monitoring a tag response value of the time slot counter, and when the tag response value is zero, generating a new random number and sending the new random number to a reader-writer; wherein the content of the first and second substances,
the initial environment types include: single-label environments and multi-label environments;
when the error type corresponds to that the Q value is not updated, sending a non-zero Q value through a reader-writer to update the Q value;
when the error type corresponds to that the chip jumps, acquiring a tag state value and reader-writer response time, storing the tag state value, acquiring a storage result, judging whether the reader-writer response time is greater than a preset time threshold, if the reader-writer response time is not greater than the preset time threshold, acquiring a command sent by reading and writing to compare command parameters, and jumping the tag state according to a preset rule according to the comparison result.
7. The method as claimed in claim 1, wherein the step of performing parameter check on the secondary processing data, performing CRC check on the parameter checked data, and generating read data after the check is successful, further comprises:
performing FPGA verification on the read data subjected to CRC; wherein the content of the first and second substances,
the FPGA verification process comprises the following steps:
adding constraint types according to the time sequence information in the read data, and determining a first check result; wherein the content of the first and second substances,
the constraint types include: timing constraints, grouping constraints, area constraints, pin constraints, proprietary constraints;
the timing constraints are periodically set for data;
the grouping constraint is achieved by grouping clocks;
the pin constraint is realized by acquiring input and output signals and transmitting the input and output signals to an FPGA output pin;
the special constraint is realized by setting a special virtual path for data;
monitoring the input and output waveforms of the digital baseband processor through an oscilloscope based on the first check result, and comparing the input and output waveforms with a preset input and output waveform threshold range to determine a comparison result;
and when the comparison result shows that the input and output waveforms of the digital baseband processor are within a preset input and output waveform threshold range, judging that the read data time sequence is consistent.
8. The method as claimed in claim 1, wherein the clock synchronization of the clock chip further comprises a plurality of clock domains; wherein the content of the first and second substances,
the clock domain includes: clk _ m clock domain, clk _ tpp clock domain, clk _ BLF clock domain;
the clk _ m is provided by an analog radio frequency front end for a system main clock;
the clk _ TPP is a TPP coded data clock, and the decoding module is used for decoding the TPP coded data and processing command parameters;
the clk _ BLF is the tag reverse link clock, generated by the DIV module, used to recover the data.
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