CN101441703B - Coding and decoding circuit of super high frequency radio frequency personal identification system - Google Patents

Abstract

The invention discloses a coding and decoding circuit for a system of ultra-high frequency radio frequency identification (UHF RFID). Every time when error codes are found, the coding and decoding circuit based on the prior cyclic redundancy check (CRC) circuit resends, thus frequency of communication between a reader-writer and a tag can be increased in the situation of long distances of reading and writing and serious noise interference. If the speed of reading and writing is definite, time for successfully reading once is certainly extended, thereby influencing practicability and reliability of the UHF RFID system in the situation of reading and writing at high speed. To solve the problem, the invention is provided with a convolution error correcting code, adopts concatenation connection with the CRC circuit to reduce frequency of reading and writing, so as to improve the successful reading rate of the system in certain time. The CRC circuit of the invention is a parallel circuit with compact conformation and fast arithmetic designed based on FPGA, thereby further reducing time of communication between the reader and the tag, and increasing the amount of tag identification in unit time.

Description

A kind of coding and decoding circuit of super high frequency radio frequency personal identification system

Technical field

The invention belongs to the RFID communications field, relate to a kind of coding and decoding circuit of super high frequency radio frequency personal identification system.

Background technology

The super high frequency radio frequency recognition technology, decipherment distance is far away, and the increasing fields such as logistics management, traffic management, factory's work piece production control that are applied to have produced huge economic benefit.Although a lot of successful application cases are arranged, fading channel, signal multipath disturb ultrahigh-frequency radio-frequency identification system, the problem of many labels collision owing to reading/writing distance exists greatly, and security and reliability can't guarantee, have had a strong impact on its large-scale commercial application.Therefore significant with improvement to the super high frequency radio frequency systematic research, particularly high at a high speed design of reading the ultrahigh-frequency radio-frequency identification system of success ratio has more challenge, and actual application value is more arranged.

Summary of the invention

For the coding and decoding circuit based on CRC (CRC), because each error code of finding all will be retransmitted, therefore for the serious occasion of the big noise of reading/writing distance, the number of communications between read write line and the label will increase.Suppose under the certain situation of read or write speed, must prolong the time of once successfully reading, influence ultrahigh-frequency radio-frequency identification system in practicality and the reliability of reading and writing occasion at a high speed.In order to address this problem, the present invention has designed the coding and decoding circuit of new radio-frequency recognition system, i.e. a kind of coding and decoding circuit of super high frequency radio frequency personal identification system.

Technical solution of the present invention is following:

A kind of coding and decoding circuit of super high frequency radio frequency personal identification system comprises coding circuit, decoding scheme and CRC circuit, it is characterized in that, also comprises convolutional encoding circuit and convolution decoder circuit; Described CRC circuit connects data bus; The input end of the described convolutional encoding circuit of its output termination; The input end of the output termination coding circuit of convolutional encoding circuit, the output signal of coding circuit is sent to the signal receiving end of super high frequency radio frequency personal identification system; The signal receiving end of the input termination super high frequency radio frequency personal identification system of said decoding scheme is to receive data; The input end of the output termination convolution decoder circuit of said decoding scheme, the input end of the output termination CRC circuit of said convolution decoder circuit.

Described convolutional encoding circuit adopts the convolution coding of " 2,1,3 "; Described convolution decoder circuit adopts viterbi coding method to decode.

As improvement, described CRC circuit is the CRC circuit of parallel input and line output.

The CRC circuit of described parallel input and line output is:

Generator polynomial is G (g ₀, g ₁... G _m), the input data are D (d ₀, d ₁... D _k), be output as X (x ₀, x ₁... X _m); Each parallel processing figure place is m, process

The individual clock period, circuit output CRC extra-code; Have:

$X\′\left(0\right)=F\⊗X\left(0\right)\⊕D;$

$X\′=F^m\⊗X\⊕D;$

Wherein, $F=\left[\begin{array}{ccccc}{g}_{m-1}& 1& 0& ...& 0\\ g_{m-2}& 0& 1& ...& 0\\ ...& ...& ...& ...& 0\\ {\mathrm{<figure-callout\; id="1"\; label="g"\; filenames="DEST\_PATH\_H200810143062201E00012.png,DEST\_PATH\_H200810143062201E00021.png"\; state="\{\{state\}\}">g</figure-callout>}}_1& 0& 0& ...& 1\\ {\mathrm{<figure-callout\; id="0"\; label="g"\; filenames="DEST\_PATH\_H200810143062201E00021.png"\; state="\{\{state\}\}">g</figure-callout>}}_0& 0& 0& ...& 0\end{array}\right]$ Be m * m matrix, the original state of X (0) expression register, the next state of X ' (0) expression register,

Symbolic representation and XOR more later on,

The symbolic representation XOR, $F^m=[F^{m-1}\&CircleTimes;g\&prime;|\&CenterDot;\&CenterDot;\&CenterDot;F\&CircleTimes;g\&prime;|g\&prime;],$ G=(g _M-1G ₁g ₀) ^TF ^mThe gating matrix that enables for the CRC circuit of parallel input and line output.

Beneficial effect:

Mentality of designing of the present invention is to add convolution error correcting code, and and the mode of CRC circuits cascading reduce between read write line and the label and read and write number of times, improved the successful within a certain period of time read rate of system.CRC circuit among the present invention is based on the compact conformation of FPGA design realization, the parallel circuit of fast operation, has further reduced the communication time between reader and label.Compared with prior art, advantage of the present invention just is: owing to introduced the convolution coding-decoding circuit, significantly improved system's error correcting capability, strengthened the stability and the reliability of system; In addition, the CRC circuit that improves original serial is parallel CRC circuit, has also obviously improved the treatment effeciency of the data-handling capacity and the system of system.

Description of drawings

Fig. 1 is the radio-frequency recognition system general structure theory diagram that relates to of the present invention

Fig. 2 is existing radio-frequency recognition system coding and decoding circuit theory diagram;

Fig. 3 is CRC of the present invention and convolution cascade coding and decoding circuit theory diagram;

Fig. 4 is a convolutional encoding circuit of the present invention;

Fig. 5 is a Parallel CRC circuit of the present invention;

Fig. 6 (a) is the sequential of linear feedback shift register CRC circuit; (b) be the sequential of Parallel CRC circuit;

Fig. 7 is existing general linear feedback shift register circuit.

Embodiment

Below will combine accompanying drawing and practical implementation process that the present invention is explained further details:

Embodiment 1:

The present invention considers to be made up of reader and electronic tag two parts like Fig. 1 radio-frequency recognition system.In electronic tag got into the reader EFFECTIVE RANGE, both sides can communicate through electromagnetic field according to certain agreement.Reader and electronic tag can be divided into mimic channel and digital baseband part on structure.The mimic channel of label comprises mu balanced circuit and radio-frequency interface circuit, and mu balanced circuit is responsible in radiofrequency signal, obtaining energy and is offered the use of label digital baseband part, and radio-frequency interface circuit then is responsible for the modulation transmission and the receiving demodulation of radiofrequency signal.Digital baseband part comprises coding and decoding circuit, clock circuit, system state machine, storage system.The NRZ that coding and decoding circuit will be fit to digital processing is converted into other codings that are suitable for Channel Transmission, and the affix error control code; Clock circuit produces the frequency of operation of system; The system state machine produces the control signal of total system; The storage system stored protocol information.

The ISO/IEC18000-6 standard definition air interface and the communication protocol of radio-frequency recognition system in 860～960MHz band limits.Two types of non-contact radio-frequency card Type A and Type B have been stipulated.These two types of cards all adopt ASK modulation (amplitude-shift keying modulation) mode, have a reader pattern (Reader talks first) earlier, and the FMO coding is all adopted to link in the back, all uses the CRC check sign indicating number.Difference is that the forward link of Type A adopts the PIE coding, and what anti-collision algorithms was used is the ALOHA agreement; Type B agreement adopts the Manchester coding, and anti-collision algorithms is used binary tree.According to the ISO/IEC18000-6 standard, codec module comprises CRC check circuit, coding circuit, decoding scheme, control circuit, clock division circuits (as shown in Figure 2).

The basic thought of CRC check circuit is: produce the sign indicating number sequence that a string verification is used at transmitting terminal according to the certain according to this rule of binary number that will transmit, and the information that is attached to sends at the back.At receiving end, whether make mistakes in then transmitting according to the rule judgment of being followed between information code and the check code.According to agreement, the ultrahigh frequency system adopts CRC-5 and CRC-16, and generator polynomial is respectively x ⁵+ x ³+ 1 and x ¹⁶+ x ¹²+ x ⁵+ 1.

Coding circuit and decoding circuit adopt the PIE coding based on agreement category-A card forward link, and category-B card forward link adopts graceful Chester coding, and the back of two kinds of cards all adopts the FMO coding to link.

Control circuit comes programming Control with the MCU chip.It mainly is used for controlling the co-ordination of codec module each several part and as the interface of codec module and system, accepts the order of system state machine.Clock division circuits produces the required frequency of operation of various circuit in the codec module through the frequency division to system clock.

Can know that through above analysis find at every turn that based on the codec module of CRC circuit error code all will retransmit, therefore for the serious occasion of the big noise of reading/writing distance, the number of communications between read write line and the label will increase to codec module.Suppose under the certain situation of read or write speed, must prolong the time of once successfully reading.Recognition and tracking that this must influence ultrahigh frequency system workpiece on highway unmanned charge station, streamline etc. is read and write the practicality and the reliability of occasion at a high speed.In order to address this problem, the present invention proposes the adding convolution error correcting code, and reduce the read-write number of times with the mode (see figure 3) of CRC circuits cascading, thus the successful within a certain period of time read rate of raising system.Increase the convolutional encoding sign indicating number time though add the convolutional code circuit, reduced the time of repeated communications.Along with made of hardware circuits which process speed is more and more faster, advantage is obvious more.

Coding and decoding circuit system works flow process proposed by the invention is: delivery section adds check code through the CRC circuit earlier to data, carries out convolutional encoding then and sends.Receiving end carries out convolution decoder, CRC school sign indicating number then earlier.For general error code, just can correct at the convolution decoder end; The not correctable error that has only continuous a plurality of error code to cause is just found by CRC school sign indicating number, and requires to retransmit.

The present invention adopts the convolutional code of (2,1,3), deciphers with Viterbi (Viterbi) interpretation method.The convolution coder principle is as shown in Figure 4.The coding rule of (2,1,3) convolutional code is the code character that is encoded into 1 bit information 2 bits, but the code character of being weaved into not only with the information-related of current input but also information-related with 2 bits in front, generator polynomial G (z) (referring to Fig. 4) as follows:

$G\left(z\right)=\left[\begin{array}{c}1+z^2\\ 1+z+z^2\end{array}\right]$

$\left\{\begin{array}{c}{Y}_1\left(z\right)=X\left(z\right)(1+z^2)\\ Y_2\left(z\right)=X\left(z\right)(1+z+z^2)\end{array}\right.$

X in the following formula (z) is the input of convolution coder, and Y (z) is the output of convolution coder.

The decoding of convolutional code can be divided into two types of algebraic decoding and probabilistic decodings, and wherein algebraic decoding generally only is used for simple convolutional encoding; Viterbi decoding algorithm belongs to the maximum-likelihood decoding in the probabilistic decoding.The concrete steps of Viterbi decoding are following: each individual path of each state of entering and the Hamming distance (hard decision) between the receiving symbol are calculated in (1), and this distance is called the branch metric of this branch.(2) the corresponding separately together previous moment state measurement addition summation of each branch metric, obtain path metric.In each state, select in the path metric that arrives this state and keep the state measurement of reckling as current time.Keep corresponding with it path simultaneously as survivor path.(3) in the survivor path of each state, select minimum one of state measurement, recall, obtain decoding output along this.

In order to improve the data processing speed of radio-frequency recognition system, increase the tag recognition amount in the unit interval, the present invention has designed new coding and decoding CRC (CRC) circuit.

Linear feedback shift register (LFSR) is realized CRC relatively, and parallel cyclic redundancy check (CRC) circuit is all comparatively complicated on algorithm and circuit.For reducing the complicacy of circuit, reduce the area of label chip, simple algorithm and circuit are the keys of Parallel CRC circuit design.

Parallel CRC circuit design and algorithm that the present invention proposes are following:

If generator polynomial is G (g ₀, g ₁... G _m), the input data are D (d ₀, d ₁... D _k), be output as X (x ₀, x ₁... X _m).Each parallel processing figure place is m; Then pass through

the individual clock period, circuit output CRC extra-code.

Construct a m * m matrix $F=\left[\begin{array}{ccccc}{g}_{m-1}& 1& 0& ...& 0\\ g_{m-2}& 0& 1& ...& 0\\ ...& ...& ...& ...& 0\\ {\mathrm{<figure-callout\; id="1"\; label="g"\; filenames="DEST\_PATH\_H200810143062201E00012.png,DEST\_PATH\_H200810143062201E00021.png"\; state="\{\{state\}\}">g</figure-callout>}}_1& 0& 0& ...& 1\\ {\mathrm{<figure-callout\; id="0"\; label="g"\; filenames="DEST\_PATH\_H200810143062201E00021.png"\; state="\{\{state\}\}">g</figure-callout>}}_0& 0& 0& ...& 0\end{array}\right],$ If with the original state of X (O) expression register, the next state of X ' (0) expression register, and with

Symbolic representation and XOR more later on,

The symbolic representation XOR, then:

$X\&prime;\left(0\right)=F\&CircleTimes;X\left(0\right)\&CirclePlus;D;$

Can recursion go out:

$X\&prime;=F^m\&CircleTimes;X\&CirclePlus;D;$

Wherein $F^m=[F^{m-1}\&CircleTimes;g\&prime;|\&CenterDot;\&CenterDot;\&CenterDot;F\&CircleTimes;g\&prime;|g\&prime;],$ G '=(g _M-1G ₁g ₀) ^T

The Parallel CRC circuit is as shown in Figure 5, F ^mThe gating matrix that enables for circuit.

With CRC-5, generator polynomial is x below ⁵+ x ³+ 1 (101001) enables matrix F for example explanation ^mProduction process.

At first construct m * m matrix $F=\left[\begin{array}{ccccc}0& 1& 0& 0& 0\\ 1& 0& 1& 0& 0\\ 0& 0& 0& 1& 0\\ 0& 0& 0& 0& 1\\ 1& 0& 0& 0& 0\end{array}\right],$ Then can recursion go out column matrix down:

$F^2=\left[\begin{array}{cc}1& 0\\ 0& 1\\ 0& 0\\ 1& 0\\ 0& 1\end{array}\right|\left.\begin{array}{ccc}1& 0& 0\\ 0& 1& 0\\ 0& 0& 1\\ 0& 0& 0\\ 0& 0& 0\end{array}\right],$ $F^3=\left[\begin{array}{ccc}0& 1& 0\\ 1& 0& 1\\ 1& 0& 0\\ 0& 1& 0\\ 1& 0& 1\end{array}\right|\left.\begin{array}{cc}1& 0\\ 0& 1\\ 0& 0\\ 0& 0\\ 0& 0\end{array}\right]\&CenterDot;\&CenterDot;\&CenterDot;\&CenterDot;\&CenterDot;\&CenterDot;$ $F^5=\left[\begin{array}{ccccc}1& 1& 0& 1& 0\\ 1& 1& 1& 0& 1\\ 1& 0& 1& 0& 0\\ 0& 1& 0& 1& 0\\ 1& 0& 1& 0& 1\end{array}\right]$

Use

The output of expression register, [x ₄x ₃x ₂x ₁x ₀] ^TThe input of expression register, [d ₄d ₃d ₂d ₁d ₀] ^TExpression input data, then:

$x_4^{\&prime;}=x_4\&CirclePlus;x_3\&CirclePlus;x_1\&CirclePlus;d_4$

$x_3^{\&prime;}=x_4\&CirclePlus;x_3\&CirclePlus;x_2\&CirclePlus;x_0\&CirclePlus;d_3$

$x_2^{\&prime;}=x_4\&CirclePlus;x_2\&CirclePlus;d_2$

$x_1^{\&prime;}=x_3\&CirclePlus;x_1\&CirclePlus;{\mathrm{<figure-callout\; id="1"\; label="d"\; filenames="DEST\_PATH\_H200810143062201E00012.png,DEST\_PATH\_H200810143062201E00021.png"\; state="\{\{state\}\}">d</figure-callout>}}_1$

$x_0^{\&prime;}=x_4\&CirclePlus;x_2\&CirclePlus;x_0\&CirclePlus;{\mathrm{<figure-callout\; id="0"\; label="d"\; filenames="DEST\_PATH\_H200810143062201E00021.png"\; state="\{\{state\}\}">d</figure-callout>}}_0$

For time-invariant system, promptly generator polynomial enables later can the cancelling with door of control end for fixing CRC circuit among Fig. 5, is general CRC circuit diagram shown in Fig. 5, has only and confirms could confirm circuit after parallel bit wide and the generator polynomial.Number of registers is parallel bit wide among the figure, and generator polynomial confirms to enable the logical relation of matrix, e _{(m, m)}Be 1 to open and door, allow register next state input or door; e _{(m, m)}Be 0 to forbid.The left side is a m bar vertical line among Fig. 5, is each register and e _{(m, m)}The connecting line of matrix.Can be found out by Fig. 5: adopt parallel circuit not make CRC CRC circuit obviously complicated, radio-frequency recognition system label chip area increases limited.

Experimental analysis:

Utilize the fpga chip of Xilinx company; Spartan2E series xc2s50e; On Xilinx ISE7.1i platform; Respectively 1. the linear feedback shift register circuit of 1. inserting the register original state in advance (is called for short circuit; See ISO/IEC18000-6C standard accessory A), 2. general linear feedback shift register circuit (see circuit shown in Figure 7, be called for short circuit 2.) and 3. the novel parallel circuit (see circuit shown in Figure 5, be called for short circuit 3.) that proposes of the present invention realize that the CRC CRC makes an experiment and tests.Fig. 6 (a) is the timing sequence test figure (1., 2. identical) of linear feedback shift register CRC circuit, and Fig. 6 (b) is the timing sequence test figure of Parallel CRC circuit.

Fig. 6 has tested the CRC-16 computing of 24 Bit datas, and generator polynomial is x ¹⁶+ x ¹²+ x ⁵+ 1,1., 2. circuit has used 25 clock period (a clock period initialization); And 3. circuit has only used 3 clock period.

3 circuit are as shown in table 1 in fpga chip resource operating position:

Table 1.FPGA resources of chip operating position table

System resource (always)	Circuit 1.	Circuit 2.	Circuit 3.
				Logical block section Slice (768)	9(1％)	33(4％)	18(2％)
Latch Flip-Flops (1536)	16(1％)	50(3％)	16(1％)
				Look-up table LUT (1536)	0(0％)	38(2％)	35(2％)

Can find out by table 1: the relative serial linear feedback shift register of the novel Parallel CRC circuit of the present invention CRC circuit; (1. circuit is the custom chip circuit to the unobvious increase of complicated circuit degree; So it is minimum that resource is used), but processing speed is significantly fast.

A large amount of experiments show that the improvement ultrahigh-frequency radio-frequency identification system coding and decoding circuit of the adding convolutional code compiler that the present invention proposes can reduce the error correction number of times of CRC CRC circuit; Thereby reduce the number of communications of label and reader, improved the stability and the reliability of high speed long distance radio system; The novel Parallel CRC circuit data fast operation of the present invention's design, circuit is simple, can improve radio-frequency recognition system coding and decoding data processing speed frequently well, increases the tag recognition amount in the unit interval.Simultaneously, because circuit is simple relatively, the label chip area increases limited, can not exert an influence to the label cost basically, and good practical value is arranged.

Claims (1)

1. the coding and decoding circuit of a super high frequency radio frequency personal identification system comprises coding circuit, decoding scheme and CRC circuit, it is characterized in that, also comprises convolutional encoding circuit and convolution decoder circuit; Described CRC circuit connects data bus; The input end of the described convolutional encoding circuit of its output termination; The input end of the output termination coding circuit of convolutional encoding circuit, the output signal of coding circuit is sent to the signal receiving end of super high frequency radio frequency personal identification system; The signal receiving end of the input termination super high frequency radio frequency personal identification system of said decoding scheme is to receive data; The input end of the output termination convolution decoder circuit of said decoding scheme, the input end of the output termination CRC circuit of said convolution decoder circuit;

Described convolutional encoding circuit adopts the convolution coding of " 2,1,3 "; Described convolution decoder circuit adopts viterbi coding method to decode;

Described CRC circuit is the CRC circuit of parallel input and line output;

The CRC circuit of described parallel input and line output is:

Generator polynomial is G (g ₀, g ₁... G _m), the input data are D (d ₀, d ₁... D _k), be output as X (x ₀, x ₁... X _m); Each parallel processing figure place is m, process

The individual clock period, circuit output CRC extra-code; Have:

$X^{\&prime;}\left(0\right)=F\&CircleTimes;X\left(0\right)\&CirclePlus;D;$

$X^{\&prime;}=F^m\&CircleTimes;X\&CirclePlus;D;$

Wherein, $F=\left[\begin{array}{ccccc}{g}_{m-1}& 1& 0& ...& 0\\ g_{m-2}& 0& 1& ...& 0\\ ...& ...& ...& ...& 0\\ g_1& 0& 0& ...& 1\\ g_0& 0& 0& ...& 0\end{array}\right]$ Be m * m matrix, the original state of X (0) expression register, the next state of X ' (0) expression register, Symbolic representation and XOR more later on,

The symbolic representation XOR, $F^m=[F^{m-1}\&CircleTimes;g^{\&prime;}|...F\&CircleTimes;g^{\&prime;}\left|g^{\&prime;}\right],g^{\&prime;}={(g_{m-1}...g_1{g}_0)}^T;$ F ^mBe the gating matrix that enables of the CRC circuit of parallel input and line output, the coding and decoding circuit of described super high frequency radio frequency personal identification system adopts FPGA to realize.

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