CN108352838A - High-jitter-tolerance without reference frequency detector - Google Patents

High-jitter-tolerance without reference frequency detector Download PDF

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Publication number
CN108352838A
CN108352838A CN201580084028.0A CN201580084028A CN108352838A CN 108352838 A CN108352838 A CN 108352838A CN 201580084028 A CN201580084028 A CN 201580084028A CN 108352838 A CN108352838 A CN 108352838A
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signal
dff
sampled
coupled
nand gate
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CN108352838B (en
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谷亮
曹玉明
雷工
党殷
顾凡
顾一凡
李洪义
玛曼莎·德什潘德
施守波
段彦
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Huawei Technologies Co Ltd
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Huawei Technologies Co Ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D13/00—Circuits for comparing the phase or frequency of two mutually-independent oscillations
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/0944—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET
    • H03K19/0948—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET using CMOS or complementary insulated gate field-effect transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/135—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/14—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of delay lines
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/0807—Details of the phase-locked loop concerning mainly a recovery circuit for the reference signal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0008—Synchronisation information channels, e.g. clock distribution lines
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0016—Arrangements for synchronising receiver with transmitter correction of synchronization errors
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/00078—Fixed delay

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  • Computer Networks & Wireless Communication (AREA)
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  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Nonlinear Science (AREA)
  • Power Engineering (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Manipulation Of Pulses (AREA)

Abstract

A kind of device includes：First sample circuit, for being sampled to clock signal according to data-signal, to generate the first sampled signal；Second sample circuit, for being sampled to the clock signal according to postpones signal, to generate the second sampled signal；And it is coupled to the control circuit of first sample circuit and second sample circuit, wherein, the control circuit is used to be executed with non-(NAND) operation according to first sampled signal and second sampled signal, the activation signal with generation for activating the frequency of the clock signal to adjust.

Description

High-jitter-tolerance without reference frequency detector
CROSS REFERENCE TO RELATED application
This application claims submit on October 28th, 2015 it is entitled " high-jitter-tolerance without reference frequency detect The earlier application priority of 14/925th, No. 716 U.S. Non-provisional Patent application case of device ", the full content of the earlier application It is hereby incorporated herein by this.
Background technology
Circuit between two chips by High Speed System, such as in highly integrated system or in one single chip it Between, the data of transmission are usually sent in the case where being not accompanied by clock signal.Although unclocked data transmission reduces complexity Degree and power consumption, but data sink is needed to generate clock signal to restore data.Receiver can be used clock and data extensive Multiple (CDR) circuit is come the synchronous clock signal of the phase and frequency that generates with receive data.Therefore, accurate detection receives data Phase and frequency offset between phase and frequency or clock signal and data-signal communicates guarantee quality data Critically important, especially for the high-speed data system to be worked to about 100Gbps with about 10 gigabit/secs (Gbps).
Invention content
In one embodiment, the present invention includes a kind of device, including：First sample circuit, for according to data-signal Clock signal is sampled, to generate the first sampled signal；Second sample circuit is used for according to delayed data signal to described Clock signal is sampled, to generate the second sampled signal；And it is coupled to first sample circuit and second sampling The control circuit of circuit, wherein the control circuit according to first sampled signal and second sampled signal for holding Row and non-(NAND) operation, to generate the activation signal for activating the frequency of the clock signal to adjust.
In another embodiment, the present invention includes a kind of method, including：Clock signal is adopted according to data-signal Sample, to generate the first sampled signal；The duration that the data-signal is postponed to the chronomere of a quarter is prolonged with generating Slow signal；The clock signal is sampled according to the postpones signal, to generate the second sampled signal；And according to described First sampled signal and second sampled signal execute NAND operation, to generate for activating charge pump by the clock signal Frequency snap to the data-signal frequency activation signal.
In yet another embodiment, the present invention includes a kind of device, including：NAND gate, including the first NAND gate input terminal Mouth, the second NAND gate input port and NAND gate output port；And voltage and current (V2I) converter, including V2I switch actives Port and V2I conversion output currents port, wherein the NAND gate output is coupled in V2I switch actives port, described It is coupled to frequency detecting loop filter in V2I conversion output currents port.
In detailed description below and combination drawings and claims, it can be more clearly understood that these and other spy Sign.
Description of the drawings
In order to be best understood from the present invention, said briefly below referring now to what is described in conjunction with the drawings and specific embodiments Bright, same reference numerals therein indicate same section.
Fig. 1 for no reference frequency detector schematic diagram.
Fig. 2 is the figure for the waveform simulated at a lock condition without reference frequency detector for showing Fig. 1.
Fig. 3 is the figure for the waveform captured in shake without reference frequency detector for showing Fig. 1.
Fig. 4 is the figure for the eye pattern captured without reference frequency detector when experience is shaken for showing Fig. 1.
Fig. 5 is the schematic diagram that no reference frequency detector is trembled according to the appearance of one embodiment of the invention.
Fig. 6 is the schematic diagram for holding the scheme for trembling no reference frequency detector according to a kind of implementation of one embodiment of the invention.
Fig. 7 is the schematic diagram according to the negative circuit of one embodiment of the invention.
Fig. 8 is the schematic diagram according to the buffer circuit of one embodiment of the invention.
Fig. 9 is according to the common mode logic of one embodiment of the invention to CMOS complementary metal-oxide-semiconductor (CML-to- CMOS) the schematic diagram of level shifting circuit.
Figure 10 is the schematic diagram according to the NAND gate of one embodiment of the invention.
Figure 11 be according to one embodiment of the invention show the appearance of Fig. 5 tremble no reference frequency detector undergo shake when catch The figure of the waveform obtained.
Figure 12 be according to one embodiment of the invention show the appearance of Fig. 5 tremble no reference frequency detector undergo shake when catch The figure of the eye pattern obtained.
Figure 13 is that the method detected without reference frequency is executed when undergoing shake according to a kind of of one embodiment of the invention Flow chart.
Specific implementation mode
First it should be understood that although the illustrated embodiment of one or more embodiments is provided below, disclosed is Any number of technology can be used to implement for system and/or method, and no matter the technology is currently known or existing.The present invention determines It should not necessarily be limited by illustrated embodiment described below, attached drawing and technology, including illustrated and described here exemplary set Meter and embodiment, but can be changed in the scope of the appended claims and the full breadth of its equivalent.
Frequency detector usually uses in the CDR based on phaselocked loop (PLL), with the recovery time information from data.Nothing Reference frequency detector refers to a kind of frequency detector including frequency detecting loop, and the frequency detecting loop is in an out-of-lock condition Automatic activation, and deactivated automatically after completing frequency acquisition, without using reference clock or lock detector.Save reference Clock and lock detector reduce the quantity of hardware component and reduce power consumption.Therefore, no reference frequency detector can be CDR A kind of attractive scheme is provided.
Fig. 1 for no reference frequency detector 100 schematic diagram.Frequency detector 100 includes three D flip-flops (DFF) 111,112 and 113, delay buffer 120 and charge pump 130.DFF 111,112 and 113 includes the data-in port for being shown as D 114, input end of clock mouth 115 and it is shown as the output port 116 of Q.DFF 111,112 and 113 further includes for passing through clock Clock signal at input port 115 samples the digital data signal at data-in port 114 and passes through output end Mouth 116 exports the circuit of sampled signals.Above-mentioned sampling can be executed in the rising edge or falling edge of clock cycle.Delay buffer 120 include the circuit for input signal to be postponed to a period of time, this time can be about holding for the chronomere of a quarter The continuous time.Charge pump 130 includes the circuit for the electric current flowing in control loop filter.For example, charge pump 130 can be Include by the V2I converters of the current source driven to and from the electric current of loop filter.
Frequency detector 100 receives data-signal VBWith clock signal CK as input.Clock signal CK is by voltage controlled oscillation Device (VCO) generates.Clock signal CK is supplied to DFF 111 and 112 by corresponding data-in port 114.Data-signal VB It is supplied to DFF 111 by the input end of clock mouth 115 of DFF 111.Data-signal postpones about four points by delay buffer 120 One of chronomere, to generate postpones signal VD, postpones signal VDIt is supplied to by the input end of clock mouth 115 of DFF 112 DFF 112.DFF 111 is in data-signal VBRising edge to clock signal CK carry out sampling and by the output end of DFF 111 Mouth 116 exports sampled output signal Q1.Similarly, DFF 112 is in postpones signal VDRising edge clock signal CK is sampled And sampled output signal Q is exported by the output port of DFF 112 1162.Output signal Q1And Q2Including identical period, this week Phase and data-signal VBDifference on the frequency between clock signal CK is directly proportional or inverse ratio.Output signal Q1And Q2Between opposite phase Move the polarity for indicating difference on the frequency.As output signal Q1More than output signal Q2When, the frequency of clock signal CK is less than data-signal VB Frequency.As output signal Q1Less than output signal Q2When, the frequency of clock signal CK is more than data-signal VBFrequency.
DFF 113 is coupled to the output port 116 of DFF 111 and 112.The data input pin that DFF 113 passes through DFF 113 Mouth 114 receives output signal Q1And output signal Q is received by the input end of clock mouth 115 of DFF 1132.DFF 113 is by defeated Go out signal Q2To output signal Q1It is sampled.As output signal Q1More than output signal Q2When, DFF 113 generates logically high electricity Flat output signal Q3.As output signal Q1Less than output signal Q2When, DFF 113 generates the output signal Q of logic low3。 Logic high indicates that binary value 1, logic low indicate binary value 0.The voltage of logic high and logic low Level depends on the supply voltage that frequency detector 100 uses.Due to output signal Q3Carry data-signal VBWith clock signal CK Between difference on the frequency polarity, so output signal Q3Charge pump 130 be may be used to indicate to loop filter charge or discharge.Ring The output voltage of path filter is increased or decreased with loop filter charge or discharge.Therefore, the output of loop filter Voltage can be used for controlling VCO, wherein the frequency of clock signal CK is directly proportional to output voltage.For example, charge pump 130 is exporting Signal Q3To be used to charge to loop filter when high level, and in output signal Q3To be used for loop filter when low level Electric discharge.When the Frequency Locking of clock signal CK is to data-signal VBFrequency when, need deactivate loop filter charging or Electric discharge.As shown, output signal Q2Activation and deactivation for controlling charge pump 130.The activation of charge pump 130 is low electricity It is flat effective, therefore output signal Q2Inversion signal for activating and deactivate charge pump 130, as shown in bubble 140.It is correcting Clock signal CK is with matched data signal VBFrequency after, signal CK can be used for data-signal VBOr data-signal VBPair When originally resetting or sampled to carry out data recovery, it is described more fully below.
Fig. 2 is the Figure 200 for the waveform for showing that no reference frequency detector 100 is simulated at a lock condition.Locking condition is The frequency of clock signal of the finger for being sampled to input data signal is approximately equal to the condition when frequency of input data signal. In Figure 200, x-axis indicates that the time of certain constant units, y-axis indicate the voltage of certain constant units.Waveform VB210 correspond to Data-signal V in frequency detector 100B.Waveform VD220 correspond to the postpones signal V in frequency detector 100D.Waveform VC230 correspond to the data-signal V for the duration for delaying about eighth chronomereB.Waveform CK 240 corresponds to Clock signal CK in frequency detector 100.Waveform Q1250 correspond to the output letter of the DFF 111 in frequency detector 100 Number Q1.Waveform Q2260 correspond to the output signal Q of the DFF 112 in frequency detector 1002.As shown, working as clock signal The Frequency Locking of CK is to data-signal VBFrequency when, data-signal VBIn bits switch always occur in clock signal CK and be When low level, as shown in dotted line 271, and data-signal VDIn bits switch to always occur in clock signal CK be high electricity When flat, as shown in dotted line 272.Therefore, at a lock condition, signal Q1The logic low kept constant, signal Q2It keeps Constant logic high.Therefore, signal Q1And Q2Including the logic state 01 under locking condition.In addition, waveform CK's 240 is upper It rises edge and snaps to waveform VCBits switch in 230, as shown in dotted line 273.Therefore, original data bits can be believed by clock The failing edge of number CK is to waveform VC230 signal is sampled to restore.
However, if VBAnd VDIt shakes, then the rising edge of clock signal CK can to the left or to the right drift about moment.Occur There are many kinds of the reason of shake, such as the noise on transmission line, the intersymbol interference (ISI) in reception data flow and original transmitted Noise in source traffic.When drifting beyond time sequence allowance 281 or 282, drift can lead to VBAnd VDSimultaneously in clock signal CK It is converted when for low level or clock signal CK being high level, therefore can switching signal Q1And Q2.Switching changes Q1And Q2's Logic state, causing frequency detector 100 to have falsely detected, locking is lost and carried out to the frequency of clock signal CK need not The correction wanted.
Fig. 3 is the Figure 30 0 for the waveform for showing that no reference frequency detector 100 is captured in shake.In Figure 30 0, x-axis Indicate that the time of certain constant units, y-axis indicate that unit is the signal amplitude of voltage.Waveform Q1310 correspond to frequency detector Output signal Q in 1001.Waveform Q2320 correspond to the output signal Q in frequency detector 1002.Waveform Q3330 correspond to Output signal Q in frequency detector 1003.Signal Q1、Q2And Q3For differential signal, each signal equal, pole including amplitude Property the opposite positive negative signal of a pair.Solid-line curve corresponds to positive signal, and point curve corresponds to negative signal.Waveform 340 corresponds to by electricity The control voltage that the loop filter of 130 driving of lotus pump generates.For control voltage for driving VCO, which generates frequency detector In clock signal CK.Region 390 corresponds to the period that there is shake.As shown, waveform Q2Positive signal in 320 and Negative signal switches in the case where there is shake, leads to signal Q1And Q2It is transformed into state 00 or state 11 from lock-out state 01.When Q1And Q2When moment is transformed into state 11, due to Q as described above2It is that low level is effective to keep high level and charge pump 130, then electric Lotus pump 130 remains inactive for state.However, working as Q1And Q2When moment is transformed into state 00, due to Q2For low level, then charge pump 130 mistakenly activate, therefore loop filter is caused to carry out unnecessary change to control voltage, such as waveform VCTRL340 institutes Show.The variation of driving voltage causes VCO unstable, therefore the frequency of VCO is no longer locked to input data frequency.
Fig. 4 is to show no reference frequency detector 100 in the Figure 40 0 for undergoing the eye pattern 410 that the when of shaking captures.X-axis table Show that the time of certain constant units, y-axis indicate the signal amplitude of certain constant units.Eye pattern 410 corresponds to by frequency detector 100 data-signal when resetting.Data-signal when resetting refers to the copy to original input data signals by clock signal The sampling of progress, the clock signal are adjusted by frequency detectors such as frequency detectors 100.As shown, eye pattern 410 is due to trembling It is dynamic almost to close, thus data bit can not correctly from restatement when data-signal in restore.
Disclosed herein is the embodiments without reference frequency detector for providing high-jitter-tolerance.The disclosed embodiments Using it is a kind of include three sample circuits without reference frequency detector.First sample circuit is according to input data signal to VCO The clock signal of generation is sampled, to generate the first output signal Q1.Second sample circuit prolongs according to input data signal Slow copy samples clock signal, to generate the second output signal Q2, wherein delay is the chronomere of about a quarter Duration.Third sample circuit is sampled by second the first output signal of output signal pair, to generate third output Signal.Third output signal indicates the electric current flowing of charge pump control loop filter, so that the frequency of VCO is snapped to input The frequency of data-signal.However, the disclosed embodiments are only in Q1In logic high and Q2It is activated when in logic low Charge pump, rather than based on the Q in frequency detector 1002Directly activate charge pump.The disclosed embodiments pass through in charge pump Input be inserted into NAND gate execute activation condition, wherein Q1And Q2As input.In one embodiment, first, second and Three sample circuits are implemented by the DFF including CML logic circuits, and NAND gate is implemented by CMOS logic circuit.Therefore, exist CML to CMOS level translators are applied to before the output end of NAND gate, CML to CMOS level translators are used for defeated by first Go out signal Q1With the second output signal Q2It is transformed into the rail-to-rail signals of CMOS from CML differential signals.The use of NAND gate avoids frequency Rate detector mistakenly triggers VCO frequency correction when height is shaken.Disclosed frequency detector is suitable for be arrived with about 10Gbps It is used in the High Speed Systems such as the optical module of about 100Gbps work.
Fig. 5 is the schematic diagram that no reference frequency detector 500 is trembled according to the appearance of one embodiment of the invention.Frequency detector 500 using logical block come when frequency detector 500 being avoided to overdrive and shake VCO to the frequency of VCO carry out it is unnecessary Correction.Frequency detector 500 includes three DFF 511,512 and 513, delay buffer 520, charge pump 530 and NAND gate 540.DFF 511,512 and 513 is similar with DFF 111,112 and 113.Delay buffer 520 is similar with delay buffer 120. Charge pump 530 is similar with charge pump 130.DFF 511 passes through data-signal VBClock signal CK is sampled, to generate first Output signal Q1, wherein clock signal CK is generated by local VCO.Delay buffer 520 is by data-signal VBDelay about four/ The duration of one chronomere, to generate postpones signal VD.DFF 512 passes through postpones signal VDClock signal CK is carried out Sampling, to generate the second output signal Q2。
In order to avoid in the Frequency Locking of VCO to data-signal VBFrequency when because of shake mistakenly activate charge pump 530, frequency detector 500 uses NAND gate 540, with only in the first output signal Q1For high level and the second output signal Q2For Activation condition is executed when low level.NAND gate 540 is coupled to DFF 511 and 512, and for receiving the second output signal Q2's Reverse signal and the first output signal Q1As input.NAND gate 540 is to the second output signal Q2Reverse signal and first output Signal Q1Execute NAND operation.Following table summarizes the logic of NAND gate 540：
Table 1：The logic of NAND gate 540
As shown in table 1, NAND gate 540 is only in Q1And Q2The output of logic low is generated when including logic state 10.Due to Charge pump 530 be low level it is effective, so using signal ON/OFF come the output to NAND gate 540 before activating charge pump 530 Signal is shown as ON/OFF, is inverted.
DFF 513 passes through Q2To Q1It is sampled, to generate designation date signal VBThe difference on the frequency between clock signal CK Polar error signal Q3.Error signal Q3Drive charge pump 530 to loop filter charge or discharge, this is generated for adjusting The frequency of VCO is with matched data signal VBFrequency control voltage.Frequency detector 500 can be used for using DFF 511,512 Frequency comparison as shown in the figure is carried out with 513 or can be used for implementing similar functions using other suitable logic circuits.
Fig. 6 is to tremble no reference frequency detector according to appearances such as a kind of implementation frequency detectors 500 of one embodiment of the invention Scheme 600 schematic diagram.Scheme 600 uses three DFF modules 611,612 and 613, V2I modules 630, two CML to CMOS Module 641 and 642, NAND module 650, buffer module 660 and inversed module 670 implement frequency detector 500.Scheme 600 The positive negative signal components of a pair of of difference are indicated using difference channel and respectively by alphabetical P and letter M.Negative signal components are positive signals The reversed component of component.Scheme 600 is to a pair of of differential data signals VBM and VBP, a pair of of differential delay signal VDM and VDP and one Differential clock signal VCO_CKM and VCO_CKP are operated.Data-signal VBM and VBP correspond in frequency detector 500 Input data signal VB.Postpones signal VDM and VDP correspond to signal VBDelay the delay after about a quarter chronomere Signal VD.Clock signal CKM and CKP correspond to the clock signal CK that the VCO that frequency detector 500 controls is generated.
DFF modules 611,612 and 613 may include the CML circuits of the sampling functions for implementing DFF 511,512 and 513. Each DFF module in DFF modules 611,612 and 613 further includes：Differential data input terminal mouth 621, including terminal DM and DP；Differential clocks input port 622, including terminal CKM and CKP；And difference output port 623, including terminal QM and QP.Number According to input port 621, input end of clock mouth 622 and output port 623 respectively with data-in port 114, input end of clock mouth 115 is similar with output port 116, and provides the more detailed view of differential terminal.DFF modules 611,612 and 613 are known as sampling electricity Road.V2I modules 630, NAND module 650, buffer module 660, inversed module 670 and CML to CMOS modules 641 and 642 are known as Control circuit.
The configuration class of the configuration of DFF modules 611,612 and 613 and the DFF 511,512 and 513 in frequency detector 500 Seemingly, they intercouple.The data-in port 621 of DFF modules 611 and 612 is for being connected to this to differential clock signal VCO_CKM and VCO_CKP.The input end of clock mouth 622 of DFF modules 611 for be connected to this to differential data signals VBM and VBP.The input end of clock mouth 622 of DFF modules 612 is for being connected to this to differential delay signal VDM and VDP.DFF modules 611 Output port 623 generate a pair of of differential output signal Q1M and Q1P, this to signal be coupled to DFF modules 613 data input Port 621.The output port 623 of DFF modules 612 generates a pair of of differential output signal Q2M and Q2P, this is coupled to DFF to signal The input end of clock mouth 622 of module 613.The output port 623 of DFF modules 613 generates a pair of of differential output signal Q3M and Q3P.
CML to CMOS modules 641 and 642 include for signal is electric from CML voltage level conversions to CMOS logic voltage Flat circuit.For example, CML may include the output voltage swing lower than CMOS logic.It is every in CML to CMOS modules 641 and 642 One further includes：Differential Input port 645, including terminal VIN_M and VIN_P；And difference output port 646, including terminal VOUT_M and VOUT_P.Input port 645 receives CML differential signals, and output port 646 is generated from the CML difference letter received Number rail-to-rail signals of the CMOS converted.The internal circuit of CML to CMOS modules 641 and 642 has carried out more fully below Ground describes.The input port 645 of CML to CMOS modules 641 is used to receive signal Q1M and Q1P from DFF modules 611 and export Level offset signal Q1P_LS and Q1M_LS are generated at port 646.The input port 645 of CML to CMOS modules 642 be used for from DFF modules 612 receive signal Q2M and Q2P and generate level offset signal Q2P_LS and Q2M_LS.As shown, configuration DFF moulds Block 611,612 and 613 and the connection between CML to CMOS modules 641 and 642 so that positive signal component is connected to plus end, bears Signal component is connected to negative terminal.
NAND module 650 includes the circuit of the NAND operation for implementing NAND gate 540.Buffer module 660 includes being used for By signal buffer or the circuit of delay a period of time, the unit of this time can be the clock cycle.Inversed module 670 includes using In the circuit inverted to signal polarity.NAND module 650 is coupled to CML to CMOS modules 641 and 642, and for receiving signal Q1P_LS and Q2M_LS is as input A and B and generates the NAND of signal Q1P_LS and Q2M_LS as output Y.NAND module 650 input state and output state is shown in table 1.Inversed module 670 and buffer module 660 are coupled to NAND module 650 Output.Inversed module 670 includes for inverting the output signal of NAND module 650 to generate output signal FONOFF_M Circuit.Buffer module 660 includes the circuit for the output signal of NAND module 650 to be postponed to a period of time, this delay with The delay of inversed module 670 is similar.Buffer module 660 generates output signal FONOFF_P.Output signal FONOFF_M and FONOFF_P is used to form differential pair, to activate or deactivate V2I modules 630.
V2I modules 630 include the current source for converting the voltage into electric current.V2I modules 630 further include：Differential signal Adjust port 631, including terminal ADJM and ADJP；Difference activates port 632, including terminal ONOFFM and ONOFFP；And it is defeated Go out electric current port 633, is shown as IOUT.Signal adjusts port 631 and is used to receive output letter from the output port 623 of DFF modules 613 Number Q3M and Q3P.Activate port 632 for receiving output signal from inversed module 670 and the output end of buffer module 660 respectively ONOFFM and ONOFFP.When ONOFFP signals are in logic high, V2I modules 630 generate electric current at output port 633 Signal, wherein the magnitude of current depends on signal Q3M and Q3P.Current signal is used to drive the electric current to and from loop filter To control the frequency of VCO.
Fig. 7 is the schematic diagram according to the negative circuit 700 of one embodiment of the invention.Circuit 700 can be used in inversed module 670 To implement signal reverse function.Circuit 700 includes 710 He of n- NMOS N-channel MOS Ns (NMOS) transistor for being shown as M1 It is shown as p- NMOS N-channel MOS Ns (NMOS) transistor 720 of M2.NMOS transistor 710 and PMOS transistor 720 Drain and gate is connected with each other.The source electrode of NMOS transistor 710 is connected to the ground connection for being shown as GND.The source electrode of PMOS transistor 720 It is connected to and is shown as VDDSupply voltage.The input of phase inverter 700, is shown as A, is connected to NMOS transistor 710 and PMOS transistor 720 grid.The output of negative circuit 700, is shown as Y, is connected to the drain electrode of NMOS transistor 710 and PMOS transistor 720.When When input A is low level, NMOS transistor 710 is closed, and PMOS transistor 720 is opened, to provide output Y and VDDBetween rail Connection path.Therefore, output Y is in logic high.When it is high level to input A, NMOS transistor 710 is opened, and PMOS is brilliant Body pipe 720 is closed, to provide the connection path between output Y and GND.Therefore, output Y is in logic low.
Fig. 8 is the schematic diagram according to the buffer circuit 800 of one embodiment of the invention.Circuit 800 can be used in buffer module 600 To implement pooling feature.Circuit 800 includes two negative circuits 810 and 820 similar with negative circuit 700.Negative circuit 810 Input signal A is received, and generates the reverse signal of input signal A, is shown as Z.Negative circuit 820 receives reverse signal Z, and generates The reverse signal of signal Z, is shown as Y.Therefore, circuit 800 exports the delayed duplicate of input signal A.
Fig. 9 is the schematic diagram according to CML to the CMOS level shifting circuits 900 of one embodiment of the invention.CML to CMOS moulds Circuit 900 can be used to implement level conversion function in block 650.Circuit 900 is electric to CMOS logic voltage by CML voltage level conversions It is flat.Circuit 900 includes two differential logic parts 910 and 920 and output par, c 930.Differential logic part 910 includes being shown as The NMOS transistor 911 of M1 and the NMOS transistor 912 for being shown as M2.Differential logic part 920 includes the PMOS crystal for being shown as M3 Pipe 913 and the PMOS transistor 914 for being shown as M4.The grid of NMOS transistor 911 receives input voltage VIN P, NMOS transistor 912 grid receives input voltage VIN M.Input voltage VIN P and VINM include CML voltage levels.The leakage of NMOS transistor 911 Pole is connected to the grid of the drain electrode and PMOS transistor 914 of PMOS transistor 913.The drain electrode of NMOS transistor 912 is connected to The grid of the drain electrode and PMOS transistor 913 of PMOS transistor 914.The source electrode of NMOS transistor 911 and 912, which is connected to, to be shown as The ground connection of GND.The source electrode of PMOS transistor 913 and 914, which is connected to, is shown as VDDSupply voltage, the voltage be CMOS rail voltages. In operation, when VINP is high level, VINM is low level.Therefore, NMOS transistor 911 is opened, and NMOS transistor 912 closes It closes, it is logic low to lead to VA.The conversion of VA makes PMOS transistor 914 open, to provide VB and VDDConnection between rail Path.When VINP is low level, VINM is high level.Therefore, NMOS transistor 911 is closed, and NMOS transistor 912 is opened, It is logic low to lead to VB.The conversion of VB makes PMOS transistor 913 open, to provide VA and VDDLink road between rail Diameter.
Output par, c 930 includes two negative circuits 931 and 932 similar with negative circuit 700,810 and 820.Reverse phase Circuit 931 is coupled to signal VA, and generates the reverse signal of signal VA, is shown as VOUTP.Negative circuit 932 is coupled to signal VB, And the reverse signal of signal VB is generated, it is shown as VOUTM.Signal VOUTP and VOUTB include being related to VDDIt, should with the voltage level of GND Voltage level is cmos voltage level.
Figure 10 is the schematic diagram according to the NAND gate 1000 of one embodiment of the invention.Electricity can be used in NAND module 650 NAND operation is implemented on road 1000.Circuit 1000 include be shown respectively as M1 and M2 two NMOS transistors 1011 and 1012 and It is shown respectively as two PMOS transistors 1013 and 1014 of M3 and M4.The source electrode of NMOS transistor 1011 is connected to NMOS transistor 1012 drain electrode.The source electrode of NMOS transistor 1012 is connected to the ground connection for being shown as GND.The grid of NMOS transistor 1011 and 1012 It is connected respectively to a pair of of input A and B.The drain electrode of PMOS transistor 1013 and 1014 is connected to the drain electrode of NMOS transistor 1011, The drain electrode of NMOS transistor 1011 is the output of NAND circuit 1000, is shown as Y.PMOS transistor 1013 is connected with 1014 source electrode To being shown as VDDSupply voltage.The grid of PMOS transistor 1014 and 1013 is connected respectively to a pair of of input A and B.NMOS crystal Pipe 1011 and 1012 serves as pulldown network, wherein when it is low level to input A and B, output Y is low level.PMOS transistor The upper pull-up network of 1013 and 1014 chargings, wherein when it is low level to input A or B, output Y is high level.
Figure 11 is to show that appearance trembles the figure for the waveform that no reference frequency detector 500 captures according to one embodiment of the invention 1100.In Figure 110 0, x-axis indicates that the time of certain constant units, y-axis indicate that unit is the signal amplitude of voltage.Figure 110 0 It is generated by implementing frequency detector according to scheme 600.In Figure 110 0, solid-line curve corresponds to positive differential signal component, point Curve corresponds to negative differential signal component.Waveform Q11110 show the signal Q1M captured at the output of DFF modules 611 And Q1P.Waveform Q21120 show the signal Q2M and Q2P captured at the output of DFF modules 612.Waveform Q31130 institutes It is shown as the signal Q3M and Q3P captured at the output of DFF modules 613.Waveform F_ONOFF 1140 is shown in inversed module 670 and buffer module 660 output at the signal F_ONOFFM and F_ONOFFP that capture respectively.Waveform VCTRLShown in 1150 The control voltage signal generated for the loop filter that V2I modules 630 control.Control voltage signal is used to adjust the frequency of VCO, The VCO generates the clock signal CKM and CKP in scheme 600.As shown, working as waveform Q2Signal in 1120 is cut due to shaking When changing, the solid-line curve in waveform F_ONOFF 1140 corresponding to signal F_ONOFFP is maintained on logic high rather than switches To logic low.Compare waveform VCTRL340 and waveform VCTRL1150, waveform VCTRLV in 1150CTRLSignal stabilization, and Unlike waveform VCTRLV in 340CTRLSignal can change.
Figure 12 is to show to hold to tremble no reference frequency detector 500 in the figure for undergoing the eye pattern 1210 that the when of shaking captures 1200.In Figure 120 0, x-axis indicates that the time of certain constant units, y-axis indicate the signal amplitude of certain constant units.Eye pattern 1210, which correspond to frequency detector 500, is undergoing data-signal when being reset when shake.Compared to eye pattern 410 and eye pattern 1210, Eye pattern 1210 is open, and eye pattern 410 is to close.
Figure 13 is that the method detected without reference frequency is executed when undergoing shake according to a kind of of one embodiment of the invention 1300 flow chart.Method 1300 is used by the equal frequency detectors of frequency detector 500, and frequency detector 500 is ce circuit A part.Mechanism and frequency detector 500 that method 1300 uses and scheme 600 it is similar.At step 1310, according to data Signal samples clock signal, to generate the first sampled signal.For example, the first d type flip flop, for example, DFF 111,112, 113,511,512 and 513 or DFF modules 611,612 and 613, it can be used for sampling clock signal.In step 1320 Data-signal is postponed the duration of the chronomere of a quarter, to generate postpones signal by place.For example, being buffered with delay The buffer similar with buffer circuit 800 with 520, buffer module 660 of device 120 can be used for delayed data signal.In step 1330 Place, samples clock signal according to postpones signal, to generate the second sampled signal.At step 1340, adopted according to first Sample signal and the second sampled signal execute NAND operation, to generate activation signal.Activation signal for activate charge pump with by when The frequency of clock signal snaps to the frequency of data-signal.For example, NAND gate, such as NAND gate 540, NAND module 650 and NAND Circuit 700 can be used for executing NAND operation.In order to generate activation signal and so that charge pump is only in the first sampled signal patrols Volume state 1 and the second sampled signal activate when be in logic state 0, the reverse signal of NAND gate the second sampled signal of reception and the One sampled signal is as input.The output of NAND gate is shown in table 1 above.
Although the present invention provides multiple specific embodiments, it is to be understood that, disclosed system and method can also pass through it Its a variety of concrete form embodies, without departing from the spirit or scope of the present invention.The present invention example should be considered as it is illustrative and It is unrestricted, and the present invention is not limited to details given hereins.For example, various elements or component can be in another systems It combines or integrates in system or certain features can be omitted or not implement.
In addition, without departing from the scope of the invention, described in various embodiments and explanation is discrete or independent Technology, system, subsystem and method can be combined or integrate with other systems, module, techniques or methods.Displaying or opinion Power mode, mechanical system or other means can also be adopted via certain for discussed as coupled or directly coupled or communication other items by stating One interface, equipment or intermediate module are coupled or are communicated indirectly.Other changes replace, substitute example to those skilled in the art For be it will be apparent that all without departing from spirit and scope disclosed herein.

Claims (20)

1. a kind of device, which is characterized in that including：
First sample circuit, for being sampled to clock signal according to data-signal, to generate the first sampled signal；
Second sample circuit, for being sampled to the clock signal according to postpones signal, to generate the second sampled signal；With And
It is coupled to the control circuit of first sample circuit and second sample circuit, wherein the control circuit is used for According to first sampled signal and second sampled signal executes and non-(NAND) operation, when generating for activating described The activation signal of the frequency adjustment of clock signal.
2. the apparatus according to claim 1, which is characterized in that the postpones signal corresponds to the time of delay a quarter The data-signal of unit, the control circuit include NAND gate, and the control circuit is additionally operable to by the NAND gate The inversion signal and first sampled signal for applying second sampled signal execute the NAND operation, described in generation Activation signal.
3. the apparatus of claim 2, which is characterized in that the data-signal, the postpones signal and the clock Signal is the differential signal for including common mode logic (CML) voltage level；First sample circuit include the first common mode logic extremely CMOS complementary metal-oxide-semiconductor (CML-to-CMOS) converter, for by first sampled signal from the CML voltages Level conversion is to CMOS complementary metal-oxide-semiconductor (CMOS) logical voltage level, to generate the first level shifted signal；Institute It includes the 2nd CML to CMOS converters to state the second sample circuit, is used for second sampled signal from the CML voltage levels It is transformed into the CMOS logic voltage level, to generate second electrical level conversion signal.
4. device according to claim 3, which is characterized in that the control circuit is additionally operable to by the NAND gate Input applies the positive signal component of first level shifted signal and the negative signal components of the second electrical level conversion signal come Execute the NAND operation.
5. device according to claim 3, which is characterized in that the control circuit further includes：
Phase inverter is coupled to the NAND gate and for inverting the activation signal generated by the NAND gate, is born with generating Differential signal component, wherein the phase inverter is associated with delay time；
Buffer is coupled to the NAND gate and is used to the activation signal postponing the delay time, to generate positive differential Signal component；And
It is coupled to the charge pump of the phase inverter and the buffer, wherein the charge pump is used to believe according to from the activation Number generate the positive differential signal component and the negative differential signal component activate the frequency of the clock signal to adjust.
6. device according to claim 5, which is characterized in that the first CML to the CMOS converters, the 2nd CML Include CMOS logic circuit to CMOS converters, the NAND gate, the phase inverter and the buffer.
7. the apparatus according to claim 1, which is characterized in that first sample circuit and the second sample circuit packet Include one or more D flip-flops (DFF).
8. the apparatus according to claim 1, which is characterized in that further include being coupled to first sample circuit and described The third sample circuit of two sample circuits, wherein the third sample circuit is used for according to second sampled signal to described First sampled signal is sampled, and is to increase or reduce the frequency of the clock signal to match the data to generate instruction The frequency error signal of the frequency of signal.
9. the apparatus according to claim 1, which is characterized in that the data-signal and the clock signal are in about 10 lucky ratios It works between spy/second (Gbps) and about 100Gbps.
10. a kind of method, which is characterized in that including：
Clock signal is sampled according to data-signal, to generate the first sampled signal；
The duration that the data-signal is postponed to the chronomere of a quarter, to generate postpones signal；
The clock signal is sampled according to the postpones signal, to generate the second sampled signal；And
According to first sampled signal and second sampled signal executes and non-(NAND) operation, to generate for activating electricity The frequency of the clock signal is snapped to the activation signal of the frequency of the data-signal by lotus pump.
11. according to the method described in claim 10, it is characterized in that, the data-signal and the clock signal are to include altogether The differential signal of mode logic (CML) voltage level, the method further include：
By the first level translator by first sampled signal from the CML voltage level conversions to complementary metal oxide Object semiconductor (CMOS) logical voltage level, to generate the first level shifted signal；And
It is by second electrical level converter that second sampled signal is electric from the CML voltage level conversions to the CMOS logic Voltage level, to generate second electrical level conversion signal.
12. according to the method for claim 11, which is characterized in that the execution NAND operation further includes：
The positive signal component that the first input to non-(NAND) door applies first level shifted signal applies；And
Apply the negative signal components of the second electrical level conversion signal to the second input of the NAND gate.
13. according to the method for claim 11, which is characterized in that further include：In the following manner from the activation signal Middle generation differential signal：
The activation signal is inverted, to generate the negative signal components of the differential signal；And
Postpone the activation signal, to generate the positive signal component of the differential signal.
14. according to the method described in claim 10, it is characterized in that, further including：According to second sampled signal to described First sampled signal is sampled, to generate the frequency error signal of the frequency for correcting the clock signal.
15. a kind of device, which is characterized in that including：
With non-(NAND) door, including the first NAND gate input port, the second NAND gate input port and NAND gate output port；With And
Voltage and current (V2I) converter, including V2I switch actives port and V2I conversion output currents port, wherein
The NAND gate output is coupled in V2I switch actives port, and
It is coupled to frequency detecting loop filter in V2I conversion output currents port.
16. device according to claim 15, which is characterized in that further include：
First D flip-flop (DFF), including the first DFF data-in ports, the first DFF input end of clock mouth and it is coupled to institute State the first DFF output ports of the first NAND gate input port；And
2nd DFF, including the 2nd DFF data-in ports, the 2nd DFF input end of clock mouth and it is coupled to second NAND gate 2nd DFF output ports of input port.
17. device according to claim 16 further includes the 3rd DFF, including is coupled to the first DFF output ports 3rd DFF data input pins, the 3rd DFF input end of clock mouth and the 3rd DFF for being coupled to the 2nd DFF output ports Output port, wherein the V2I converters further include the V2I switching current adjustment ends for being coupled to the 3rd DFF output ports Mouthful.
18. device according to claim 16, which is characterized in that described device further includes：
First common mode logic is to CMOS complementary metal-oxide-semiconductor (CML-to-CMOS) converter, including the first Differential Input Port and the first difference output port containing the first plus end and the first negative terminal；And
2nd CML to CMOS converters, including the second Differential Input port and containing the second plus end and the second negative terminal Two difference output ports, wherein
The first DFF output ports are coupled in first Differential Input port,
The 2nd DFF output ports are coupled in second Differential Input port,
First plus end of first difference output port is coupled to the first NAND gate input port, and
Second negative terminal of second difference output port is coupled to the second NAND gate input port.
19. device according to claim 18, which is characterized in that further include：
Phase inverter, including anti-phase input port and anti-phase output port；And
Buffer, including buffer inputs mouth and buffering output port, wherein
V2I switch actives port is the difference port for including positive actuation terminal and negative activation terminal,
The NAND gate output port is coupled in the anti-phase input port,
The positive actuation terminal is coupled in the anti-phase output port,
The buffer inputs mouth is coupled to the NAND gate output port, and
It is coupled to the negative activation terminal in the Buffer output port.
20. device according to claim 19, which is characterized in that the first CML to the CMOS converters, described second CML to CMOS converters, the NAND gate, the buffer and the phase inverter include p- NMOS N-channel MOS Ns (NMOS) transistor and n- NMOS N-channel MOS Ns (NMOS) transistor.
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US9584303B1 (en) 2017-02-28
CN112953522A (en) 2021-06-11

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