CN104009756B - Clock pulses data restoring circuit module and data recovery clock method for generating pulse - Google Patents
Clock pulses data restoring circuit module and data recovery clock method for generating pulse Download PDFInfo
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- CN104009756B CN104009756B CN201310061480.8A CN201310061480A CN104009756B CN 104009756 B CN104009756 B CN 104009756B CN 201310061480 A CN201310061480 A CN 201310061480A CN 104009756 B CN104009756 B CN 104009756B
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Abstract
The present invention provides a kind of clock pulses data restoring circuit module, including clock pulses data restoring circuit, frequency comparison circuit and signal deteching circuit.Clock pulses data restoring circuit is used to recover crossfire and data recovery clock pulse according to input signal and clock pulse signal come output data.Frequency comparison circuit is coupled to clock pulses data restoring circuit.Frequency comparison circuit is to compare the frequency-splitting between data recovery clock pulse and clock pulse signal, to adjust the frequency of clock pulse signal according to comparative result.Signal deteching circuit is coupled to frequency comparison circuit.Signal deteching circuit decides whether according to testing result initiation culture comparison circuit to receive and detect input signal.In addition, a kind of data recovery clock method for generating pulse is also suggested.
Description
Technical field
The invention relates to a kind of data processing circuit and signal generating method, and in particular to a kind of clock arteries and veins
Rush data recovery circuit module and data recovery clock method for generating pulse.
Background technology
In general, in the signal receiving end of data transmission interface, it will usually configurable clock generator pulse data restoring circuit, its
Received input signal can be recovered according to data recovery clock pulse, and produce (retimed) data of reclocking
Crossfire.In some specific specifications, to ensure the accuracy for the data that clock pulses data restoring circuit is recovered, count again
When the shake (jitter) of data stream crossed can not be excessive.Therefore, in signal receiving end, vibrated used in collocation phaselocked loop
Device is typically crystal oscillator, to meet the requirement of accuracy.The frequency of pulse reference clock produced by this crystal oscillator
Error compared to the frequency of input signal is necessarily less than in the range of some.With third generation USB (Universal
Serial Bus3.0；USB3.0 exemplified by specification), the error between the frequency of pulse reference clock and the frequency of input signal
It is necessarily less than 300ppm (notes：One ppm is equal to hundred a ten thousandths).Although commercial crystal oscillator can produce frequency error and be less than
Positive and negative 100ppm clock pulse signal, and can be as preferable clock pulse signal source, but the price of this crystal oscillator
Costliness, and larger circuit board space can be occupied.
In order to save cost and circuit board space, prior art, which is proposed, utilizes automatic tracing (auto-tracking) number
There is provided phaselocked loop accuracy high pulse reference clock according to the mode of recovered clock pulse frequency.However, such a mode is in USB
Set up communication connection (link) during, or in low-power mode (low power mode) operate when, if still lasting
Data recovery clock pulse is followed the trail of, the accuracy of pulse reference clock frequency will be easily reduced.
The content of the invention
The present invention provides a kind of clock pulses data restoring circuit module, can dynamically decide whether to carry out frequency tracking
(tracking)。
The present invention provides a kind of data recovery clock method for generating pulse, can be decided whether to produce number according to input signal
According to recovered clock pulse.
The present invention provides a kind of clock pulses data restoring circuit module, including a clock pulses data recovery circuit, one
Frequency comparison circuit and a signal deteching circuit.Clock pulses data restoring circuit is used to according to an input signal and a clock
Pulse signal exports a data recovery crossfire and a data recovery clock pulse.Frequency comparison circuit is coupled to clock pulses number
According to restoring circuit.Frequency comparison circuit to compare the frequency-splitting between data recovery clock pulse and clock pulse signal,
To adjust the frequency of clock pulse signal according to a comparative result.Signal deteching circuit is coupled to frequency comparison circuit.Signal
Circuit is detected to receive and detect input signal, and decides whether according to testing result initiation culture comparison circuit.
In an embodiment of the present invention, above-mentioned signal deteching circuit includes a first frequency detection unit and one second
Frequency detecting unit.First frequency detection unit is to receive and detect whether input signal includes the data of a first frequency.
Second frequency detection unit is to receive and detect whether input signal includes the data for being not less than a second frequency.Second frequency
Rate is more than first frequency.
In an embodiment of the present invention, the number not less than second frequency is included when signal deteching circuit detects input signal
According to when, initiation culture comparison circuit.
In an embodiment of the present invention, when signal deteching circuit, which detects input signal, includes the data of first frequency,
Not initiation culture comparison circuit.
In an embodiment of the present invention, above-mentioned input signal includes an electrical idle state.When signal deteching circuit inspection
When measuring input signal and being in electrical idle state, not initiation culture comparison circuit.
In an embodiment of the present invention, above-mentioned clock pulses data restoring circuit include a clock pulses restoring circuit with
And a data recovery circuit.Clock pulses restoring circuit according to input signal and clock pulse signal to produce data recovery
Clock pulses.Data recovery circuit is to produce data recovery crossfire according to input signal.
In an embodiment of the present invention, above-mentioned clock pulses restoring circuit includes a clock pulse generating circuit and one
Frequency generating circuit.Clock pulse generating circuit is coupled to frequency generating circuit.Clock pulse generating circuit is used to according to input
Signal and clock pulse signal produce data recovery clock pulse.Frequency generating circuit is coupled to frequency comparison circuit.Frequency
Generation circuit according to a pulse reference clock to produce clock pulse signal.Frequency comparison circuit is exported according to comparative result
One control signal, to adjust the frequency of the clock pulse signal produced by frequency generating circuit.
In an embodiment of the present invention, above-mentioned frequency generating circuit includes a phase-locked loop circuit and a reference clock arteries and veins
Rush generation circuit.Phase-locked loop circuit is coupled to frequency comparison circuit.Phase-locked loop circuit is controlled by control signal, to according to control
Signal produces clock pulse signal with pulse reference clock.Pulse reference clock generation circuit is coupled to phase-locked loop circuit.Ginseng
Clock pulse generating circuit is examined to produce and export pulse reference clock.
In an embodiment of the present invention, above-mentioned clock pulses data restoring circuit output data recovers crossfire and data are extensive
Clock pulses is answered to a data processing block.Data processing block includes a buffer memory circuit and a decoder circuit.Solution
Code device circuit recovers crossfire to decoding data.Buffer memory circuit is used to data recovery storage crossfire.Frequency comparison circuit
It is coupled to buffer memory circuit.When frequency comparison circuit is activated, buffer memory circuit output data recovers crossfire extremely
Decoder circuit.
In an embodiment of the present invention, above-mentioned clock pulses data restoring circuit module also includes a checking circuit.Test
Card circuit is coupled to decoder circuit, to verify the data recovery crossfire decoded by decoder circuit, and in discovery data
After the error bit of recovery crossfire is more than a threshold value, pause frequency comparison circuit compares data recovery clock pulse and clock arteries and veins
The operation of the frequency-splitting rushed between signal.
The present invention provides a kind of data recovery clock method for generating pulse, comprises the following steps.An input signal is detected, with
Decided whether to compare the frequency-splitting between a data recovery clock pulse and a clock pulse signal according to testing result.Than
Compared with the frequency-splitting between data recovery clock pulse and clock pulse signal.According to data recovery clock pulse and clock pulses
The comparative result of signal adjusts the frequency of clock pulse signal.
In an embodiment of the present invention, above-mentioned data recovery clock method for generating pulse also comprises the following steps.According to
Input signal and clock pulse signal come produce data recovery clock pulse and data recovery crossfire at least one.
In an embodiment of the present invention, the step of above-mentioned detection input signal comprises the following steps.Detect input signal
Whether the data of a first frequency are included.Detect whether input signal includes the data for being not less than a second frequency.Second frequency
Rate is more than first frequency.
In an embodiment of the present invention, when detecting data of the input signal including being not less than second frequency, ratio is performed
The step of compared with frequency-splitting between data recovery clock pulse and clock pulse signal.
In an embodiment of the present invention, when detecting data of the input signal including first frequency, do not perform and relatively count
The step of according to frequency-splitting between recovered clock pulse and clock pulse signal.
In an embodiment of the present invention, above-mentioned input signal includes an electrical idle state.Detect the step of input signal
It is rapid to include whether detection input signal is in electrical idle state.When detecting input signal in electrical idle state, no
The step of frequency-splitting between data recovery crossfire and clock pulse signal is compared in execution.
In an embodiment of the present invention, above-mentioned data recovery clock method for generating pulse also includes according to a reference clock
Pulse produces clock pulse signal.The step of adjusting the frequency of clock pulse signal includes being controlled according to comparative result output one
Signal, to adjust the frequency of clock pulse signal.
In an embodiment of the present invention, above-mentioned data recovery clock method for generating pulse also comprises the following steps.Decoding
Data recovery crossfire.Checking by decoding data recovery crossfire, and in data recovery crossfire error bit number more than one
After threshold value, the frequency-splitting between data recovery clock pulse and clock pulse signal is compared in pause.
Based on above-mentioned, in the exemplary embodiment of the present invention, signal deteching circuit meeting is according to whether detect input signal
Echo signal do not start or initiation culture comparison circuit, therefore can dynamically decide whether to carry out the operation of frequency tracking.
For the features described above and advantage of the present invention can be become apparent, special embodiment below, and it is detailed to coordinate accompanying drawing to make
Carefully it is described as follows.
Brief description of the drawings
Figure 1A shows the schematic block diagram of the clock pulses data restoring circuit module of an exemplary embodiment of the invention；
Figure 1B shows the schematic block diagram of the signal receiving end of the memory storage apparatus of an exemplary embodiment of the invention；
The summary oscillogram of the input signal of different exemplary embodiments of the invention is shown respectively in Fig. 2 and Fig. 3；
Fig. 4 shows the schematic block diagram of the signal receiving end of the memory storage apparatus of another exemplary embodiment of the invention；
Fig. 5 shows the outline flowchart of the data recovery clock method for generating pulse of an exemplary embodiment of the invention；
Fig. 6 shows the outline flowchart of the data recovery clock method for generating pulse of another exemplary embodiment of the invention.
Description of reference numerals：
10：Data receiver block；
20：Data processing block；
22：Transformation from serial to parallel circuit；
24：Buffer memory circuit；
26：Decoder circuit；
100、400：Clock pulses data restoring circuit module；
110、410：Clock pulses data restoring circuit；
112、412：Clock pulses restoring circuit；
118、418：Data recovery circuit；
120、420：Frequency comparison circuit；
130、430：Signal deteching circuit；
132：First frequency detection unit；
134：Second frequency detection unit；
140：Verify circuit；
413：Phase-locked loop circuit；
414：Frequency generating circuit；
415：Pulse reference clock generation circuit；
416：Clock pulse generating circuit；
CLK：Clock pulse signal；
CLK_REF：Pulse reference clock；
CDR_CLK：Data recovery clock pulse；
CDR_DATA：Data recovery crossfire；
LFPS：Low frequency cycle signal；
DATA：Data-signal；
IN_DATA：Input signal；
EN：Switching signal；
CTRL：Control signal；
S500、S510、S520、S530、S600、S610、S620、S630、S640、S650、S660：Method and step.
Embodiment
Multiple embodiments set forth below illustrate the present invention, but the present invention is not limited only to illustrated multiple embodiments.
And appropriate combination is also still allowed between embodiment." coupling " used in this case specification in full (including claim)
One word can refer to any direct or indirect connection means.For example, if first device is coupled to second device described in text,
The first device should be construed as and can be directly connected to the second device, or the first device can pass through other devices
Or certain connection means and be coupled indirectly to the second device.In addition, " signal " one word can refer at least an electric current, voltage, electricity
Lotus, temperature, data or any other one or more signal.
It refer to Figure 1A and 1B, Figure 1A show the clock pulses data restoring circuit module of an exemplary embodiment of the invention
Schematic block diagram, Figure 1B shows the summary square of the signal receiving end of the memory storage apparatus of an exemplary embodiment of the invention
Figure.The circuit framework of the signal receiving end of this exemplary embodiment includes data receiver block 10 and data processing block 20.One
As for, when memory storage apparatus by data transmission interface receives the input transmitted from host computer system or other elements
During signal IN_DATA, it will usually first carry out data syn-chronization to the input signal IN_DATA inputted using data receiver block 10
Processing, its purpose primarily to the data-signal for being carried input signal IN_DATA can be with signal receiving end operation
Clock pulses is synchronous, to avoid the data processing block 20 of rear end from producing mistake in processing data.
In this exemplary embodiment, data receiver block 10 includes clock pulses data restoring circuit module 100, to make
Data-signal and the operating clock impulsive synchronization of signal receiving end that input signal IN_DATA is carried.This exemplary embodiment
Clock pulses data restoring circuit module 100 includes clock pulses data restoring circuit 110, frequency comparison circuit 120 and letter
Number detection circuit 130, as shown in Figure 1A.Figure 1B is further disclosed and applied in data receiver block 10, and clock pulses data are extensive
The detailed embodiment of each circuit blocks in the inside of compound circuit module 100.Specifically, clock pulses data restoring circuit 110 is used
It is extensive to produce data recovery crossfire CDR_DATA and data with the clock pulse signal according to input signal IN_DATA and its inside
Multiple clock pulses CDR_CLK, is exported to data processing block 20 and frequency comparison circuit 120 respectively.In this instance, clock arteries and veins
Rushing data recovery circuit 110 includes clock pulses data circuit 112 and data recovery circuit 118.Clock pulses data circuit 112
The operation of clock pulses recovery (clock recovery) can be carried out to input signal IN_DATA, so that data recovery crossfire
CDR_DATA and data recovery clock pulse CDR_CLK operations are in more correct frequency.
Frequency comparison circuit 120 is coupled to clock pulses data restoring circuit 110.Frequency comparison circuit 120 is to compare
The frequency-splitting between clock pulse signal inside data recovery crossfire CDR_DATA and clock pulses restoring circuit 112, with
The frequency of clock pulse signal is adjusted according to comparative result.In this instance, clock pulse signal is, for example, extensive by clock pulses
Produced by phaselocked loop (phase lock loop, PLL) circuit blocks inside compound circuit 112, and frequency comparison circuit 120 can
PLL circuit block is controlled using control signal CTRL, to adjust the frequency of the clock pulse signal produced by it.In another model
In example embodiment, the PLL circuit block inside clock pulses restoring circuit 112 can also be independently of the recovery of clock pulses data
One circuit module of circuit 110.
Signal deteching circuit 130 is coupled to frequency comparison circuit 120.Signal deteching circuit 130 is to detect input signal
IN_DATA, and decide whether that initiation culture comparison circuit 120 is entered with the frequency to clock pulse signal according to testing result
Row adjustment.In this instance, signal deteching circuit 130 is using switching signal EN is come forbidden energy or enables frequency comparison circuit 120.
In this exemplary embodiment, input signal IN_DATA for example mainly may include the data of first frequency, not less than
The data of two frequencies and electrical idle state.The data not less than second frequency are as frequency in this exemplary embodiment
The target that comparison circuit 120 is followed the trail of.Therefore, when signal deteching circuit 130 detects the echo signal in input signal IN_DATA
When, can initiation culture comparison circuit 120 so that its output control signal CTRL adjusts the frequency of clock pulse signal.Relatively
, when signal deteching circuit 130 detect be first frequency in input signal IN_DATA data, or input signal IN_
DATA be in electrical idle state when, will not initiation culture comparison circuit 120, to avoid the first of input signal IN_DATA
The target that the data of frequency and input signal IN_DATA in electrical idle state are followed the trail of as frequency comparison circuit 120.
Wherein, in this exemplary embodiment, this first frequency is a frequency for being less than second frequency.
In this exemplary embodiment, signal deteching circuit 130 includes first frequency detection unit 132 and second frequency is detected
Unit 134, is coupled to each other, respectively to receive and detect whether input signal IN_DATA includes the data and not of first frequency
Less than the data of second frequency.In this instance, the data of first frequency are, for example, input signal IN_DATA low frequency cycle letter
Number LFPS (low frequency period signal), first frequency detection unit 132 can be the squelch detection electricity of low frequency
Road (squelch detector).Second frequency composition such as input signal IN_DATA data content, it is as entering line frequency
Echo signal during tracking, its frequency is generally 5 gigahertz (GHZ)s (Gigahertz, GHz).Therefore, in this exemplary embodiment, second
Frequency is more than first frequency.Second frequency detection unit 134 can be high speed squelch detecting circuit, to detect input signal
Whether IN_DATA includes the data not less than second frequency.
On the other hand, input signal IN_DATA, data recovery crossfire CDR_DATA and data recovery clock arteries and veins are being received
Rush after CDR_CLK, data recovery circuit 118 can be according to CDR_CLK pairs of input signal IN_DATA and data recovery clock pulse
Data recovery crossfire CDR_DATA carries out the operation of data recovery (data recovery), and by the data recovery string after processing
Stream CDR_DATA is transmitted to transformation from serial to parallel circuit 22.Then, transformation from serial to parallel circuit 22 is extensive by the data for changing into parallel form
Multiple crossfire CDR_DATA, which is exported to buffer memory circuit 24, to be stored.Afterwards, data recovery crossfire CDR_DATA is exported to solution again
Code device circuit 26 is decoded.
In another exemplary embodiment, frequency comparison circuit 120 also can control the accessing operation of buffer memory circuit 24.
For example, to can control buffer memory circuit 24 more electric in the initiation culture of signal deteching circuit 130 for frequency comparison circuit 120
Ability output data is recovered crossfire CDR_DATA and decoded to decoder circuit 26 behind road 120.
In this exemplary embodiment, the standard of the coffret of the input/output interface of the memory storage apparatus is used as
Including Serial Advanced Technology Attachment (Serial Advanced Technology Attachment, SATA) standard, electric and electricity
1394 standards of sub- IEEE (Institute of Electrical and Electronic Engineers, IEEE),
High-speed peripheral interconnection (Peripheral Component Interconnect Express, PCI Express) standard, general
Universal serial bus (Universal Serial Bus, USB) standard, safe digital (Secure Digital, SD) interface standard, note
Recall rod (Memory Stick, MS) interface standard, it is multimedia storage card (Multi Media Card, MMC) interface standard, small-sized
Quick flashing (Compact Flash, CF) interface standard, integrated form driving electrical interface (Integrated Device
Electronics, IDE) standard or other suitable standards.
The summary oscillogram of the input signal of different exemplary embodiments of the invention is shown respectively in Fig. 2 and Fig. 3.It refer to Fig. 2
And Fig. 3, in this exemplary embodiment, by taking USB3.0 standards as an example, input signal IN_DATA generally includes low frequency cycle signal
LFPS (low frequency period signal), data-signal DATA and electrical idle state.Low frequency cycle signal
LFPS is, for example, the data with first frequency in input signal IN_DATA, and it can be distributed in continuous or discrete mode
In input signal IN_DATA, respectively as shown in Figures 2 and 3.Low frequency cycle signal LFPS is low frequency signal, and its cycle is about
Between 20 nanoseconds (nanosecond, ns) between 100ns.In this exemplary embodiment, data-signal DATA is, for example, input
There are the data of second frequency, frequency comparison circuit 120 is to be chased after with data-signal DATA as line frequency is entered in signal IN_DATA
Echo signal during track, its frequency is generally 5 gigahertz (GHZ)s (Gigahertz, GHz).Therefore, when the memory storage apparatus is logical
During letter establishment of connection, or during in low-power mode, input signal IN_DATA can include low frequency cycle signal
LFPS and electrical idle state.The signal deteching circuit 130 of this exemplary embodiment can detect input signal IN_DATA low frequency
Periodic signal LFPS and electrical idle state, and using switching signal EN come temporary transient not initiation culture comparison circuit 120, to tie up
Hold the accuracy of frequency tracking.
In this instance, when switching signal EN is high level, to initiation culture comparison circuit 120, conversely, switching signal EN
During for low level, to not initiation culture comparison circuit 120, the present invention is not any limitation as, low in another exemplary embodiment
The switching signal EN of level also can be used to initiation culture comparison circuit 120, and the switching signal EN of high level also can be used to not start
Frequency comparison circuit 120.In addition, in this exemplary embodiment, when frequency comparison circuit 120 is activated, signal deteching circuit
130 can be closed, to temporarily cease running.
In addition, in this exemplary embodiment, clock pulses data restoring circuit module 100 also includes checking circuit 140.Test
Card circuit 140 also can be used to suspend the running of frequency comparison circuit 120.Specifically, if the number that decoder circuit 26 is decoded
After inspection according to empirical tests circuit 140, checking circuit 140 finds decoded data recovery crossfire CDR_DATA error bit
During more than a threshold value, it now can be considered data recovery crossfire CDR_DATA by a noise jamming.Therefore, it is original in order to prevent
The stable frequency drift of gained after tracking, now verifies that circuit 140 can also suspend frequency comparison circuit 120, remains former with this
Some clock pulse signals.
In addition, in an exemplary embodiment of the invention, clock pulses data restoring circuit module 100 can be applicable to wired company
Connect in communication system (wire-linked communication system), and input signal IN_DATA can be serial
(serial) data stream, clock pulses data restoring circuit module 100 can receive input signal IN_ by single channel
DATA.But the present invention is not limited, in another exemplary embodiment, clock pulses data restoring circuit module 100 can also be answered
Used in a wireless communication system, and input signal IN_DATA is alternatively parallel data crossfire.
Fig. 4 is refer to, Fig. 4 shows the general of the signal receiving end of the memory storage apparatus of another exemplary embodiment of the invention
Block diagram is wanted, it further discloses the inside structure of clock pulses restoring circuit 412.In this exemplary embodiment, clock pulses
Restoring circuit 412 includes clock pulse generating circuit 416 and frequency generating circuit 414.Frequency generating circuit 414 includes lock phase
Loop circuit 413 and pulse reference clock generation circuit 415.Wherein, in this exemplary embodiment, pulse reference clock produces electricity
Road 415 can for Hartley oscillator (Hartley Oscillator), Colpitts oscillator (Colpitts Oscillator),
Clapp oscillator (Clapp Oscillator) oscillator, phaseshift oscillator, RC oscillator (RC
Oscillator), LC oscillator (LC Oscillator) or other be quartz (controlled) oscillator oscillator.With reference to when
Clock generation circuit 415 is coupled to phase-locked loop circuit 413.Pulse reference clock generation circuit 415 is to produce and export ginseng
Clock pulses CLK_REF is examined to phase-locked loop circuit 413.Wherein, in this exemplary embodiment, because pulse reference clock produces electricity
Road 415 is an oscillator for not having quartz (controlled) oscillator, therefore its clock pulse signal CLK provided is more inaccurate, utilization of still needing
Clock pulse generating circuit 416 is by the data recovery clock pulse CDR_CLK obtained in input signal IN_DATA via frequency
Comparison circuit 420 is corrected to it, then can the voluntarily more accurate clock pulse signal CLK of output.Even if in this way, clock arteries and veins
Rush restoring circuit 412 and do not receive an input signal IN_DATA with data-signal DATA, also can the accurate clock pulses of output
Signal CLK.Phase-locked loop circuit 413 is coupled to frequency comparison circuit 420.Phase-locked loop circuit 413 is controlled by control signal CTRL use
To produce clock pulse signal CLK according to pulse reference clock CLK_REF to clock pulse generating circuit 416.Clock pulses
Generation circuit 416 is coupled to frequency generating circuit 414.Clock pulse generating circuit 416 be used to according to clock pulse signal CLK come
The operation of clock pulses recovery is carried out to input signal IN_DATA, to produce data recovery clock pulse CDR_CLK.In this example
In, in order that frequency comparison circuit 420 can carry out the operation of automatic frequency tracking, clock pulse generating circuit 416 can be by data
Recovered clock pulse CDR_CLK is exported to frequency comparison circuit 420, is used as the reference compared.
Therefore, in one example of the present invention embodiment, data receiver block 10 receives input signal IN_DATA, signal
Detect whether the detection input signal of circuit 430 IN_DATA includes echo signal, for example whether the number including not less than second frequency
It is believed that number DATA.If so, the initiation culture comparison circuit 420 of signal deteching circuit 430 enters the operation of line frequency automatic tracing.It is another
Aspect, when input signal IN_DATA is inputted, data-signal DATA can be transferred to respectively clock pulses restoring circuit 412 and
Data recovery circuit 418, to produce data recovery clock pulse CDR_CLK and data recovery crossfire CDR_DATA.In addition, at this
In exposure, the clock pulse signal of phase-locked loop circuit 413 is, for example, to be produced using RC oscillator (RC oscillator)
It is raw.Clock pulses data restoring circuit module 400 utilizes data recovery clock pulse CDR_CLK by frequency comparison circuit 420
Frequency correct the clock pulse signal CLK of phase-locked loop circuit 413.Its correcting mode is included in adjustment phase-locked loop circuit 413
The frequency multiplier multiple in portion or the frequency of oscillation of frequency generating circuit 414, so that phase-locked loop circuit 413 produces one accurately
Clock pulse signal CLK.When data receiver block 10 is not received by data-signal DATA, clock pulses data restoring circuit
The signal that this accurate clock pulse signal CLK is used as synchronizing frequency can also be used in module 400.
Fig. 5 shows the outline flowchart of the data recovery clock method for generating pulse of an exemplary embodiment of the invention.It please join
Figure 1B and Fig. 5 is examined, in this exemplary embodiment, in step S500, the detection input signal IN_DATA of signal deteching circuit 130,
To be decided whether to compare the frequency between data recovery clock pulse CDR_CLK and clock pulse signal CLK according to testing result
Rate difference.Then, in step S510, frequency comparison circuit 120 compares data recovery clock pulse CDR_CLK and clock pulses
Frequency-splitting between signal CLK.Afterwards, in step S520, frequency comparison circuit 120 is according to data recovery clock pulse
CDR_CLK and clock pulse signal CLK comparative result adjust clock pulse signal CLK frequency.Again, in step S530
In, clock pulses data restoring circuit 110 produces data recovery according to input signal IN_DATA and clock pulse signal CLK
Both clock pulses CDR_CLK and data recovery crossfire CDR_DATA at least one.
Fig. 6 shows the outline flowchart of the data recovery clock method for generating pulse of another exemplary embodiment of the invention.Please
With reference to Figure 1B and Fig. 6, in this exemplary embodiment, in step S600, signal deteching circuit 130 first detects whether to have received
To input signal IN_DATA echo signal.In this instance, input signal IN_DATA echo signal is, for example, that frequency is higher
Second frequency composition, i.e. Fig. 2 or Fig. 3 data-signal DATA.If detecting this echo signal, in step S610, signal
The meeting initiation culture of circuit 130 comparison circuit 120 is detected, so that frequency comparison circuit 120 compares data recovery clock pulse CDR_
Frequency-splitting between CLK and clock pulse signal CLK, carries out frequency tracking function, as shown in step S620, so that in step
In S630, frequency comparison circuit 120 can adjust clock pulse signal CLK frequency according to comparative result.Then, in step
In S660, clock pulses data restoring circuit 110 can be according to input signal IN_DATA and adjusted clock pulse signal CLK
Come produce both data recovery crossfire CDR_DATA and data recovery clock pulse CDR_CLK at least one.In this step
In, the clock pulse signal CLK before adjusted clock pulse signal CLK is more originally adjusted believes for more accurately clock pulses
Number.
In addition, in another exemplary embodiment, if the inspection for the data empirical tests circuit 140 that decoder circuit 26 is decoded
Afterwards, when checking circuit 140 finds decoded data recovery crossfire CDR_DATA error bit more than a threshold value, now may be used
It is considered as data recovery crossfire CDR_DATA by a noise jamming.Therefore, in order to prevent the stable frequency of gained after original follow the trail of
Drift, now verifies that circuit 140 can also suspend frequency comparison circuit 120, and original clock pulse signal is maintained with this.
On the other hand, in step S600, if signal deteching circuit 130 does not detect input signal IN_DATA target
During signal, for example, non-targeted signal or electrical idle state are detected, in step S640, signal deteching circuit 130 will not be opened
Dynamic frequency comparison circuit 120, so that frequency comparison circuit 120 is stopped, without frequency tracking, as shown in step S650.
In addition, the data recovery clock method for generating pulse for the exemplary embodiment that above-mentioned Fig. 5 and Fig. 6 is disclosed can be by Figure 1A
Enough teachings, suggestion is obtained into the narration of Fig. 4 embodiments with implementing to illustrate, therefore repeat no more.
In summary, in the exemplary embodiment of the present invention, the target in input signal is detected when signal deteching circuit
During signal, meeting initiation culture comparison circuit, to enter the function of line frequency automatic tracing.Conversely, when signal deteching circuit is detected
During non-targeted signal, not initiation culture comparison circuit is understood temporarily, to maintain the accuracy of frequency tracking.
Finally it should be noted that：Various embodiments above is merely illustrative of the technical solution of the present invention, rather than its limitations；To the greatest extent
The present invention is described in detail with reference to foregoing embodiments for pipe, it will be understood by those within the art that：Its according to
The technical scheme described in foregoing embodiments can so be modified, or which part or all technical characteristic are entered
Row equivalent substitution；And these modifications or replacement, the essence of appropriate technical solution is departed from various embodiments of the present invention technology
The scope of scheme.
Claims (16)
1. a kind of clock pulses data restoring circuit module, it is characterised in that including：
One clock pulses data recovery circuit, to export a data recovery according to an input signal and a clock pulse signal
Crossfire and a data recovery clock pulse；
One frequency comparison circuit, is coupled to the clock pulses data restoring circuit, to compare the data recovery clock pulse and
Frequency-splitting between the clock pulse signal, to adjust the frequency of the clock pulse signal according to a comparative result；And
One signal deteching circuit, is coupled to the frequency comparison circuit, to receive and detect the input signal, and according to an inspection
Result is surveyed to decide whether to start the frequency comparison circuit,
Wherein the signal deteching circuit includes：
One first frequency detection unit, to receive and detect whether the input signal includes the data of a first frequency；And
One second frequency detection unit, to receive and detect whether the input signal includes a number for being not less than a second frequency
According to,
Wherein the second frequency is more than the first frequency.
2. clock pulses data restoring circuit module according to claim 1, it is characterised in that when the signal deteching circuit
Detect the input signal including this be not less than the second frequency data when, start the frequency comparison circuit.
3. clock pulses data restoring circuit module according to claim 1, it is characterised in that when the signal deteching circuit
When detecting data of the input signal including the first frequency, the frequency comparison circuit is not started.
4. clock pulses data restoring circuit module according to claim 1, it is characterised in that when the signal deteching circuit
When judging the input signal for an electrical idle status signal, the frequency comparison circuit is not started.
5. clock pulses data restoring circuit module according to claim 1, it is characterised in that the clock pulses data are extensive
Compound circuit includes：
One clock pulses restoring circuit, to produce the data recovery clock according to the input signal and the clock pulse signal
Pulse；And
One data recovery circuit, to produce the data recovery crossfire according to the input signal.
6. clock pulses data restoring circuit module according to claim 5, it is characterised in that the clock pulses recovers electricity
Road includes：
One clock pulse generating circuit, to produce the data recovery clock according to the input signal and the clock pulse signal
Pulse；And
One frequency generating circuit, is coupled to the clock pulse generating circuit and the frequency comparison circuit, during being referred to according to one
Clock produces the clock pulse signal,
Wherein the frequency comparison circuit exports a control signal according to the comparative result, with produced by adjusting the frequency generating circuit
The clock pulse signal frequency.
7. clock pulses data restoring circuit module according to claim 6, it is characterised in that the frequency generating circuit bag
Include：
One phase-locked loop circuit, is coupled to the frequency comparison circuit, is controlled by the control signal, to according to the control signal and this
Pulse reference clock produces the clock pulse signal；And
One pulse reference clock generation circuit, is coupled to the phase-locked loop circuit, to produce and export the pulse reference clock.
8. clock pulses data restoring circuit module according to claim 1, it is characterised in that the clock pulses data are extensive
Compound circuit exports the data recovery crossfire and the data recovery clock pulse to a data processing block, the data processing block bag
A buffer memory circuit and a decoder circuit are included, the wherein decoder circuit is to decode the data recovery crossfire, and this delays
Memory circuitry is rushed to store the data recovery crossfire, the frequency comparison circuit is coupled to the buffer memory circuit, when this
When frequency comparison circuit is activated, the buffer memory circuit exports the data recovery crossfire to the decoder circuit.
9. clock pulses data restoring circuit module according to claim 8, it is characterised in that also include：
One checking circuit, is coupled to the decoder circuit, to verify the data recovery string decoded by the decoder circuit
Stream, and in find the data recovery crossfire error bit more than a threshold value after, suspend the frequency comparison circuit and compare the number
According to the operation of the frequency-splitting between recovered clock pulse and the clock pulse signal.
10. a kind of data recovery clock method for generating pulse, it is characterised in that including：
An input signal is detected, to decide whether to compare a data recovery clock pulse and a clock arteries and veins according to a testing result
The frequency-splitting rushed between signal；
Compare the frequency-splitting between the data recovery clock pulse and the clock pulse signal；And
The frequency of the clock pulse signal is adjusted according to the comparative result of the data recovery clock pulse and the clock pulse signal
Rate,
The step of wherein detecting the input signal includes：
Detect whether the input signal includes the data of a first frequency；And
Detect whether the input signal includes the data for being not less than a second frequency,
Wherein the second frequency is more than the first frequency.
11. data recovery clock method for generating pulse according to claim 10, it is characterised in that also include：
The data recovery clock pulse and a data recovery crossfire are produced according to the input signal and the clock pulse signal extremely
It is one of few.
12. data recovery clock method for generating pulse according to claim 10, it is characterised in that when detecting the input
When signal includes the data that this is not less than the second frequency, the data recovery clock pulse and the clock pulse signal are compared in execution
Between frequency-splitting the step of.
13. data recovery clock method for generating pulse according to claim 10, it is characterised in that when detecting the input
When signal includes the data of the first frequency, do not perform and compare between the data recovery clock pulse and the clock pulse signal
The step of frequency-splitting.
14. data recovery clock method for generating pulse according to claim 10, it is characterised in that the input signal includes
One electrical idle state, the step of detecting the input signal includes：
Detect whether the input signal is in the electrical idle state,
Wherein when detect the input signal be in the electrical idle state when, do not perform compare the data recovery clock pulse and
The step of frequency-splitting between the clock pulse signal.
15. data recovery clock method for generating pulse according to claim 10, it is characterised in that also include：
The clock pulse signal is produced according to a pulse reference clock,
The step of frequency for wherein adjusting the clock pulse signal, includes：
One control signal is exported according to the comparative result, to adjust the frequency of the clock pulse signal.
16. data recovery clock method for generating pulse according to claim 11, it is characterised in that also include：
Decode the data recovery crossfire；And
Checking by decoding the data recovery crossfire, and in the data recovery crossfire error bit number more than a threshold value
Afterwards, the frequency-splitting between the data recovery clock pulse and the clock pulse signal is compared in pause.
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| CN113078978A (en) * | 2021-03-26 | 2021-07-06 | 杭州加速科技有限公司 | Synchronization method, system and test method for remote multi-ATE semiconductor test equipment |
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