JP2010021950A - Asynchronous interface circuit and method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an asynchronous interface circuit which enables verifiable data transmission and reception between transmitting- and receiving-side blocks, without increasing STA verification and test pattern creation. <P>SOLUTION: In the asynchronous interface circuit interposed in between the transmitting- and receiving-side blocks having respective master clock signals, one block of the transmitting- and receiving-side blocks receives the master clock signal of the other block. When the count value, based on the master clock signal of one-side block which is obtained from the leading or the trailing edge of the received master clock signal agrees with a predetermined value, a block-generating circuit which masks the master clock signal of the one-side block and feeds it to the one-side block is provided. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to an asynchronous interface circuit, and more particularly to an asynchronous interface circuit between a transmission side block and a reception side block that operate as independent synchronization circuits.

  In the development of a semiconductor device such as LSI (Large Scale Integration), when the transmission side block and the reception side block operate with independent clock signals, and data is transferred asynchronously from the transmission side block to the reception side block. For example, a technique of designing using an asynchronous interface circuit as shown in FIG. 5 is known.

First, the circuit configurations of the transmission side block and the reception side block are designed as shown in the following (A1) to (A4).
(A1) One enable signal line is provided between the transmission side block and the reception side block.
(A2) The transmission side block uses the flip-flop circuit 2010 and the flip-flop circuit 2011 to transmit transmission data and transmit an enable signal based on the transmission side clock.
(A3) In the reception side block, the enable signal received from the transmission side block via the enable signal line is converted into a two-stage flip-flop circuit of a flip-flop circuit 1010 and a flip-flop circuit 1011 based on the reception side clock. Receive in two steps. This is a metastable measure.
(A4) In the transmission side block, transmission data is fetched by the flip-flop circuit 1012 (FF1012) based on the enable signal received after two steps.

FIG. 6 is a sequence diagram of the asynchronous interface circuit of FIG. As a technique related to such an asynchronous interface circuit, for example, a technique according to Patent Document 1 is known.
JP 2002-215568 A

  However, the asynchronous interface circuit shown in Patent Document 1 has the following problems. After designing the circuit configuration of the transmission side block and the reception side block, the designer needs to perform verification as shown in the following (B1) to (B2).

(B1) In the layout and the STA (Static Timing Analysis) verification, the flip-flop circuit 1012 reliably sets the setup time and hold time conditions in relation to the transmission data to be captured and the enable signal received in two stages. It is necessary to verify that it is satisfied.
(B2) Further, at the time of designing, it is necessary to perform the above detailed design for each asynchronous interface.

  Here, when the transmission side block and the reception side block operate with the clock signals synchronized with each other, and the data transmitted from the transmission side block is synchronously transferred to the reception side block, the design as described above is performed. Care is not required. However, if there are many places that become asynchronous interfaces, there is a problem that the number of man-hours for care as described above increases.

  Also, in creating a test pattern for a shipping test, there is a possibility that the data transmission / reception timing is shifted by one cycle between the maximum delay time and the minimum delay time. Therefore, in particular, when there are a plurality of asynchronous interface locations, there is a problem that the number of steps for creating a test pattern increases. In addition, the clock path in the terminal flip-flop circuit has a large delay, and it may be necessary to match the skew in the clock tree. In the test pattern, it is necessary to create a test pattern for adjusting the skew with such a clock tree, and there is a problem that the number of man-hours increases.

  The present invention has been made in view of such circumstances, and its purpose is to enable verification without increasing STA verification and test pattern creation, between a transmission side block and a reception side block. An asynchronous interface circuit capable of transmitting and receiving data and an asynchronous interface method are provided.

  The present invention has been made to solve the above-described problems, and the invention according to claim 1 is an asynchronous interface circuit between a transmission side block and a reception side block each having a master clock signal, One of the transmission side block and the reception side block receives the master clock signal of the other block, and from the rising or falling edge of the received master clock signal, based on the master clock signal of the one block A clock generation circuit that masks a master clock signal of the one block and supplies the master clock signal to the one block when the counted value matches a predetermined value; Asynchronous interface circuit.

  According to a second aspect of the present invention, when the one block is a receiving block, the transmitting block transmits transmission data in synchronization with a master clock signal of the transmitting block and the transmission The clock generation circuit operates in synchronization with the master clock signal of the side block, and the reception side block receives transmission data from the transmission side block in synchronization with the master clock signal masked by the clock generation circuit. The asynchronous interface circuit according to claim 1, wherein the asynchronous interface circuit operates in synchronization with a masked master clock signal.

  In the invention according to claim 3, when the one block is a transmission side block, the transmission side block transmits transmission data in synchronization with a master clock signal masked by the clock generation circuit, The clock generation circuit operates in synchronization with the masked master clock signal, and the reception side block receives transmission data from the transmission side block in synchronization with the master clock signal of the reception side block, and the reception 2. The asynchronous interface circuit according to claim 1, wherein the asynchronous interface circuit operates in synchronization with a master clock signal of a side block.

  According to a fourth aspect of the present invention, the clock generation circuit receives the master clock signal of the other block, detects a rising edge of the received master clock signal, and the rising detection circuit detects the rising edge of the received master clock signal. A mask signal output circuit that counts based on the rising edge based on the master clock signal of the one block and outputs a mask signal when the counted value matches a predetermined value, and the mask signal generation 4. A mask circuit that masks a master clock signal of the one block and supplies the master clock signal to the one block based on a mask signal output from the circuit. The asynchronous interface circuit according to any one of the above.

  According to a fifth aspect of the present invention, the clock generation circuit receives the master clock signal of the other block, and generates a signal that is phase-synchronized with the received master clock signal as a phase synchronization signal; When counting is performed based on the master clock signal of the one block according to the period of the phase synchronization signal generated by the phase synchronization circuit being at a high level, and the counted value matches a predetermined value A mask signal output circuit that outputs a mask signal; and a mask circuit that masks the master clock signal of the one block and supplies the mask signal to the one block based on the mask signal output from the mask signal generation circuit. The asynchronous interface circuit according to claim 1, wherein the asynchronous interface circuit is provided.

  The invention according to claim 6 is an asynchronous interface method used in an asynchronous interface circuit between a transmission-side block and a reception-side block each having a master clock signal, wherein the transmission-side block and the reception-side block are One block receives the master clock signal of the other block, and the value counted based on the master clock signal of the one block from the rising or falling edge of the received master clock signal is predetermined. In the asynchronous interface method, the master clock signal of the one block is masked and supplied to the one block when the values match.

  According to the present invention, in the asynchronous interface circuit between the transmission side block and the reception side block each having a master clock signal, one of the transmission side block and the reception side block is the master clock signal of the other block. When the value counted based on the master clock signal of one block from the rising or falling edge of the received master clock signal matches the predetermined value, the master clock of one block The signal is masked and supplied to one block.

  Therefore, according to this asynchronous interface circuit, the reception side block does not capture the transmission data from the transmission side block at the timing at which the metastable is generated or at the timing at which the setup time and the hold time are not satisfied. . Alternatively, the transmission side block does not transmit the transmission data to the reception side block at the timing at which the metastable is generated on the reception side or the timing at which the setup time and hold time are not satisfied.

  Therefore, transmission of transmission data is performed between the transmission side block and the reception side block having the respective master clock signals so that the metastable is not generated and the setup time and hold time are satisfied. Can receive. Further, the transmission side block and the reception side block operate as a synchronization circuit in synchronization with each master clock signal. Therefore, each block can be verified as a synchronous circuit. Therefore, STA verification and test pattern creation can be verified without increasing.

<First Embodiment>
Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a schematic block diagram showing a configuration of an asynchronous interface circuit 1 according to the first embodiment of the present invention. The asynchronous interface circuit 1 is a circuit used for an asynchronous interface between a transmission side block and a reception side block. Each of the transmission side block and the reception side block has a master clock signal. Here, a case where the receiving side block has the asynchronous interface circuit 1 will be described. In the following description, it is assumed that the master clock signal used for the synchronization processing in the reception side block is faster than the master clock signal used for the synchronization processing in the transmission side block.

  The asynchronous interface circuit 1 receives the master clock signal of the transmission side block, and a value counted based on the master clock signal of the reception side block from the rising or falling edge of the received master clock signal is determined in advance. A clock generation circuit 2 that masks the master clock signal of the receiving side block and supplies it to the receiving side block when it matches the value.

  The clock generation circuit 2 includes a rising edge detection circuit 10, a mask signal output circuit 20, and a mask circuit 30. The rising edge detection circuit 10 receives the master clock signal of the transmission side block and detects the rising edge of the received master clock signal. The mask signal output circuit 20 counts based on the rising edge detected by the rising edge detection circuit 10 based on the master clock signal of the receiving side block, and when the counted value matches a predetermined value, the mask signal Is output. The mask circuit 30 masks the master clock signal of the receiving block based on the mask signal output from the mask signal output circuit 20 and supplies the mask to the receiving block.

  The transmission side block transmits transmission data in synchronization with the master clock signal of the transmission side block and operates in synchronization with the master clock signal of the transmission side block. For example, in the transmission side block, a pre-stage circuit that generates transmission data operates in synchronization with the master clock signal of the transmission side block. The transmission circuit transmits the transmission data generated by the preceding circuit in synchronization with the master clock signal of the transmission side block.

  The reception side block receives transmission data from the transmission side block in synchronization with the master clock signal masked by the clock generation circuit 2, and operates in synchronization with the master clock signal masked by the clock generation circuit 2. For example, in the reception side block, the reception circuit receives transmission data from the transmission side block in synchronization with the master clock signal masked by the clock generation circuit 2. Further, the subsequent circuit executes operations such as signal processing on the transmission data received by the receiving circuit in synchronization with the master clock signal masked by the clock generation circuit 2.

  Next, details of each component will be described. The rising edge detection circuit 10 includes a plurality of flip-flop circuits 100 and a reset signal output circuit 200. The multi-stage flip-flop circuit 100 sequentially latches the received master clock signal of the transmission side block based on the master clock signal of the reception side block.

  For example, when the number of stages of the multi-stage flip-flop circuit 100 is three, the multi-stage flip-flop circuit 100 includes flip-flop circuits 101, 102, and 103. Each flip-flop circuit latches the input signal in response to the rise of the master clock signal of the receiving side block and outputs it as an output signal. The master clock signal of the transmission side block is input to the input terminal of the flip-flop circuit 101. The output of the flip-flop circuit 101 is input to the input terminal of the flip-flop circuit 101. The output of the flip-flop circuit 102 is input to the input terminal of the flip-flop circuit 103.

  The flip-flop circuits 101 and 102 are flip-flop circuits that input the master clock signal of the transmission side block in two stages using the master clock signal of the reception side block. The flip-flop circuit 103 is a flip-flop circuit for detecting the rise of the master clock signal of the transmission side block inputted in two stages.

The reset signal output circuit 200 detects the rising edge of the received master clock signal based on the signal output from the flip-flop circuit 100 in a plurality of stages and outputs a reset signal. For example, the reset signal output circuit 200 includes a logic circuit 201 and an inverter circuit 202. The logic circuit 201 is, for example, an OR circuit that inputs the output of the flip-flop circuit 102 to one input terminal via the inverter circuit 202 and inputs the output of the flip-flop circuit 103 to the other input terminal.
In the OR circuit as the logic circuit 201 of the reset signal output circuit 200, the output of the flip-flop circuit 102 becomes high level, that is, the output of the flip-flop circuit 102 inputted through the inverter circuit 202 becomes low level, and When the output of the flip-flop circuit 103 becomes low level, a low level reset signal is output.

  The mask signal output circuit 20 described above counts based on the master clock signal of the receiving block in response to the reset signal input from the reset signal output circuit 200 of the rising edge detection circuit 10, and the counted value A mask signal is output when is equal to a predetermined value.

  The mask signal output circuit 20 includes, for example, a counter unit, a comparison value storage unit, and a comparison unit. The counter unit resets the count value and starts counting based on the master clock signal of the receiving block in response to the reset signal input from the reset signal output circuit 200 of the rising edge detection circuit 10. . In the comparison value storage unit, a value to be compared with the value counted by the counter unit is stored in advance as a comparison value. The comparison unit compares the value counted by the counter unit with the value to be compared read from the comparison value storage unit, and outputs a mask signal when the comparison result matches.

  In the comparison value storage unit, a plurality of comparison values or a plurality of continuous comparison values may be stored in advance as comparison values. In this case, the comparison unit can output a mask signal having a period corresponding to a plurality of comparison values or a plurality of successive comparison values. As will be described later, in this comparison value storage unit, as will be described later, the transmission data from the transmission side block is generated at a timing at which a metastable is generated, or at a timing at which the setup time and hold time are not satisfied. Thus, values that are not captured by the receiving circuit of the receiving block in synchronization with the rising of the receiving master clock are stored in advance.

  Next, the operation of the asynchronous interface circuit 1 according to the first embodiment will be described with reference to FIG. First, at time t1, the transmission side master clock falls. Here, the mask signal output circuit 20 does not output a mask signal. That is, the mask signal output circuit 20 outputs a low level mask signal. Therefore, the mask circuit 30 supplies the reception side clock as the reception side clock without masking the reception side master clock.

  Thereafter, at time t3, the mask signal output circuit 20 outputs the mask signal to the mask circuit 30 because the counted value coincides with a predetermined value. That is, the mask signal output circuit 20 outputs a high level mask signal. The mask circuit 30 masks the reception side master clock according to the mask signal input from the mask signal output circuit 20, and supplies the masked reception side master clock to the reception side block as the reception side clock. Therefore, in the period from time t5 to time t6 and in the period from time t7 to time t8, the high pulse of the reception side master clock is masked by the mask circuit 30. The count of the mask signal output circuit 20 coincident at the time t3 is, for example, counted from the rising edge of the transmission side master clock immediately before the sequence shown in FIG.

  Thereafter, at time t6, the transmission side master clock rises. The transmission side block transmits transmission data in response to the rising of the transmission side master clock at time t6. Therefore, for example, after a predetermined delay time elapses from the rise of the transmission side master clock at time t6, transmission data from the transmission side block is input to the reception side block. For example, before and after time t7, transmission data from the transmission side block is input to the reception circuit of the reception side block.

  Here, at the time t5 or the time t7, in the reception side block, the mask circuit 30 supplies the masked reception side master clock to the reception side block as the reception side clock. Therefore, at time t5 or time t7, the receiving circuit in the receiving block does not capture transmission data from the transmitting block.

  Thereafter, the mask signal output circuit 20 stops outputting the mask signal to the mask circuit 30 at time t7. That is, at time t7, the mask signal output circuit 20 outputs a low level mask signal. The mask circuit 30 does not mask the reception-side master clock according to the mask signal input from the mask signal output circuit 20, and supplies the reception-side master clock that is not masked as a reception-side clock to the reception-side block.

  Next, the reception circuit of the reception side block supplied with the reception side master clock not masked as the reception side clock captures and receives the input transmission data in response to the rising of the reception side clock at time t9. Thereafter, the transmission circuit received by the receiving circuit is synchronized with the master clock signal masked by the clock generation circuit 2 in the subsequent circuit, and performs operations such as signal processing.

  Note that the rising edge detection circuit 10 detects the rising edge of the received transmission-side master clock and outputs a reset signal to the mask signal output circuit 20 in response to the rising edge of the reception-side master clock at time t7. The mask signal output circuit 20 to which the reset signal is input resets the counter value and starts counting in response to the rising of the receiving master clock. This count is used by the mask signal output circuit 20 to generate mask signals at later times t13 and t15.

  As described above, in the asynchronous interface circuit 1 according to the first embodiment, in the reception block, transmission data from the transmission side block such as the time t5 and the time t7 is input, and a metastable is generated. At this timing, or at a timing at which the setup time and hold time are not satisfied, the transmission data is not received and received in synchronization with the rising edge of the receiving master clock. This is because the reception side master clock masked by the clock generation circuit 2 is received by the reception side block from time t5 to t7 when transmission data is input to the reception circuit of the reception side block. This is because it is input as a clock.

  In the reception block, the clock generation circuit 2 supplies the transmission data at a timing at which a metastable is not generated and at a timing at which the setup time and hold time are satisfied (for example, at time t9). In response to the rising edge of the reception side clock, that is, in synchronization with the reception side clock, the reception circuit captures and receives the input transmission data.

  Therefore, according to this asynchronous interface circuit 1, the transmission side that operates in synchronization with each master clock signal so that the metastable is not generated and the setup time and hold time are satisfied. Transmission data can be transmitted and received between the block and the receiving block.

  Further, the transmission side block and the reception side block operate as a synchronization circuit in synchronization with each master clock signal. Further, the masking period of the mask circuit 30 is set to have a sufficient margin so that the interface between the transmission side block and the reception side block can be handled as a synchronous interface in the STA verification. Thereby, each block can be verified as a synchronous circuit. Therefore, the test pattern can be created without increasing as in the case of the asynchronous circuit verification.

  As for the verification of the asynchronous operation, only the portion of the asynchronous interface circuit 1 such as the clock generation circuit 2 needs to be verified. Therefore, in the overall verification of the transmission side block and the reception side block, verification of asynchronous operation becomes easy.

  In the above description, the case where the reception side block has the asynchronous interface circuit 1 has been described, but the transmission side block may have the asynchronous interface circuit 1. In this case, it is assumed that the master clock signal used for the synchronization processing in the transmission side block is faster than the master clock signal used for the synchronization processing in the reception side block. In this case, the clock generation circuit 2 receives the master clock signal of the receiving block, and the value counted based on the master clock signal of the transmitting block from the rising or falling edge of the received master clock signal is When the value matches a predetermined value, the master clock signal of the transmission side block is masked and supplied to the transmission side block.

  In this case, the transmission side block transmits transmission data in synchronization with the master clock signal masked by the clock generation circuit 2, and operates in synchronization with the master clock signal masked by the clock generation circuit 2. The receiving side block receives transmission data from the transmitting side block in synchronization with the master clock signal of the receiving side block, and operates in synchronization with the master clock signal of the receiving side block.

  In the first embodiment described above, the frequency of the master clock signal used for the synchronization process in the reception side block and the master clock signal used for the synchronization process in the transmission side block are The block having the fast master clock signal has the asynchronous interface circuit 1. This is because the clock generation circuit 2 that operates with the master clock signal with the fast frequency can count with the master clock signal with the fast frequency from the rising or falling edge of the received master clock signal with the slow frequency. It is. In addition, this makes it possible to generate a mask signal.

  The clock generation circuit 2 may include a PLL (Phase-Locked Loop) circuit that multiplies the master clock signal by a predetermined magnification. Here, a case where the receiving side block has the clock generation circuit 2 will be described. In this case, the PLL circuit multiplies the master clock signal of the receiving side block by a predetermined magnification.

  When the clock generation circuit 2 does not have a PLL circuit, as described above, the clock generation circuit 2 receives the master clock signal of the transmission side block, and the rising or rising edge of the received master clock signal. From the downstream, when the value counted based on the master clock signal of the receiving side block matches a predetermined value, the master clock signal of the receiving side block is masked and supplied to the receiving side block.

  On the other hand, when the clock generation circuit 2 has a PLL circuit, the clock generation circuit 2 receives the master clock signal of the transmission side block, and from the rising or falling edge of the received master clock signal. When the value counted based on the master clock signal of the receiving block multiplied by the PLL circuit matches the predetermined value, the master clock signal of the receiving block is masked and supplied to the receiving block To do. Specifically, the rising edge detection circuit 10 and the mask signal output circuit 20 operate based on the master clock signal of the reception side block, instead of operating based on the master clock signal of the reception side block. Works.

  The clock generation circuit 2 having this PLL circuit counts from the rising or falling edge of the received master clock signal even when the frequency of the master clock signal in the transmitting side block and the receiving side block is the same or almost the same. be able to.

  Therefore, the clock generation circuit 2 having this PLL circuit is configured so that metastable is not generated, similarly to the clock generation circuit 2 when the frequency of one master clock signal is high in the transmission side block and the reception side block, and The transmission data can be transmitted and received between the transmission side block and the reception side block having the respective master clock signals so that the setup time and the hold time are satisfied.

  Although the case where the reception side block has the clock generation circuit 2 has been described here, the transmission side block may have the clock generation circuit 2. In this case, the PLL circuit multiplies the master clock signal of the transmission side block by a predetermined magnification. The clock generation circuit 2 is the same as the case where the reception side block has the clock generation circuit 2.

<Second Embodiment>
Next, a second embodiment will be described with reference to FIGS. 3 and 4. Here, a case where the receiving side block has the asynchronous interface circuit 3 will be described.

  The clock generation circuit 4 according to the second embodiment includes a phase synchronization circuit 11, a mask signal output circuit 21, and a mask circuit 30. The phase synchronization circuit 11 receives the master clock signal of the transmission side block, and generates a signal that is phase-synchronized with the received master clock signal as a phase synchronization signal.

  The mask signal output circuit 21 counts based on the master clock signal of the receiving side block in accordance with the period in which the phase synchronization signal generated by the phase synchronization circuit 11 is at the high level, and the counted value is determined in advance. When the values match, the mask signal is output in the same manner as the mask signal output circuit 20. Based on the mask signal output from the mask signal output circuit 21, the mask circuit 31 masks the master clock signal of the reception side block and supplies it to the reception side block in the same manner as the mask circuit 30.

  Next, details of each component will be described. The phase synchronization circuit 11 includes a phase comparator 111, a loop filter circuit 112, a DCO (digitally controlled oscillator) 113, and a frequency divider 114. The master clock signal of the transmission side block is input to one input terminal of the phase comparator 111, and the phase synchronization signal generated by the frequency divider 114 is input to the other terminal of the phase comparator 111. . The phase comparator 111 converts the phase difference between the two input signals into a voltage and outputs the voltage.

  The loop filter circuit 112 is a low-pass filter that compensates the phase of the signal input from the phase comparator 111 and outputs the signal. The DCO 113 is a digitally controlled oscillator that controls the oscillation frequency with a digital signal, and controls the frequency of the output pulse with the digital signal input from the loop filter circuit 112.

  The frequency divider 114 divides the frequency input from the DCO 113 into N (where N is a predetermined integer or fraction) and outputs it as a phase synchronization signal. For example, the value of N may be fixed to 1. When the value of N is 1, the phase synchronization circuit 11 generates a 1 × phase synchronization signal that is phase-synchronized with the master clock signal of the transmission side block.

  The mask signal output circuit 21 has the same configuration as the mask signal output circuit 20. However, the counter unit of the mask signal output circuit 20 counts based on the master clock signal of the receiving block in accordance with the period of the phase synchronization signal generated by the phase synchronization circuit 11 being at the high level. The mask circuit 31 has the same configuration as the mask circuit 30.

  Next, the operation of the clock generation circuit 4 according to the second embodiment will be described with reference to FIG. Similar to the clock generation circuit 2 according to the first embodiment, for example, the mask signal output circuit 21 outputs a mask signal in a period from time t4 to time t6. That is, the mask signal output circuit 21 outputs a high level mask signal. Then, the mask circuit 31 masks the reception-side master clock in accordance with the high-level mask signal during the period from time t4 to time t6, and uses the masked reception-side master clock as the reception-side clock. To supply.

  Thereafter, after time t6, the mask signal output circuit 21 does not output a mask signal. That is, the mask signal output circuit 21 outputs a low level mask signal. Then, after time t6, the mask circuit 31 does not mask the reception-side master clock according to the low-level mask signal, and supplies the reception-side master clock that is not masked as a reception-side clock to the reception-side block. .

  For example, at time t6, the reception circuit of the reception side block receives and receives the transmission data in response to the rising of the reception side clock supplied from the mask circuit 31, that is, in synchronization with the reception side clock.

  Therefore, as with the asynchronous interface circuit 1 according to the first embodiment, the asynchronous interface circuit 3 according to the second embodiment is configured so that metastable is not generated and the setup time and hold time are satisfied. Thus, transmission data can be transmitted and received between the transmission side block and the reception side block having the respective master clock signals.

  Although the case where the reception side block has the clock generation circuit 4 has been described here, the clock generation circuit 4 according to the second embodiment is connected to the transmission side similarly to the clock generation circuit 2 according to the first embodiment. You may make it a block have.

  Further, the clock generation circuit 2 according to the first embodiment and the clock generation circuit 4 according to the second embodiment may be used in combination. For example, the clock generation circuit 4 according to the second embodiment uses the phase synchronization circuit 11, but when the power is turned on, the phase synchronization circuit 11 generates a phase synchronization signal that is phase-synchronized with the received master clock signal. A predetermined period may be required before output.

  By combining the first embodiment with the second embodiment at the time of turning on the power, the first embodiment and the first embodiment can be obtained even during the period when the phase synchronization circuit 11 is not in phase synchronization at the time of turning on the power. Similarly, transmission data can be transmitted and received between the transmission side block and the reception side block.

  In the case of combination, for example, the clock generation circuit 4 according to the second embodiment has the rising detection circuit 10 of the clock generation circuit 2 according to the first embodiment. Then, the rising edge detection circuit 10 inputs the reset signal to the frequency divider 114 of the phase synchronization circuit 11. Then, in response to the input of the reset signal, the frequency divider 114 starts a process of synchronizing the phase and outputs a phase synchronization signal. Thereby, the mask signal output circuit 21 and the mask circuit 31 can operate in the same manner as in the second embodiment.

  In the above description, the circuit configuration of the asynchronous interface circuit 1 or 3 has been described. However, the transmission block and the reception block are described in a hardware description language using the asynchronous interface circuit 1 or 3 having this circuit configuration. It is also possible to design the STA and verify the STA. Further, the design and STA verification according to this description may be performed on a computer device. Further, this may be a program for operating on a computer device, or this program may be recorded on a recording medium.

  The comparison value storage unit is configured by a register or RAM in an application specific integrated circuit (ASIC) or a field programmable gate array (FPGA), a nonvolatile memory such as a ROM or a flash memory, or a combination thereof. .

  The embodiment of the present invention has been described in detail with reference to the drawings. However, the specific configuration is not limited to this embodiment, and includes design and the like within a scope not departing from the gist of the present invention.

It is a block diagram which shows the structure of the asynchronous interface circuit by 1st Embodiment of this invention. It is a sequence diagram which shows operation | movement of the asynchronous interface circuit of FIG. It is a block diagram which shows the structure of the asynchronous interface circuit by 2nd Embodiment of this invention. FIG. 4 is a sequence diagram showing an operation of the asynchronous interface circuit of FIG. 3. It is a block diagram which shows the structure of the asynchronous interface circuit by a prior art. FIG. 6 is a sequence diagram showing an operation of the asynchronous interface circuit of FIG. 5.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1, 3 ... Asynchronous interface circuit, 2, 4 ... Clock generation circuit, 10 ... Rising detection circuit, 11 ... Phase synchronous circuit, 20, 21 ... Mask signal output circuit, 30, 31 ... Mask circuit, 100 ... Multiple stage flip-flop 101, 102, 103, 1010, 1011, 1012, 2010, 2011 ... flip-flop circuit, 111 ... phase comparator, 112 ... loop filter circuit, 113 ... DCO, 114 ... frequency divider, 200 ... reset signal output Circuit 201 ... Logic circuit 202 ... Inverter circuit

Claims (6)

An asynchronous interface circuit between a sending block and a receiving block each having a master clock signal,
One block of the transmitting block and the receiving block is
When the master clock signal of the other block is received, and the value counted based on the master clock signal of the one block from the rising or falling edge of the received master clock signal matches the predetermined value A clock generation circuit that masks the master clock signal of the one block and supplies the master clock signal to the one block;
An asynchronous interface circuit characterized by comprising: If the one block is a receiving block,
The sender block is
Transmitting transmission data in synchronization with the master clock signal of the transmission side block, and operating in synchronization with the master clock signal of the transmission side block,
The receiving block is
The clock generation circuit receives transmission data from the transmission side block in synchronization with the masked master clock signal, and the clock generation circuit operates in synchronization with the masked master clock signal.
The asynchronous interface circuit according to claim 1. If the one block is a sender block,
The sender block is
Transmitting transmission data in synchronization with the master clock signal masked by the clock generation circuit, and operating in synchronization with the master clock signal masked by the clock generation circuit,
The receiving block is
Receiving transmission data from the transmission side block in synchronization with the master clock signal of the reception side block, and operating in synchronization with the master clock signal of the reception side block;
The asynchronous interface circuit according to claim 1. The clock generation circuit includes:
A rising edge detection circuit that receives the master clock signal of the other block and detects the rising edge of the received master clock signal;
A mask signal output that counts based on the master clock signal of the one block based on the rising edge detected by the rising edge detection circuit and outputs a mask signal when the counted value matches a predetermined value Circuit,
A mask circuit that masks the master clock signal of the one block and supplies the mask signal to the one block based on a mask signal output from the mask signal generation circuit;
The asynchronous interface circuit according to claim 1, further comprising: The clock generation circuit includes:
A phase synchronization circuit that receives the master clock signal of the other block and generates a signal that is phase-synchronized with the received master clock signal as a phase synchronization signal;
When counting is performed based on the master clock signal of the one block according to the period of the phase synchronization signal generated by the phase synchronization circuit being at a high level, and the counted value matches a predetermined value A mask signal output circuit for outputting a mask signal;
A mask circuit that masks the master clock signal of the one block and supplies the mask signal to the one block based on a mask signal output from the mask signal generation circuit;
The asynchronous interface circuit according to claim 1, further comprising: An asynchronous interface method used in an asynchronous interface circuit between a transmission side block and a reception side block each having a master clock signal,
One block of the transmitting block and the receiving block is
When the master clock signal of the other block is received, and the value counted based on the master clock signal of the one block from the rising or falling edge of the received master clock signal matches the predetermined value In addition, the master clock signal of the one block is masked and supplied to the one block.
An asynchronous interface method characterized by the above.

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