CN110299915B

CN110299915B - Clock recovery circuit

Info

Publication number: CN110299915B
Application number: CN201910368028.3A
Authority: CN
Inventors: 孙凯; 姚超凡
Original assignee: Xingchen Technology Co ltd
Current assignee: Xingchen Technology Co ltd
Priority date: 2019-05-05
Filing date: 2019-05-05
Publication date: 2022-10-14
Anticipated expiration: 2039-05-05
Also published as: CN110299915A

Abstract

A clock recovery circuit comprises a phase detector, a charge pump, a voltage-controlled oscillator, a frequency divider and a loop filter, wherein the phase detector, the charge pump, the voltage-controlled oscillator and the frequency divider are sequentially connected, the loop filter is coupled between the charge pump and the voltage-controlled oscillator, the clock signal is input into a multi-rate mode adjusting module, the multi-rate mode adjusting module generates any one of three clock signals of half frequency, full frequency and frequency multiplication according to setting, the generated clock signal is input into a half-speed phase detecting module, and any one of the clock recovery circuit of half-speed mode, full speed mode and double-speed mode can be generated by combining the setting, so that the compatibility of circuit design is greatly improved, and the chip cost is saved.

Description

Clock recovery circuit

Technical Field

The invention relates to the field of integrated circuit design, in particular to a clock recovery circuit.

Background

Clock Recovery Circuits (CDR) are widely used for high-speed Data reception, for recovering the correct Clock and Data signals from the transmitter, including but not limited to through chip packaging, application boards, connectors, or Data lines.

The clock recovery circuit includes an analog type and a digital type. As for the analog clock recovery circuit, the main structure of the analog clock recovery circuit is shown in fig. 1, and includes a phase detector 11, a charge pump 12, a voltage-controlled oscillator 13, and a frequency divider 14 connected in sequence, and further includes a loop filter 15 coupled between the charge pump 12 and the voltage-controlled oscillator 13.

The phase detector is used to detect the phase of the input data signal and output a signal that helps generate a clock signal that can modify the phase of the input signal. For a non-linear phase detector, two data samples and one band edge sample are used to provide sign information for the phase offset, helping to generate a clock signal with the band edge calibrated to the center position of the input data waveform. Fig. 2 shows a basic signal timing diagram of the phase detector shown in fig. 1. If the band edge sample is different from the first data in the input data Din and is the same as the second data, the clock signal is considered to be delayed, and the phase of the clock signal is advanced by the output symbol information (En ≦ Dn); in contrast, if the band edge sample is the same as the first data in the input data Din and different from the second data, the clock signal is considered to be delayed, and the output sign information (En ∞ Dn + 1) delays the clock signal phase. The clock signal bandedge is adjusted to the center of the input data waveform by increasing or decreasing the clock signal phase.

The clock recovery circuit described above has different data rate modes based on the ratio between the frequency of the operating clock and the input data rate. Full rate mode means that the frequency of the recovered clock is N Hz, the incoming data rate is N bps; the half-speed mode means that the frequency of the recovered clock is N/2Hz, and the input data rate is N bps; the double speed mode means that the frequency of the recovered clock is 2N Hz and the input data rate is N bps. Generally, defined as M-rate mode, this means that the frequency of the recovered clock is M × N Hz and the input data rate is N bps.

In the prior art, different data protocols correspond to different data transmission rates. For example, the SATA protocol defines three data transfer rates of 1.5G bps, 3G bps, and 6G bps, the PCIE protocol defines four data transfer rates of 2.5G bps, 5G bps, 8G bps, and 16G bps, the DP protocol defines four data transfer rates of 1.62G bps, 2.7G bps, 5.4G bps, and 8.1G bps, and so on. This requires different clock recovery circuits to be designed to match different data transmission rates, which is obviously not favorable for miniaturization of chip area and increases product cost.

Disclosure of Invention

The invention aims to provide a clock recovery circuit which is compatible with various frequencies.

In order to solve the above problems, the present invention provides a clock recovery circuit, which includes a phase detector, a charge pump, a voltage-controlled oscillator, and a frequency divider connected in sequence, and further includes a loop filter coupled between the charge pump and the voltage-controlled oscillator, wherein the phase detector includes a multi-rate mode adjustment module and a half-rate phase detection module, the clock signal is input to the multi-rate mode adjustment module, the multi-rate mode adjustment module generates any one of a half-frequency, a full-frequency, and a frequency-doubled clock signal according to a setting, and inputs the generated clock signal to the half-rate phase detection module, and any one of a half-rate mode, a full-rate mode, or a double-rate mode clock recovery circuit can be generated by combining the above settings.

Optionally, the phase detector includes a plurality of multi-rate mode adjustment modules connected in series, and each multi-rate mode adjustment module may independently generate any one of full-frequency, double-frequency and half-frequency clock signals according to a setting.

Optionally, the half-speed phase detection module includes a first stage of No. 0D flip-flop to No. 3D flip-flop, a second stage of No. 0 xor gate to No. 3 xor gate, and a third stage of No. 4D flip-flop to No. 7D flip-flop: clock input ends of the No. 0D trigger and the No. 3D trigger are respectively connected with clock signals of a 0-degree phase, a 90-degree phase, a 180-degree phase and a 270-degree phase, positive input ends D are respectively connected with data signals, a positive output end Q of the No. 0D trigger is respectively connected with input ends of the No. 0 XOR gate and the No. 3 XOR gate, a positive output end Q of the No. 1D trigger is respectively connected with input ends of the No. 1 XOR gate and the No. 0 XOR gate, a positive output end Q of the No. 2D trigger is respectively connected with input ends of the No. 2 XOR gate and the No. 1 XOR gate, and a positive output end Q of the No. 3D trigger is respectively connected with input ends of the No. 3 XOR gate and the No. 2 XOR gate; clock input ends of the No. 0D trigger and the No. 3D trigger are respectively connected with clock signals of a 0-degree phase, a 90-degree phase, a 180-degree phase and a 270-degree phase, a positive input end D is respectively connected with output ends of the No. 0 XOR gate and the No. 3 XOR gate, a positive output end Q is respectively used as a data output end of the half-speed phase detection module, and the data frequency of an output signal is half of that of input data.

Optionally, the multi-rate mode adjusting module includes a number 0D trigger to a number 1D trigger, a number 0 data selector to a number 5 data selector; the clock input ends of the No. 0D trigger and the No. 1D trigger are connected with a 0-degree phase clock signal, the positive input end D of the No. 0D trigger is connected with the negative output end Q (-), and the positive output end Q of the No. 0D trigger is connected with the positive input end D of the No. 1D trigger; the low level input ends of the data selector 0 and the data selector 1 are respectively connected to the positive output ends Q of the D flip-flop 0 and the D flip-flop 1, and the high level input ends are connected with a phase clock 0 degree and a phase clock 180 degree of a full-speed clock; the low level input ends of the No. 2 data selector and the No. 4 data selector are respectively connected to the output end Q of the No. 0 data selector, and the high level input ends are connected with a 0-degree phase clock signal and a 180-degree phase clock signal of a half-speed clock; the low level input ends of the No. 3 data selector and the No. 5 data selector are respectively connected to the output end Q of the No. 1 data selector, and the high level input ends are connected with a 90-degree phase clock signal and a 270-degree phase clock signal of a half-speed clock; the data selectors 2 to 5 output the modulated clock signals of 0 °,90 °, 180 °, and 270 ° phases, respectively.

The multi-rate mode adjusting module can generate any one of full-frequency, frequency-multiplication and half-frequency clock signals according to the setting, and the generated clock signals are input into the half-speed phase detecting module, and the combination of the setting can generate any one of a double-speed mode, a half-speed mode and a full-speed mode, and can also implement a multi-rate compatible scheme of half-speed, full-speed and the like based on a 1/4 rate mode. Therefore, the clock signal with more multiple speed can be configured under the condition of relatively less increasing cost, and the frequency compatibility of the clock recovery circuit is increased.

Drawings

Fig. 1 is a schematic diagram showing a structure of an analog clock recovery circuit in the prior art, and fig. 2 is a signal timing diagram of the circuit shown in fig. 1.

Fig. 3 is a schematic diagram of a clock recovery circuit according to an embodiment of the present invention.

FIG. 4 is a circuit diagram of one embodiment of the half-speed phase detection module of FIG. 3, and FIG. 5 is a timing diagram of the above circuit.

Fig. 6 is a circuit diagram illustrating one embodiment of the multi-rate mode adjustment module of fig. 3.

Detailed Description

The following describes in detail a specific embodiment of the clock recovery circuit according to the present invention with reference to the drawings.

Fig. 3 is a schematic structural diagram of a clock recovery circuit according to this embodiment, which includes a phase detector 31, a charge pump 32, a voltage-controlled oscillator 33, and a frequency divider 34 connected in sequence, and further includes a loop filter 35 coupled between the charge pump 32 and the voltage-controlled oscillator 33. In this embodiment, in order to support the multi-rate mode, the phase detector 31 includes a multi-rate mode adjustment module 321 and a half-rate phase detection module 322, the clock signal is input to the multi-rate mode adjustment module 321, the multi-rate mode adjustment module 321 generates any one of three clock signals of full frequency, double frequency and half frequency according to a setting, and inputs the generated clock signal to the half-rate phase detection module 322, and the combination of the above settings can generate any one of the full-rate mode, the double-rate mode and the half-rate mode.

Fig. 4 is a circuit diagram of one embodiment of the half-speed phase detection module 322 of fig. 3. The half-speed phase detection module 322 includes a first stage of No. 0D flip-flop DFF0 to No. 3D flip-flop DFF3, a second stage of No. 0 exclusive or gate XOR0 to No. 3 exclusive or gate XOR3, and a third stage of No. 4D flip-flop DFF4 to No. 7D flip-flop DFF7.

Clock input ends of the D flip-flops DFF0 to DFF3 are respectively connected with clock signals of phases of 0 degrees, 90 degrees, 180 degrees and 270 degrees, positive input ends D are respectively connected with data signals, a positive output end Q of the D flip-flop DFF0 is respectively connected with input ends of XOR0 and XOR3, a positive output end Q of the D flip-flop DFF1 is respectively connected with input ends of XOR1 and XOR0, a positive output end Q of the D flip-flop DFF2 is respectively connected with input ends of XOR2 and XOR1, and a positive output end Q of the D flip-flop DFF3 is respectively connected with input ends of XOR3 and XOR 2; clock input ends of the D flip-flops DFF0 to DFF3 are respectively connected with clock signals of 0-degree phase, 90-degree phase, 180-degree phase and 270-degree phase, a positive input end D is respectively connected with output ends of the exclusive-OR gates XOR0 to 3-degree XOR3, a positive output end Q is respectively used as a data output end of the half-speed phase detection module, and the data frequency of an output signal is half of that of input data.

The DATA signal (DATA) is used for sampling. The clock signals CLK0, CLK90, CLK180, and CLK270 in the 0 ° phase, 90 ° phase, 180 ° phase, and 270 ° phase have the same frequency, which is half the frequency of the data signal. The configured D flip-flops are all positive flip-flops, and a positive input end D outputs the same-direction level to a positive output end Q at the rising edge of a clock signal. Fig. 5 shows a timing diagram of the above circuit, and it can be seen that the 0 ° phase clock signal CLK0 samples the data D0 through the No. 0D flip-flop DFF0, and the 90 ° phase clock signal CLK90 samples the data E0 through the No. 1D flip-flop DFF 1. The signals D0 and E0 are operated by an exclusive or gate XOR0 of No. 0 to generate symbol information, which is used for clock error correction. The symbol information obtained after the E0 ≦ D0 operation is used in the D flip-flop DFF4 No. 4, and the phase of the recovered clock is corrected through subsequent processing of circuits such as a charge pump, etc., so as to achieve the purpose of phase alignment with the input DATA, thereby correcting the clock frequency of the DATA signal D0. By analogy, the operation results of E0 bolad 1, E1 bolad 2 are also used for clock error correction of E0, D1, and E1, thereby achieving the purposes of phase alignment and clock recovery. The positive output terminals Q of the D flip-flops No. 4 to No. 7 DFF4 to DFF7 are respectively used to output different sign information.

Fig. 6 is a circuit diagram of one embodiment of the multi-rate mode adjustment module of fig. 3, including D flip-flop No. 0 DFF0, D flip-flop No. 1 DFF1, data selector No. 0 MUX0 through data selector No. 5 MUX5.

The multi-rate mode adjusting module comprises a number 0D trigger to a number 1D trigger, a number 0 data selector to a number 5 data selector; the clock input ends of the No. 0D trigger and the No. 1D trigger are connected with a 0-degree phase clock signal, the positive input end D of the No. 0D trigger is connected with the negative output end Q (-), and the positive output end Q of the No. 0D trigger is connected with the positive input end D of the No. 1D trigger; the low-level input ends of the No. 0 data selector and the No. 1 data selector are respectively connected to the positive output ends Q of the No. 0D trigger and the No. 1D trigger, and the high-level input ends are connected with a 0-degree phase clock and a 180-degree phase clock signal of a full-speed clock; the low level input ends of the No. 2 data selector and the No. 4 data selector are respectively connected to the output end Q of the No. 0 data selector, and the high level input ends are connected with a 0-degree phase clock signal and a 180-degree phase clock signal of a half-speed clock; the low level input ends of the 3-number data selector and the 5-number data selector are respectively connected to the output end Q of the 1-number data selector, and the high level input ends are connected with a 90-degree phase clock signal and a 270-degree phase clock signal of a half-speed clock; the data selectors 2 to 5 output the modulated clock signals of 0 °,90 °, 180 °, and 270 ° phases, respectively.

The circuit can be selectively operated in a half-speed mode, a full-speed mode or a double-speed mode in actual operation. Setting the data selection ends of the MUX0 and the MUX1 to be low level, and setting the data selection ends of the MUX2 to the MUX5 to be high level, and then working in a half-speed mode; the MUXs 2 to 5 output clock signals CLK _ HR _0, CLK _ HR _90clk _hr _, HR _, 180, and CLK _ HR _270 in a phase of 0 °,90 °, 180 °, and 270 ° in a half-speed mode, respectively, which is the same as the half-speed phase detection block 322 shown in fig. 3. The drive ends of MUX0 and MUX1 are selected to be high level, and MUX2 to MUX5 are selected to be low level, so that the full-speed mode is operated; MUX2 and MUX4 output the 0 phase full-speed clock signal CLK _ FR _0 from MUX0, and MUX3 and MUX5 output the 180 phase full-speed clock signal CLK _ FR _180 from MUX 1. The driving ends of MUX0 and MUX1 are selected to be low level, and MUX2 to MUX5 are also selected to be low level, so that the double-speed mode is operated; the MUXs 2 to 5 respectively output the clock signals divided by the CLK _ DR _ 0.

The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.

Claims

1. A clock recovery circuit, the said clock recovery circuit includes phase detector, charge pump, voltage controlled oscillator, and frequency divider connected sequentially, also include coupling to the loop filter between charge pump and voltage controlled oscillator, characterized by that, the said phase detector includes a many-rate mode regulating module and a half-speed phase detection module, the clock signal inputs the many-rate mode regulating module, the said many-rate mode regulating module produces any one in half-frequency, all-frequency and frequency-doubled clock signal according to setting, and input the clock signal produced to the half-speed phase detection module, the combination of the above-mentioned settings, can produce any one in half-speed mode, full-speed mode or two-speed mode clock recovery circuit; wherein

Half speed phase detection module includes the D flip-flop of 0 # to the D flip-flop of 3 # of first grade, the exclusive OR gate of 0 # to the exclusive OR gate of 3 # of second grade to and the D flip-flop of 4 # to the D flip-flop of 7 # of third grade:

clock input ends of the D flip-flops 0 to 3 are respectively connected with clock signals of a phase of 0 degree, a phase of 90 degrees, a phase of 180 degrees and a phase of 270 degrees, positive input ends D are respectively connected with data signals, a positive output end Q of the D flip-flop 0 is respectively connected with input ends of an exclusive-OR gate 0 and an exclusive-OR gate 3, a positive output end Q of the D flip-flop 1 is respectively connected with input ends of an exclusive-OR gate 1 and an exclusive-OR gate 0, a positive output end Q of the D flip-flop 2 is respectively connected with input ends of an exclusive-OR gate 2 and an exclusive-OR gate 1, and a positive output end Q of the D flip-flop 3 is respectively connected with input ends of an exclusive-OR gate 3 and an exclusive-OR gate 2;

clock input ends of the No. 4D flip-flops to the No. 7D flip-flops are respectively connected with clock signals of 0-degree phase, 90-degree phase, 180-degree phase and 270-degree phase, a positive input end D is respectively connected with output ends of the No. 0 XOR gate to the No. 3 XOR gate, a positive output end Q is respectively used as a data output end of the half-speed phase detection module, and the data frequency of an output signal is half of that of input data;

the multi-rate mode adjusting module comprises a D trigger from 0 to 1, a data selector from 0 to 5;

the clock input ends of the No. 0D trigger and the No. 1D trigger are connected with a 0-degree phase clock signal, 0

Positive input end D and negative output end of number D trigger

The positive output end Q of the D flip-flop No. 0 is connected with the positive input end D of the D flip-flop No. 1;

the low level input ends of the data selector 0 and the data selector 1 are respectively connected to the positive output ends Q of the D flip-flop 0 and the D flip-flop 1, and the high level input ends are connected with a phase clock 0 degree and a phase clock 180 degree of a full-speed clock;

the low level input ends of the No. 2 data selector and the No. 4 data selector are respectively connected to the output end Q of the No. 0 data selector, and the high level input ends are connected with a 0-degree phase clock signal and a 180-degree phase clock signal of a half-speed clock;

the low level input ends of the No. 3 data selector and the No. 5 data selector are respectively connected to the output end Q of the No. 1 data selector, and the high level input ends are connected with a 90-degree phase clock signal and a 270-degree phase clock signal of a half-speed clock;

the data selectors 2 to 5 output the modulated clock signals of 0 °,90 °, 180 °, and 270 ° phases, respectively.