WO2012126420A3 - Data and clock recovery module and data and clock recovery method - Google Patents

Data and clock recovery module and data and clock recovery method Download PDF

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Publication number
WO2012126420A3
WO2012126420A3 PCT/CN2012/075299 CN2012075299W WO2012126420A3 WO 2012126420 A3 WO2012126420 A3 WO 2012126420A3 CN 2012075299 W CN2012075299 W CN 2012075299W WO 2012126420 A3 WO2012126420 A3 WO 2012126420A3
Authority
WO
WIPO (PCT)
Prior art keywords
data
signal
clock recovery
clock
adjusted
Prior art date
Application number
PCT/CN2012/075299
Other languages
French (fr)
Chinese (zh)
Other versions
WO2012126420A2 (en
Inventor
付生猛
廖振兴
余长亮
Original Assignee
华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to PCT/CN2012/075299 priority Critical patent/WO2012126420A2/en
Priority to CN201280000894.3A priority patent/CN102859927B/en
Publication of WO2012126420A2 publication Critical patent/WO2012126420A2/en
Publication of WO2012126420A3 publication Critical patent/WO2012126420A3/en

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0337—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/0807—Details of the phase-locked loop concerning mainly a recovery circuit for the reference signal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

The embodiments of the present invention relate to a data and clock recovery module and a data and clock recovery method. The method includes: performing phase adjustment on a clock signal generated on the basis of the reference frequency according to a first control signal, and performing phase adjustment on a data signal according to the first control signal, wherein the phase adjustment direction of the clock signal is contrary to that of the data signal, the frequency of the clock signal is locked onto that of the data signal, and the first control signal is obtained by filtering the phase difference between the adjusted clock signal and the adjusted data signal; and sampling the adjusted data signal using the adjusted clock signal so as to obtain a data signal synchronous with the adjusted clock signal. The embodiments of the present invention reduce the synchronization time of the clock signal and the data signal, and improve the jitter performance.
PCT/CN2012/075299 2012-05-10 2012-05-10 Data and clock recovery module and data and clock recovery method WO2012126420A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
PCT/CN2012/075299 WO2012126420A2 (en) 2012-05-10 2012-05-10 Data and clock recovery module and data and clock recovery method
CN201280000894.3A CN102859927B (en) 2012-05-10 2012-05-10 Data and clock recovery module and data and clock recovery method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2012/075299 WO2012126420A2 (en) 2012-05-10 2012-05-10 Data and clock recovery module and data and clock recovery method

Publications (2)

Publication Number Publication Date
WO2012126420A2 WO2012126420A2 (en) 2012-09-27
WO2012126420A3 true WO2012126420A3 (en) 2013-04-18

Family

ID=46879796

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2012/075299 WO2012126420A2 (en) 2012-05-10 2012-05-10 Data and clock recovery module and data and clock recovery method

Country Status (2)

Country Link
CN (1) CN102859927B (en)
WO (1) WO2012126420A2 (en)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20150016534A (en) 2012-05-09 2015-02-12 자프겐 인크. Fumagillol type compounds and methods of making and using same
WO2012126420A2 (en) * 2012-05-10 2012-09-27 华为技术有限公司 Data and clock recovery module and data and clock recovery method
US9246669B2 (en) * 2014-05-22 2016-01-26 Analog Devices Global Apparatus and method for modular signal acquisition and detection
CN104135413B (en) * 2014-07-29 2017-06-13 北京航天自动控制研究所 A kind of high-speed serial bus sampling system suitable for multiple spot interconnecting application occasion
CN108886464B (en) * 2016-08-31 2020-08-14 华为技术有限公司 Clock recovery device and clock recovery method
CN110299915B (en) * 2019-05-05 2022-10-14 星宸科技股份有限公司 Clock recovery circuit
CN111092714B (en) * 2019-12-10 2022-05-06 中国科学院微电子研究所 High-speed signal clock recovery method and device
CN113078978A (en) * 2021-03-26 2021-07-06 杭州加速科技有限公司 Synchronization method, system and test method for remote multi-ATE semiconductor test equipment
CN113507286A (en) * 2021-06-16 2021-10-15 深圳市傲科光电子有限公司 Method, apparatus and computer readable storage medium for determining clock signal
CN115378567B (en) * 2022-08-19 2023-07-18 深圳市紫光同创电子有限公司 Clock synchronization circuit, clock synchronization method and electronic equipment
WO2024103269A1 (en) * 2022-11-16 2024-05-23 华为技术有限公司 Time synchronization method and apparatus

Citations (4)

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CN1666456A (en) * 2003-05-01 2005-09-07 三菱电机株式会社 Clock data recovery circuit
CN1973478A (en) * 2003-12-08 2007-05-30 日本电气株式会社 Clock and data recovery circuit
CN101867368A (en) * 2009-04-20 2010-10-20 索尼公司 Clock data recovery circuit and multiplied-frequency clock generation circuit
CN102859927A (en) * 2012-05-10 2013-01-02 华为技术有限公司 Data and clock recovery module and data and clock recovery method

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US5864250A (en) * 1996-05-21 1999-01-26 Advanced Communications Devices Corporation Non-servo clock and data recovery circuit and method
CN1286289C (en) * 2003-04-25 2006-11-22 中兴通讯股份有限公司 Circuit for recovering timing data and implementing method
US7301996B1 (en) * 2003-05-28 2007-11-27 Lattice Semiconductor Corporation Skew cancellation for source synchronous clock and data signals
CN1798018A (en) * 2004-12-30 2006-07-05 中兴通讯股份有限公司 Device and method for synchronizing system clock
US7978802B1 (en) * 2007-10-12 2011-07-12 Xilinx, Inc. Method and apparatus for a mesochronous transmission system
CN101964688B (en) * 2009-07-21 2015-05-20 中兴通讯股份有限公司 Method and system for recovering data clock
CN102223198B (en) * 2011-06-17 2016-12-21 中兴通讯股份有限公司 One realizes clock recovery method and device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1666456A (en) * 2003-05-01 2005-09-07 三菱电机株式会社 Clock data recovery circuit
CN1973478A (en) * 2003-12-08 2007-05-30 日本电气株式会社 Clock and data recovery circuit
CN101867368A (en) * 2009-04-20 2010-10-20 索尼公司 Clock data recovery circuit and multiplied-frequency clock generation circuit
CN102859927A (en) * 2012-05-10 2013-01-02 华为技术有限公司 Data and clock recovery module and data and clock recovery method

Also Published As

Publication number Publication date
CN102859927A (en) 2013-01-02
CN102859927B (en) 2015-03-11
WO2012126420A2 (en) 2012-09-27

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