JP2014096709A - Clock reproduction device and method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reproduce a clock corresponding to a plurality of client signals, in the processing of a high speed transmission signal framed in multistep with a multi-tier frame by common PLL.SOLUTION: In a clock reproduction device for reproducing the clock of client data of data amount C transmitted in a format framed in multistep with a multi-tier frame in line data of data amount L, a phase difference signal corresponding to the phase difference of a frequency division clock of a clock obtained by multiplying the frequency of a client clock signal by L/C, and a frequency division clock of a signal obtained by multiplying the frequency of a line clock signal by L/C, is fed back to a circuit (20) generating the client clock signal.

Description

  The present invention relates to a clock recovery apparatus and method, and more particularly, in a processing of a high-speed transmission signal (for example, OTU4, 112 Gbps) framed in multiple stages in a plurality of layers in an optical transmission system, a plurality of high-speed transmission signals. The present invention relates to a clock recovery apparatus and method necessary for demapping processing for extracting data corresponding to client data of the client.

  2. Description of the Related Art Conventionally, an optical transmission system that transmits a plurality of client signals having a bit rate of several tens of Gbps, such as SONET, SDH, and Ethernet (registered trademark) in a multi-layered frame format in a multi-layered frame has been actively developed. ing.

  When performing demapping processing for extracting client data from line data transmitted in a multi-layered frame format with multiple layers of frames, a clock signal is recovered from the line data, and the client in the line data is recovered from the recovered clock signal. Data is being retrieved. When the recovered clock signal is recovered from the line data at the time of demapping, it is necessary to generate an enable signal obtained by alternately generating the enable period and the disable period of the ratio of the client data to the line data. (For example, patent document 2). An enable signal generation circuit is described in Patent Document 3, for example. The clock recovery signal is obtained by a phase-locked loop circuit that oscillates a clock signal by using the enable signal as a phase comparison target in phase-locked loop processing and uses the oscillated clock signal as a phase comparison target with the enable signal. (For example, Patent Documents 2 and 3).

JP 2001-177491 A (paragraphs 0008, 10 and 15) Japanese Patent No. 4927033 (paragraphs 0004 and 0005) Japanese Patent No. 4789976

  2. Description of the Related Art Conventionally, a separation device on the receiving side of an optical transmission system has the above-described enable generation circuit and phase in order to regenerate a clock of a client signal (client data) transmitted in a multi-layered frame format with multiple layers of frames. A lock loop (PLL).

  FIG. 3 shows a configuration of a clock recovery device 50 having a PLL for high-speed transmission signals (OTU3, 43 Gbps) configured in the prior art. The PLL in FIG. 3 includes a client clock generation circuit 20 that generates a client clock signal, a frequency-divided clock generation circuit 22 that generates a divided clock by dividing the generated client clock signal into a fixed number, an enable signal A frequency-divided clock generation circuit 14 that generates a frequency-divided clock by dividing the line clock signal during the enable period into a fixed frequency, and the frequency-divided line clock signal during the enable period A phase comparison circuit 24 that detects a phase difference of the client clock signal and outputs a phase difference signal corresponding to the phase difference; and a smoothing circuit (LPF) 26 that smoothes the phase difference signal and outputs the phase difference signal to the client clock generation circuit 20 Is provided.

  FIG. 3 also shows a demapping processing circuit 10 and an enable signal generation circuit 12. The demapping processing circuit 10 performs demapping processing on the line signal (line data) for transmitting the client data in a multi-layered format with a plurality of hierarchical frames by using the above-described client clock signal, and extracts the client data (output) Circuit). The demapping processing circuit 10 supplies the amount of client data (for example, converted into the number of bits) C and the amount of line data in which the client data is framed (for example, converted into the number of bits) L to the enable signal generating circuit 12. To do. This enable signal is input as a phase comparison target of the aforementioned PLL circuit.

  The enable signal generation circuit 12 is a circuit that outputs a signal sequence in response to an input of a line clock, and a signal for C / L in the output signal sequence is, for example, a signal having a value of “+1” (Enable signal), and others are signals having a value of “0”. The enable signal generation circuit 12 enables C / L of the line clock signal based on the amount C of client data supplied from the demapping processing circuit 10 and the amount L of line data in which client data is framed. Output as a signal (effective clock).

  The client clock generation circuit 20 is, for example, a voltage controlled crystal oscillator (VCXO), and is a circuit that generates a client clock signal.

  The frequency-divided clock generation circuit 22 includes a register that counts 386, for example, and outputs a frequency-divided clock every 386 clocks of the client clock signal. In this example, the line clock (OTU3) frequency in the LSI is about 168 MHz, the client clock (STM-64) frequency is about 155 MHz, and the divided clock frequency is about 402 kHz. The divided clock generation circuit 22 divides the client clock signal into a fixed number of divisions (fixed division) in that one divided clock is output in response to input of 386 client clocks. Circuit.

  The frequency-divided clock generation circuit 14 is a circuit that fixedly divides the line clock during an enable period (for example, a period in which the enable signal is at a high level) of the enable signal generated by the enable signal generation circuit 12. The divided clock generation circuit 14 may be the same as the divided clock generation circuit 22.

  The phase comparison circuit 24 is a circuit that detects a phase difference between the divided client clock signal and the divided line clock signal and outputs a phase difference signal corresponding to the phase difference.

  The smoothing circuit 26 smoothes the phase difference signal and outputs it to the client clock generation circuit 20. The client clock signal generated by the client clock generation circuit 20 is adjusted and stabilized based on the signal from the smoothing circuit 26.

  However, in the client clock generation in the conventional separating apparatus on the receiving side, the line clock signal during the enable period is fixedly divided by the divided clock generation circuit 14, and the client clock signal is also fixedly divided by the divided clock generation circuit 22. The phases of the clocks that have been rotated and fixedly divided by the phase comparator 24 are compared. For this reason, when the types of the client signals are different, there is a problem that it is necessary to configure the PLL by setting the LPF parameter and the phase comparison parameter corresponding to the frequency of the clock of each client signal.

  In order to achieve the above object, the present invention provides a data amount C transmitted in a multi-layered frame format in a plurality of hierarchical frames in line data having a data amount L. A clock regenerator for regenerating a clock signal of client data, a client clock generating means (20) for generating a client clock signal, and a frequency-divided clock obtained by multiplying the frequency of the client clock signal by L / C equivalently And an enable signal generating means (12) for generating an enable signal by inputting a line clock signal, the data amount L of the line data, and the data amount C of the client data. And the frequency of the line clock signal during the enable period of the enable signal cycle is equivalently Second means (30, 34) for generating a divided clock of a signal multiplied by / C, a divided clock generated by the first means, and a divided clock generated by the second means A phase comparison means (24) for outputting a phase difference signal corresponding to the phase difference and a smoothing means (26) for smoothing the phase difference signal and outputting it to the client clock generation means are provided. .

  According to a second aspect of the present invention, there is provided the clock recovery device according to the first aspect, wherein the first means obtains a clock equivalent to L / C times the frequency of the client clock signal. A correction unit; and a first fixed frequency dividing unit that fixedly divides the output of the first correction unit, and the second unit is configured to detect the line clock signal during the enable period of the enable signal cycle. And a second correction unit that obtains a signal equivalently L / C times the frequency, and a second fixed frequency dividing unit that fixedly divides the output of the second correction unit. And the second correction means are the same, and the first fixed frequency dividing means and the second fixed frequency dividing means are the same.

  A third aspect of the present invention is the clock recovery device according to the second aspect, wherein the first correction unit and the second correction unit are enabled periods of the period of the client clock signal or the enable signal. A means for adding the difference value between the data amount L and the data amount C for each effective clock, and determining whether the added value obtained by the adding means is less than the data amount C or more than the data amount C. When it is determined that the addition value is less than the data amount C, the count unit that counts and outputs one clock when the addition value is less than the data amount C; Subtracting counting means for counting and outputting two clocks as a new added value obtained by subtracting the data amount C from the added value is provided.

  According to a fourth aspect of the present invention, in the clock recovery device, a clock for recovering a clock signal of client data of a data amount C transmitted in a multi-layered frame format with a plurality of hierarchical frames in line data of a data amount L In the reproduction method, the client clock signal is generated by the client clock generation means (20) and the frequency of the client clock signal is equivalently reduced to L by the first divided clock generation means (32, 36). / C times the frequency-divided clock, and the enable signal generating means (12) receives the line clock signal, the data amount L of the line data, and the data amount C of the client data as an input signal. And the second divided clock generation means (30, 34) When the divided clock of the signal obtained by equivalently multiplying the frequency of the line clock signal during the enable period of the enable signal cycle by L / C is generated, the first divided clock is generated by the phase comparison means (24). Outputting a phase difference signal corresponding to the phase difference between the divided clock generated by the means and the divided clock generated by the second divided clock generating means, and by the smoothing means (26), And smoothing the phase difference signal and outputting it to the client clock generation means.

  The invention according to claim 5 is the clock recovery method according to claim 4, wherein the first frequency-divided clock generation means includes a first correction means and a first fixed frequency-dividing means, The second frequency-divided clock generation means includes second correction means and second fixed frequency-dividing means, and the method uses the first correction means to equalize the frequency of the client clock signal. Obtaining a clock multiplied by L / C, fixedly dividing the output of the first correction means by the first fixed frequency dividing means, and the period of the enable signal by the second correction means Obtaining a signal obtained by equivalently multiplying the frequency of the line clock signal during the enable period by L / C, and fixedly dividing the output of the second correcting means by the second fixed dividing means. It is characterized by including.

  A sixth aspect of the present invention is the clock recovery method according to the fifth aspect, wherein each of the first correction unit and the second correction unit includes an addition unit, a determination unit, a count unit, and a subtraction count. The method includes adding a difference value between the data amount L and the data amount C for each effective clock during an enable period of the period of the client clock signal or the enable signal by each of the adding units. Each of the determination means determines whether the addition value obtained by the corresponding addition means is less than the data amount C or more than the data amount C, and each of the count means determines the addition value. Is determined to be less than the data amount C, one clock is counted and output, and each of the subtraction counting means sets the added value to the data. If it is determined that the amount C or more, a value obtained by subtracting the data amount C from the addition value as a new added value, characterized in that it comprises and outputting by counting the two clocks.

  As described above, according to the present invention, a plurality of client signals (e.g., OTU4, 112 Gbps) are processed in a high-speed transmission signal (e.g., OTU4, 112 Gbps) framed in multiple layers by a common PLL configuration. A clock signal corresponding to 10 Gbps SONET / SDH / 10 GbE) can be reproduced. That is, even if the types of client signals are different, it is not necessary to set the LPF parameter and the phase comparison parameter corresponding to the frequency of each client signal and configure each PLL. Further, by using an L / C correction circuit that can change L and C of the L / C correction circuit, it can be shared by one PLL configuration, and various client signals with different speeds can be accommodated.

It is a figure for demonstrating the structure of the clock reproducing | regenerating apparatus concerning one Embodiment of this invention. It is a figure for demonstrating operation | movement of the correction circuit concerning one Embodiment of this invention, (a) is the enable signal production | generation period EC, (b) is the enable signal EN, (c) is count value CT0, (D) is an addition value AD1, and (e) is a diagram showing a count value CT1 when corrected. It is a figure for demonstrating the structure of a clock reproduction apparatus.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The same symbols indicate the same elements. Therefore, the overlapping description is omitted.

  FIG. 1 is a diagram for explaining the configuration of a clock recovery device 40 according to an embodiment of the present invention. 1 includes a client clock generation circuit 20 that generates a client clock signal, a divided clock generation circuit 36 that generates a divided clock of the generated client clock, and an enable signal generation that generates an enable signal. The circuit 12, the frequency-divided clock generation circuit 34 that generates the frequency-divided clock of the line clock during the enable period of the enable signal cycle (for example, the period in which the enable signal is high level), and the phase difference between the two frequency-divided clocks A phase comparison circuit 24 that detects and outputs a phase difference signal corresponding to the phase difference, and a smoothing circuit (LPF) 26 that smoothes the phase difference signal and outputs it to the client clock generation circuit 20 are provided. The clock recovery device 40 of FIG. 1 includes an L / C correction circuit 30 between the enable signal generation circuit 12 and the divided clock generation circuit 34. An L / C correction circuit 32 is provided between the client clock generation circuit 20 and the divided clock generation circuit 36. The two L / C correction circuits (30, 32) may be the same.

  The L / C correction circuit (30, 32) includes an addition circuit and a determination circuit (both not shown).

  The specified value of the data amount of the line data is L ′, and the specified value of the data amount of the client data is C ′. The adder circuit of the L / C correction circuit 30 calculates (L′−C ′) for each effective clock during the enable period (for example, the period in which the enable signal is high level) of the enable signal from the enable signal generation circuit 12. to add. The determination circuit of the L / C correction circuit 30 determines whether the addition value of the addition circuit is less than C ′ or greater than C ′.

  When it is determined that the added value is less than C ′, the L / C correction circuit 30 outputs a control signal for counting one clock of the above-mentioned effective clock as “+1” clocks to the divided clock generation circuit 34. When it is determined that the added value is equal to or greater than C ′, a value obtained by subtracting C ′ from the added value is used as a new added value, and a control signal for counting one clock of the above-described effective clock as “+2” clocks is divided. Output to the clock generation circuit 34. The L / C correction circuit 30 outputs “0” to the divided clock generation circuit 34 when the signal from the enable signal generation circuit 12 is not an enable signal (in the case of a disable signal).

  Similarly, the addition circuit of the L / C correction circuit 32 adds (L′−C ′) for each client clock (for example, a signal having a value “+1” clock) from the client clock generation circuit 20. The determination circuit of the L / C correction circuit 32 determines whether the addition value of the addition circuit is less than C ′ or greater than C ′.

  When it is determined that the addition value is less than C ′, the L / C correction circuit 32 outputs a control signal for counting one client clock as “+1” clocks to the divided clock generation circuit 36, and the addition value is C When it is determined that the value is equal to or greater than this, a value obtained by subtracting C from the added value is set as a new added value, and a control signal for counting one client clock as “+2” clocks is output to the divided clock generation circuit 36.

  The frequency-divided clock generation circuit 34 counts the value “0”, “+1” or “+2” input from the L / C correction circuit 30 as the number of clocks, and divides the line clock during the enable period of the enable signal cycle. The frequency-divided clock is output to the phase comparator 24. For example, in the example shown in FIG. 1, the frequency-divided clock generation circuit 34 includes a register that counts 386, and advances the counter according to the value (control signal) input from the L / C correction circuit 30 every 386 clocks. Output one divided clock. Therefore, the divided clock generation circuit 34 counts one clock when the input is “+1”, counts two clocks when the input is “+2”, and counts when the input is “0”. do not do.

  Similarly, the divided clock generation circuit 36 counts the value “0”, “+1”, or “+2” input from the L / C correction circuit 32 as the number of clocks, and divides the client clock signal. Is output to the phase comparator 24.

  Next, the operation of the correction circuit will be described with specific numerical values. When L ′ = 3 and C ′ = 2, the cycle timing of the enable signal generation cycle EC (FIG. 2A) is “1, 2, 3”, and the enable signal EN is shown in FIG. To be generated. In the case of FIG. 3 without the LC correction circuit, the clock is counted when the enable signal EN is “H”, and the count value CT0 (FIG. 2C) is repeatedly counted in the order of “1, 2”.

  Next, in the case of FIG. 1 to which the correction circuit 30 is added, the addition value AD1 is equal to L′−C in the EC period 1 (the signal period corresponding to 1 in FIG. 2A) because the enable signal EN is “H”. '= 1 is added, and the added value AD1 becomes 1 (FIG. 2 (d) (1)). Since it is determined that the added value AD1 is less than C ′ = 2, the added value AD1 is the value as it is (FIGS. 2D and 2), and the counter CT1 counts one clock (FIG. 2E). In the next EC period 2, since the enable signal EN is “H”, L′−C ′ = 1 is further added, and the added value AD1 becomes 2 (FIGS. 2D and 1). Here, since it is determined that the added value AD1 is equal to or greater than C ′ = 2, the final added value AD1 is reduced by 2 to 0 (FIGS. 2D and 2). In this case, since two clocks are counted, the value of the counter CT1 is 3 ((3) in FIG. 2). Next, since the enable signal is “L” in EC3 at the end of the cycle, the addition operation is not performed. As described above, the clock count value is L '/ C' = 3/2 times that when no correction circuit is provided. That is, it can be seen that the frequency is equivalently L '/ C' = 3/2 times. Similarly, the frequency of the client clock signal correction circuit 32 is L '/ C' = 3/2 times equivalently.

  Therefore, the L / C correction circuit (30, 32) can be said to be a circuit that controls the operation speed of the divided clock generation circuit (34, 36) according to the amount C of client data with respect to the amount L of line data. . Alternatively, the L / C correction circuit (30, 32) determines the frequency of dividing the clock signal input to the frequency-divided clock generation circuit (34, 36) as the amount of client data with respect to the amount L of line data. It can also be said to be a circuit controlled according to C.

  The L / C correction circuit 30 increases (LC) clock signals for every C line clocks during the enable period of the enable signal cycle. As a result, the divided clock generation circuit 34 counts L clocks every period of the enable signal. Therefore, the L / C correction circuit 30 and the divided clock generation circuit 34 are corrected so as to multiply the line clock signal by L / C at the point of generating the divided clock of the line clock during the enable period of the enable signal cycle. It can also be said to be a circuit.

  As described above, the L / C correction circuit of the present invention makes it possible to share the PLL LPF parameters and phase comparison parameters even when the types of client signals are different (the frequencies of the client signals are different). Further, by using an L / C correction circuit that can change L and C of the L / C correction circuit, it can be shared by one PLL configuration, and various client signals with different speeds can be accommodated.

DESCRIPTION OF SYMBOLS 10 Demapping processing circuit 12 Enable signal generation circuit 14 Frequency division clock generation circuit 20 Client clock generation circuit 22 Frequency division clock generation circuit (client clock frequency division circuit)
24 Phase comparison circuit 26 Low-pass filter (smoothing circuit)
30 Correction circuit (enable signal)
32 Correction circuit (client clock signal)
34 divided clock generation circuit 36 divided clock generation circuit (client clock division circuit)
40 clock recovery device 50 clock recovery device

In order to achieve the above object, the present invention provides a data amount C transmitted in a multi-layered frame format in a plurality of hierarchical frames in line data having a data amount L. A clock regenerator that regenerates a clock signal of client data, and generates a client clock generating means (20) for generating a client clock signal and a frequency-divided clock by multiplying the frequency of the client clock signal by L / C. A first means (32, 36); an enable signal generating means (12) for generating an enable signal by inputting a line clock signal, the data amount L of the line data, and the data amount C of the client data; Shin the frequency of the line clock signal in the enable period of the period of the enable signal is L / C times According to the phase difference between the second clock (30, 34) for generating the divided clock and the divided clock generated by the first means and the divided clock generated by the second means. A phase comparison means (24) for outputting a phase difference signal and a smoothing means (26) for smoothing the phase difference signal and outputting it to the client clock generation means are provided.

The invention according to claim 2 is the clock recovery apparatus according to claim 1, wherein the first means includes first correction means for obtaining a clock obtained by multiplying the frequency of the client clock signal by L / C. And a first fixed frequency dividing means for fixedly dividing the output of the first correction means, wherein the second means sets the frequency of the line clock signal during the enable period of the period of the enable signal to L Second correction means for obtaining a signal multiplied by / C, and second fixed frequency dividing means for fixedly dividing the output of the second correction means, and the first correction means and the second correction frequency dividing means. The correction means is the same, and the first fixed frequency dividing means and the second fixed frequency dividing means are the same.

According to a fourth aspect of the present invention, in the clock recovery device, a clock for recovering a clock signal of client data of a data amount C transmitted in a multi-layered frame format with a plurality of hierarchical frames in line data of a data amount L In the reproduction method, the client clock signal is generated by the client clock generation means (20), and the frequency of the client clock signal is multiplied by L / C times by the first divided clock generation means (32, 36). And generating an enable signal by inputting the line clock signal, the data amount L of the line data, and the data amount C of the client data by the enable signal generating means (12). And the second divided clock generation means (30, 34) When the frequency-divided clock of the signal obtained by multiplying the frequency of the line clock signal during the enable period of the enable signal cycle by L / C is generated, the signal is generated by the first frequency-divided clock generating means by the phase comparing means (24). A phase difference signal corresponding to the phase difference between the frequency-divided clock and the frequency-divided clock generated by the second frequency-divided clock generation means is output, and the phase difference signal is smoothed by the smoothing means (26). And outputting to the client clock generation means.

The invention according to claim 5 is the clock recovery method according to claim 4, wherein the first frequency-divided clock generation means includes a first correction means and a first fixed frequency-dividing means, The second frequency-divided clock generating means includes second correction means and second fixed frequency-dividing means, and the method uses the first correction means to change the frequency of the client clock signal to L / C. Obtaining a multiplied clock, fixing the frequency of the output of the first correcting means by the first fixed frequency dividing means, and enabling period of the enable signal by the second correcting means. And obtaining a signal obtained by multiplying the frequency of the internal line clock signal by L / C, and dividing the output of the second correction means by the second fixed dividing means. To do.

Next, in the case of FIG. 1 to which the correction circuit 30 is added, the addition value AD1 is equal to L′−C in the EC period 1 (the signal period corresponding to 1 in FIG. 2A) because the enable signal EN is “H”. '= 1 is added, and the added value AD1 becomes 1 (FIG. 2 (d) (1)). Since it is determined that the addition value AD1 is less than C ′ = 2, the addition value AD1 is a value as it is (FIGS. 2D and 2), and the counter CT1 counts one clock (FIG. 2E). In the next EC period 2, since the enable signal EN is “H”, L′−C ′ = 1 is further added, and the added value AD1 becomes 2 (FIGS. 2D and 1). Here, since it is determined that the added value AD1 is equal to or greater than C ′ = 2, the final added value AD1 is reduced by 2 to 0 (FIGS. 2D and 2). In this case, since two clocks are counted, the value of the counter CT1 is 3 ((3) in FIG. 2). Next, since the enable signal is “L” in EC3 at the end of the cycle, the addition operation is not performed. As described above, the clock count value is L ′ / C ′ = 3/2 times that in the case where there is no correction circuit. It can be seen that Sunawa Chi frequency is in the L '/ C' = 3/ 2 -fold. Correction circuit of a client clock signal 32 is similarly frequency is L '/ C' = 3/ 2 -fold to become.

Claims (6)

A clock recovery device for recovering a clock signal of client data of data amount C transmitted in a multi-layered frame format in line data of data amount L,
Client clock generation means (20) for generating a client clock signal;
First means (32, 36) for generating a divided clock of a clock obtained by equivalently multiplying the frequency of the client clock signal by L / C;
Enable signal generating means (12) for generating an enable signal by inputting a line clock signal, the data amount L of the line data, and the data amount C of the client data;
Second means (30, 34) for generating a frequency-divided clock of a signal that is equivalent to L / C times the frequency of the line clock signal during the enable period of the enable signal cycle;
Phase comparison means (24) for outputting a phase difference signal corresponding to the phase difference between the frequency-divided clock generated by the first means and the frequency-divided clock generated by the second means;
A clock recovery apparatus comprising: smoothing means (26) for smoothing the phase difference signal and outputting the smoothed signal to the client clock generation means. The first means includes first correction means for obtaining a clock obtained by equivalently multiplying the frequency of the client clock signal by L / C, and a first fixed division for fixedly dividing the output of the first correction means. A circumferential means,
The second means includes second correction means for obtaining a signal equivalently L / C times the frequency of the line clock signal during the enable period of the enable signal cycle, and the output of the second correction means. Second fixed frequency dividing means for fixed frequency division,
The first correction unit and the second correction unit are the same,
2. The clock recovery apparatus according to claim 1, wherein the first fixed frequency dividing unit and the second fixed frequency dividing unit are the same. The first correction unit and the second correction unit are:
Means for adding a difference value between the data amount L and the data amount C for each effective clock in the enable period of the cycle of the client clock signal or the enable signal;
Determining means for determining whether the added value obtained by the adding means is less than the data amount C or more than the data amount C;
Counting means for counting and outputting one clock when the added value is determined to be less than the data amount C;
Subtraction counting means for counting and outputting two clocks as a new addition value obtained by subtracting the data amount C from the addition value when the addition value is determined to be greater than or equal to the data amount C. The clock recovery device according to claim 2. In a clock recovery device, a clock recovery method for recovering a clock signal of client data of data amount C transmitted in a multi-layered frame format in line data of data amount L, wherein
Generating a client clock signal by client clock generation means (20);
Generating a divided clock of a clock obtained by equivalently multiplying the frequency of the client clock signal by L / C by first divided clock generation means (32, 36);
An enable signal generating means (12) for generating an enable signal by inputting a line clock signal, the data amount L of the line data, and the data amount C of the client data;
When the second divided clock generating means (30, 34) generates a divided clock of a signal that is equivalent to L / C times the frequency of the line clock signal during the enable period of the enable signal cycle,
A phase difference according to the phase difference between the divided clock generated by the first divided clock generating means and the divided clock generated by the second divided clock generating means by the phase comparing means (24). Outputting a signal;
A clock recovery method comprising: smoothing the phase difference signal by a smoothing means (26) and outputting the smoothed signal to the client clock generating means. The first frequency-divided clock generating means has a first correcting means and a first fixed frequency dividing means,
The second frequency-divided clock generating means has second correction means and second fixed frequency dividing means,
The method
Obtaining a clock equivalent to L / C times the frequency of the client clock signal by the first correction means;
Fixedly dividing the output of the first correcting means by the first fixed dividing means;
Obtaining a signal equivalent to L / C times the frequency of the line clock signal during the enable period of the enable signal cycle by the second correction means;
The clock recovery method according to claim 4, further comprising: fixedly dividing the output of the second correction unit by the second fixed dividing unit. Each of the first correction unit and the second correction unit includes an addition unit, a determination unit, a count unit, and a subtraction count unit.
The method
Adding a difference value between the data amount L and the data amount C for each effective clock during an enable period of the period of the client clock signal or the enable signal by each of the adding means;
Each of the determination means determines whether the addition value obtained by the corresponding addition means is less than the data amount C or more than the data amount C;
When each of the counting means determines that the added value is less than the data amount C, it counts and outputs one clock;
When each of the subtraction counting means determines that the addition value is greater than or equal to the data amount C, a value obtained by subtracting the data amount C from the addition value is used as a new addition value, and two clocks are counted. The clock recovery method according to claim 5, further comprising: outputting.

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