JP4886813B2 - Digital signal processing circuit - Google Patents

Description

  The present invention relates to a digital signal processing circuit.

It is desired to increase the capacity of an optical transmission system, and it is necessary to increase the transmission capacity while maintaining the transmission distance of the conventional system. Currently, the transmittable bandwidth of an optical fiber is used almost to the limit, and a transmission method with high frequency utilization efficiency that can transmit more information in the same transmission bandwidth is desired.
The polarization multiplexing method is a promising method that can double the frequency utilization efficiency. Since the polarization rotates at the reception end during optical fiber transmission, there is a method of performing polarization separation using digital signal processing as a method of separating the polarization at the reception end. There, it is possible to separate two multiplexed polarization components by synthesizing two orthogonal components received using a FIR (Finite Impulse Response) filter (Non-Patent Document 1). 2). The FIR filter also plays a role of compensating for signal distortion factors such as residual components of chromatic dispersion, carrier phase shift, and polarization mode dispersion. As a method for estimating the optimum tap coefficient of the FIR filter, there are a blind estimation method and a method using a known signal. In the estimation method using the known signal, the filter tap coefficient is estimated using an algorithm such as LMS (Least Mean Square) so that the error between the known signal and the received signal is minimized.

H. Masuda, 13 others, “No-Guard-Interval Coherent OFDM Transmission over 6,248km using SNR Maximized Second-order DRA in the Extended L-band”, [online], Optical Society of America, [May 2009 12 days search], Internet <URL: http://www.opticsinfobase.org/abstract.cfm?URI=NFOEC-2009-PDPB5> Jianjun Yu, 2 others, “Polarization insensitive wavelength conversion for 4 × 112 Gbit / s polarization multiplexing RZ-QPSK signals”, [online], Optical Society of America, [Search May 12, 2009], Internet <URL: http://www.opticsinfobase.org/oe/abstract.cfm?uri=oe-16-26-21161>

By the way, in the optical communication, separate lasers are used on the transmission side and the reception side, and the two lasers operate independently of each other. Although the oscillation frequency of the laser is controlled, the frequency has a deviation of about several GHz and fluctuates with time. The laser oscillation frequency may hop due to resonance mode competition or the like. There is also a method of intentionally dithering for frequency control. Thus, the carrier frequency / phase varies with time at high speed. Also, sudden fluctuations in polarization are assumed.
However, the conventional technique has a drawback in that the update of the tap coefficient of the FIR filter cannot follow the high-speed carrier frequency / phase fluctuation and polarization fluctuation, and the signal quality is lowered. .

  The present invention has been made in view of the above points, and an object of the present invention is to allow the update of the tap coefficient of the FIR filter to follow high-speed carrier frequency / phase fluctuation and polarization fluctuation, thereby improving the signal quality. It is an object of the present invention to provide a digital signal processing circuit that can improve the performance.

The present invention has been made to solve the above problems, and the present invention is a digital signal processing circuit in a receiver used in an optical fiber transmission system, wherein the digital signal processing circuit emits local light. The received signal light is separated into orthogonal components and coherently received, the time waveform of the orthogonal components is input, the received data is demodulated using digital arithmetic, and is included in the received signal Prepare a frame synchronization clock unit that outputs a frame synchronization clock that is synchronized with the arrival time timing of the known pattern part, and a signal with a different amount of delay applied to the received signal, and multiply each delayed signal by a tap coefficient. The adaptive equalization filter to be added, the output pattern after equalization output from the adaptive equalization filter, and the reception unit stored in the The adaptive equalization is performed so that a subtractor that compares patterns and calculates an error thereof, and operates in a known pattern portion by using the frame synchronization clock, and an error amount output from the subtractor is minimized. An adaptive equalization tap coefficient control unit that controls the tap coefficient of the filter, and uses two different patterns as the known pattern, and the adaptive equalization tap coefficient control unit includes two polarizations included in the received signal It operates in cooperation with the output, and the error amount between one of the two polarization outputs and one of the two different patterns, and the other of the two polarization outputs and the 2 one of which is a digital signal processing circuit error amount and said users update the tap coefficient so as to minimize the other one of different patterns.

The present invention is also a digital signal processing circuit in a receiver used in an optical fiber transmission system, wherein the digital signal processing circuit uses local light to orthogonally cross the optical electric field of input signal light. The received signal is coherently received, the time waveform of the orthogonal component is input, the received data is demodulated using digital calculation, and the frame synchronization clock synchronized with the arrival time timing of the known pattern part included in the received signal is detected A frame synchronization clock unit to output, and an adaptive equalization filter that prepares a signal having a different delay amount to the received signal, multiplies each delayed signal by a tap coefficient, and adds An identification determination unit that inputs data output from the adaptive equalization filter and outputs a pattern after digital determination; and the frame synchronization clock When a known pattern of the received signal arrives, a known pattern stored in the receiving unit is output as a target pattern, and a determination output from the identification determining unit at other time portions. A switch unit that outputs a post-pattern as a target pattern; a subtractor that calculates an error between an equalized output pattern output from the adaptive equalization filter and a target pattern output from the switch unit; and the subtraction An adaptive equalization tap coefficient control unit that controls tap coefficients of the adaptive equalization filter so that an error amount output from the detector is minimized, and using two different patterns as the known pattern, The equalization tap coefficient control unit operates in cooperation with the two polarization outputs included in the received signal, and performs either one of the two polarization outputs or the previous one. The tap coefficient is updated so that the error amount between one of the two different patterns and the error amount between the other of the two polarization outputs and the other of the two different patterns are minimized. a digital signal processing circuit according to claim to Rukoto.

The present invention is also a digital signal processing circuit in a receiver used in an optical fiber transmission system, wherein the digital signal processing circuit uses local light to orthogonally cross the optical electric field of input signal light. The received signal is coherently received, the time waveform of the orthogonal component is input, the received data is demodulated using digital calculation, and the frame synchronization clock synchronized with the arrival time timing of the known pattern part included in the received signal is detected A frame synchronization clock unit to output, and an adaptive equalization filter that prepares a signal having a different delay amount to the received signal, multiplies each delayed signal by a tap coefficient, and adds An identification determination unit that inputs data output from the adaptive equalization filter and outputs a pattern after digital determination; and the adaptive equalization filter A first subtractor for calculating an error between the output pattern after equalization output from and a known pattern stored in the receiver, and an output pattern after equalization output from the adaptive equalization filter, By using the second subtractor that calculates an error from the post-determination pattern output from the identification determination unit and the frame synchronization clock, the first subtraction is performed in the time portion where the known pattern of the received signal arrives The adaptive equalization filter so that the error amount output from the switch unit is minimized, and the switch unit that outputs the error output from the second subtractor in the other time portion, and the error amount output from the switch unit comprising of an adaptive equalization tap coefficient control unit for controlling the tap coefficients, and using two different patterns as the known pattern, the adaptive equalization tap coefficient control unit 2 included in the received signal Which operates in cooperation with the polarization output of the two, the error amount between one of the two polarization outputs and one of the two different patterns, and the other of the two polarization outputs and a digital signal processing circuit error amount and said users update the tap coefficient so as to minimize the other one of said two different patterns.

  In addition, the present invention provides the above-described digital signal processing circuit, in which a signal with a different delay amount is prepared for the received signal, and a tap coefficient is added to each delayed signal and added. Output from the equalization filter, an output pattern after equalization output from the adaptive equalization filter, and a target pattern such as a known pattern stored in the receiver, and output from the subtractor An adaptive equalization tap coefficient control unit for controlling the tap coefficient of the adaptive equalization filter, and a frequency for correcting the frequency shift of the received signal input to the adaptive equalization filter so that the error amount is minimized. The carrier frequency difference between the local light and the transmission signal is calculated from the tap coefficient output from the compensation unit and the adaptive equalization tap coefficient control unit, and the frequency compensation amount given by the frequency compensation unit is calculated Characterized in that it comprises a wavenumber offset amount calculating section.

  In addition, the present invention provides the above-described digital signal processing circuit, in which a signal with a different delay amount is prepared for the received signal, and a tap coefficient is added to each delayed signal and added. Output from the equalization filter, an output pattern after equalization output from the adaptive equalization filter, and a target pattern such as a known pattern stored in the receiver, and output from the subtractor An adaptive equalization tap coefficient control unit for controlling the tap coefficient of the adaptive equalization filter, and a frequency for correcting the frequency shift of the received signal input to the adaptive equalization filter so that the error amount is minimized. Compensating unit, comparing the target pattern with the adaptive equalization filter output, calculating the error, and using the tap coefficient and the input signal of the frequency compensating unit, the frequency is such that the error is minimized. A frequency compensation amount controller for controlling the 償量, characterized in that it comprises a.

  In addition, the present invention provides the above-described digital signal processing circuit, in which a signal with a different delay amount is prepared for the received signal, and a tap coefficient is added to each delayed signal and added. Output from the equalization filter, an output pattern after equalization output from the adaptive equalization filter, and a target pattern such as a known pattern stored in the receiver, and output from the subtractor An adaptive equalization tap coefficient control unit for controlling the tap coefficient of the adaptive equalization filter, and a frequency for correcting the frequency shift of the received signal input to the adaptive equalization filter so that the error amount is minimized. A compensation unit, a carrier phase estimation unit for estimating a phase shift amount of the local light and the transmission laser from the adaptive equalization filter output pattern, and a time of the phase shift amount output from the carrier phase estimation unit The frequency deviation amount between the local light and the transmitted laser light is calculated from the calculation, and the frequency compensation amount control unit that controls the compensation amount of the frequency compensation unit so that the deviation is reduced, and is output from the carrier phase estimation unit And a phase compensation unit that compensates the phase of the output signal from the adaptive equalization filter using a phase shift amount.

According to the present invention, the digital signal processing circuit calculates the error by comparing the equalized output pattern output from the FIR filter and the known pattern stored in the receiving unit, and the error amount is minimized. Since the tap coefficient of the FIR filter is updated as described above, the update of the tap coefficient of the FIR filter can follow the high-speed carrier frequency / phase fluctuation and polarization fluctuation, and the signal quality can be improved.
Further, according to the present invention, the digital signal processing circuit outputs the known pattern stored in the receiving unit as the target pattern in the time portion when the known pattern of the received signal arrives, and identifies in the other time portion. The post-determination pattern output from the determination unit is output as a target pattern, and the tap coefficient of the FIR filter is updated so that the error amount between the equalized output pattern and the target pattern is minimized. Accordingly, the digital signal processing circuit can follow the FIR tap coefficient without frequently inserting a known pattern into the received signal, and can improve the signal quality. Further, it is possible to prevent a known pattern from being frequently inserted into a signal to reduce a payload portion and to deteriorate data transmission efficiency. Furthermore, even when the received signal gradually changes due to a time fluctuation factor, the FIR tap coefficient can follow the fluctuation, and the signal quality can be improved.
Further, according to the present invention, the digital signal processing circuit estimates the phase shift amount between the local light and the transmission laser from the FIR filter output pattern, and calculates the frequency shift amount between the local light and the transmission laser light from the time change of the phase shift amount. The compensation amount of the frequency compensator is controlled so that the deviation is reduced. As a result, the digital signal processing circuit follows the phase rotation and sets the FIR tap coefficient even when there is a time change in the frequency difference and phase difference between the laser light at the transmitting end and the local light at the receiving end. It is possible to follow, and the signal quality can be improved.
According to the present invention, the digital signal processing circuit calculates the frequency compensation amount by calculating the carrier frequency difference between the local light and the transmission signal from the FIR tap coefficient or the phase rotation amount, and based on the calculated frequency compensation amount. The frequency shift of the received signal input to the FIR filter is corrected. Thereby, even if there is a frequency difference between the laser light at the transmitting end and the local light at the receiving end, the digital signal processing circuit can follow the FIR tap coefficient by compensating for the frequency shift. Quality can be improved.

1 is a schematic block diagram showing a digital signal processing circuit according to a first embodiment of the present invention. It is another schematic block diagram which shows the digital signal processing circuit which concerns on this embodiment. It is the schematic which shows an example of the frame synchronous clock extraction which concerns on this embodiment. It is a schematic block diagram which shows the structure of the digital signal processing circuit which concerns on the 2nd Embodiment of this invention. It is a schematic block diagram which shows the structure of the digital signal processing circuit which concerns on the modification of this embodiment. It is the schematic which shows switching by the switch part which concerns on this embodiment. It is a schematic block diagram which shows the structure of the digital signal processing circuit which concerns on the 3rd Embodiment of this invention. It is a schematic block diagram which shows the structure of the digital signal processing circuit which concerns on the modification 1 of this embodiment. It is a schematic block diagram which shows the structure of the digital signal processing circuit which concerns on the modification 2 of this embodiment. It is the schematic which shows the experimental evaluation of the effect by phase compensation. It is the schematic which shows the relationship between a LMS convergence coefficient and Q value. It is the schematic which shows an example of the experimental evaluation result of frame size dependence. It is a schematic block diagram which shows the structure of the digital signal processing circuit which concerns on the modification 3 of this embodiment. It is a schematic block diagram which shows the structure of the digital signal processing circuit which concerns on the modification 4 of this embodiment. It is the schematic which shows another example of the experimental evaluation result of frame size dependence. It is a schematic block diagram which shows the structure of the digital signal processing circuit which concerns on the modification 5 of this embodiment. It is a schematic block diagram which shows the structure of the digital signal processing circuit which concerns on the 4th Embodiment of this invention. It is a schematic block diagram which shows the structure of the frequency offset amount calculation part which concerns on this embodiment. It is a schematic block diagram which shows the structure of the digital signal processing circuit which concerns on the modification 1 of this embodiment. It is the schematic which shows another example of the experimental evaluation result of frame size dependence. It is a schematic block diagram which shows the structure of the digital signal processing circuit which concerns on the modification 2 of this embodiment. It is a schematic block diagram which shows the structure of the digital signal processing circuit which concerns on the modification 3 of this embodiment. It is a schematic block diagram which shows the structure of the digital signal processing circuit which concerns on the 5th Embodiment of this invention. It is a schematic block diagram which shows the structure of the digital signal processing circuit which concerns on the 6th Embodiment of this invention. It is a schematic block diagram which shows the structure of the digital signal processing circuit which concerns on the modification 1 of this embodiment. It is a schematic block diagram which shows the structure of the digital signal processing circuit which concerns on the modification 2 of this embodiment. It is a schematic block diagram which shows the structure of the digital signal processing circuit which concerns on the modification 3 of this embodiment.

(First embodiment)
Hereinafter, a first embodiment of the present invention will be described in detail with reference to the drawings.
In the receiving end that performs optical fiber transmission, when coherently receiving polarization multiplexed signal light using local light, a time waveform of two components of orthogonal polarization, X polarization, and Y polarization is obtained. Furthermore, since the signal is transmitted on an optical carrier wave, it is given as its wave, so it has two components that are orthogonal, and the most common orthogonal separation method is the same phase component and orthogonal phase component as local light. There is a way to separate. Therefore, four orthogonal components are input to the digital signal processing unit. Since the orthogonal in-phase component and the orthogonal phase component can be expressed as a single numerical value by using complex numbers, the in-phase components and the orthogonal phase components are combined and expressed as complex numbers.

In optical fiber transmission, since it receives the chromatic dispersion of the optical fiber transmission line, the received signal receives a signal whose waveform has deteriorated due to the chromatic dispersion. In general, since time spread due to wavelength dispersion is large, an FIR filter having a large number of taps is used for this compensation. Here, the signal after compensating for chromatic dispersion is targeted.
The polarization multiplexed signal light is transmitted with separate data on the two polarizations using the degree of freedom of polarization of the optical signal. However, in the optical fiber transmission line, since the polarization rotates randomly, one orthogonal polarization component detected at the receiving end is detected as a mixture of two orthogonal polarization components at the transmitting end. The For this reason, it is necessary to estimate two orthogonal components transmitted at the transmitting end from the two components detected at the receiving end, which can be separated by using an FIR filter. Therefore, it is necessary to accurately estimate the tap coefficient of the FIR filter (referred to as FIR tap coefficient), and a configuration for estimating the FIR tap coefficient using a known signal will be described as the method.

  The transmission / reception signal is composed of a part in which a known pattern is inserted and a payload part in which transmitted data is inserted, and a combination of the two parts is called a frame. In general, the payload portion occupies a large proportion of the frame in order to increase the data transfer efficiency of the client signal. It is assumed that the known signal portion is inserted at a certain time interval. First, the receiving end estimates a FIR tap coefficient of an optimum FIR filter using a known signal. Therefore, it is necessary to detect and maintain the time timing when the known signal included in the received signal arrives. Here, the time timing when a known signal in a frame arrives is called a frame synchronization clock.

1 and 2 are schematic block diagrams showing a digital signal processing circuit 1 according to the first embodiment of the present invention. The digital signal processing circuit 1 is provided at a receiving end that performs optical fiber transmission.
In FIG. 1, the frame synchronization clock unit 11 outputs a frame synchronization clock synchronized with the arrival time timing of the known pattern portion included in the received signal. The FIR filter 14 (adaptive equalization filter) prepares signals having different delay amounts for received signals, multiplies FIR tap coefficients in the signals subjected to the respective delays, and adds them. The subtractor 12 (subtractor) compares the equalized output pattern output from the FIR filter 14 with the known pattern stored in the receiver, and calculates the error. The FIR tap coefficient control unit 13 (adaptive equalization tap coefficient control unit) operates in the known pattern portion by using the frame synchronization clock, and the FIR filter 14 so that the error amount output from the subtraction unit 12 is minimized. Controls the FIR tap coefficient of. Specifically, the FIR tap coefficient control unit 13 calculates an FIR tap coefficient that minimizes the error amount, and outputs the FIR tap coefficient to the FIR filter 14.
In the FIR filter 14 of FIG. 2, a block in which the character string “T” is described (for example, a block denoted by reference numeral 141; a delay unit) gives a delay to the input received signal. In addition, a block of a figure of ▽ (for example, a block denoted by reference numeral 141; a multiplication unit) multiplies the input signal. A block in which the character string “+” is written (for example, a block denoted by reference numeral 143; an adding unit) indicates that signals are added. The functions of the subtraction unit 12 and the FIR tap coefficient control unit 13 are the same as the functions of the subtraction unit 12 and the FIR tap coefficient control unit 13 of FIG.

In the configuration of FIG. 1, when the frame synchronization clock is input to the FIR filter coefficient control unit 13 and the known pattern portion included in the received signal is compared with the sample known pattern stored at the receiving end, both times The phases are perfectly matched.
FIG. 2 shows an example of a configuration using a transversal type FIR filter that adds weighted components to two input signals given different time delays as the FIR filter 14. The configuration of FIG. 2 is a configuration in which one component of X polarization or Y polarization is extracted from two input components of X polarization and Y polarization. Therefore, such a configuration is required for each polarization output. The FIR tap coefficient control unit 13 may operate in cooperation with the two polarization outputs.
As shown in FIG. 2, it is necessary to individually optimize the tap coefficients of the respective FIR filters for the X polarization reception component and the Y polarization reception component. In optical transmission, since the carrier frequency is very high, such as several hundred THz (terahertz), the phase noise of the carrier is large. In addition, there is a property that carrier phase fluctuations occur due to optical nonlinear effects in the transmission path such as self-phase modulation and cross-phase modulation. In addition, the transmission distance of the optical fiber is long, and the vibration causes the fluctuation of the optical signal through the acoustooptic effect or the like, so that the polarization fluctuation may occur at a high speed. In addition, the 90-degree hybrid used for mixing with local light at the receiving end, imperfect adjustment of the polarization separator, etc., and time fluctuations cause the received signals of the X polarization and Y polarization to have individual phase fluctuations. Sometimes I get it. From the above, the optimization control of the FIR tap coefficient individually for the X polarization and the Y polarization leads to an improvement in reception quality.
Further, in the control of the FIR tap coefficient, there is a feature that the update speed is relatively slow because time averaging is performed. On the other hand, carrier phase fluctuations are characterized by high speed. It is effective to detect the carrier phase fluctuation separately and perform the compensation at high speed. Further, although there is a characteristic that the individual polarization fluctuations of the X polarization component and the Y polarization component of the received signal are received, it is possible to detect the individual phase fluctuations described on the left by using the pilot signal.

First, at the stage of detecting the initial frame synchronization clock, a special transmission data pattern that is easy to detect is transmitted and analyzed at the receiving end to establish the frame synchronization clock. Once frame synchronization is established, maintaining it becomes a challenge.
FIG. 3 is a schematic diagram illustrating an example of frame synchronization clock extraction according to the present embodiment. In this figure, the known signal portion of the signal output from the FIR filter 14 and several symbols before and after it are extracted, and the cross-correlation of the known sample pattern is obtained. Here, when taking the cross-correlation, the frame synchronization clock can be detected and maintained by giving a time lag in symbol units to the both, sweeping, and detecting the peak with the highest correlation. Further, when taking the cross-correlation, the received known pattern and the sample known pattern are subjected to Fourier transform using FFT or the like, and one of them is divided by one. Furthermore, the cross correlation peak can be detected by inverse Fourier transforming the same.

In FIR filter tap coefficient estimation using a known pattern, the FIR tap coefficient can be updated when a known pattern arrives. Therefore, in the configuration of FIG. 3, when a known pattern arrives using the frame synchronization clock, the FIR tap coefficient reflects the error between the known pattern in the received signal and the sample known pattern stored at the receiving end. Update of. At this time, it is necessary to match the time phases of the known sample pattern, the FIR filter output pattern, and the FIR input pattern input to the subtracting unit 12. Since the time phases of the FIR filter input and the FIR filter output are fixed, the time phases are matched by inserting a delay device, a buffer, or the like in the propagation path of each signal in the receiving end digital arithmetic circuit. be able to. You may design so that both time phases may correspond at the time of design. In the time phase of the known pattern, a frame synchronization clock may be provided to the generation unit to generate a pattern synchronized with the generation unit. Further, a time phase may be adjusted by inserting a buffer or the like in the propagation path of the known pattern.
In addition, by setting the time length of the payload part in the frame to an integral multiple of the time length of the known signal part, the FIR filter output pattern, input pattern, You can synchronize the time phase.

The FIR tap coefficient control unit 13 takes an error between the received known pattern and the known pattern stored at the receiving end, and updates the FIR tap coefficient so that the error is minimized. As a specific method, there is a least mean square (LMS) algorithm. In this method, the FIR tap coefficient is changed so that the error gradually decreases, and the optimum FIR tap coefficient is reduced. Specifically, the following numerical calculation is performed. However, the error amounts of the X polarization and Y polarization in the kth symbol are e_x (k), e_y (k), the X polarization and Y polarization FIR filter outputs are X_r, Y_r, and the pilot signal X, respectively. Polarization and Y polarization target signals are respectively X_p, Y_p, X polarization and Y polarization FIR filter inputs are x ^* and y ^* , and FIR filter FIR tap coefficients are H_xx, H_xy, H_yx and H_yy, respectively. Let the coefficient be m.

  The error is represented by e_x (k) = X_p−X_r and e_y (k) = Y_p−Y_r. The update of the FIR tap coefficient is expressed by the following equation (1).

  Therefore, the FIR tap coefficient is updated at the timing when the known signal portion arrives.

  As described above, according to the present embodiment, the digital signal processing circuit 1 compares the output pattern after equalization output from the FIR filter with the known pattern stored in the reception unit, calculates the error, The FIR tap coefficient is updated so that the error amount is minimized. Accordingly, the digital signal processing circuit 1 can follow the update of the FIR tap coefficient with respect to high-speed carrier frequency / phase fluctuation and polarization fluctuation, and can improve the signal quality.

(Second Embodiment)
Hereinafter, a second embodiment of the present invention will be described in detail with reference to the drawings.
In the digital signal processing circuit 1 according to the first embodiment, since the FIR tap coefficient is not controlled at times other than the known pattern, the known pattern is changed to the polarization state, chromatic dispersion, polarization mode dispersion, and transmission laser. It is necessary to insert a known pattern sufficiently frequently with respect to the fluctuation time of the temporal fluctuation factors such as the frequency / phase and the frequency / phase of the receiving end LO (Local Oscillator) laser (local light). In addition, when the received signal gradually changes due to the above-described time fluctuation factor, the FIR tap coefficient cannot follow the fluctuation, and thus the degradation of the received signal quality such as improvement in error rate is inevitable.
In the digital signal processing circuit according to the present embodiment, in the time when the received signal does not include the known pattern, that is, in the payload portion, the post-determination pattern digitally determined after the FIR filter is used as the target pattern instead of the known pattern, FIR tap coefficients are estimated so that the error is minimized.

  FIG. 4 is a schematic block diagram showing the configuration of the digital signal processing circuit 2 according to the second embodiment of the present invention. The digital signal processing circuit 2 uses the frame synchronization clock to switch the target pattern by using a switch unit that outputs a known pattern as a target pattern in a known pattern portion and a pattern after determination in other payload portions. .

  In FIG. 4, the identification determination unit 26 receives data output from the FIR filter 14 and outputs a pattern after digital determination. For example, in the case of QPSK, there are four determined symbol positions shifted by 90 degrees. On the other hand, the signal input to the identification determination unit 26 has a random position due to waveform deterioration and noise. Determining this as one of the determined four symbol positions by the identification determination unit 26 is called digital determination. A signal series generated as four symbol positions is called a post-digital decision pattern. The switch unit 25 uses the frame synchronization clock to output the known pattern stored at the receiving end as the target pattern in the time portion when the known pattern of the received signal arrives, and in the other time portion, the identification determination unit The post-determination pattern output from 26 is output as a target pattern. For example, the switch unit 25 selects the time when the frame synchronization clock is input as the start time of the time portion where the known pattern arrives, and selects the input of the signal of the known pattern. The switch unit 25 measures the time of the time portion of the known pattern stored in advance from this start time, selects the time when this time has passed as the start time of the time portion of the payload portion, and inputs the signal of the post-determination pattern signal Switch. The subtraction unit 12 calculates an error between the equalized output pattern output from the FIR filter 14 and the target pattern output from the switch unit 25. The FIR tap coefficient control unit 13 controls the FIR tap coefficient of the FIR filter 14 so that the error amount output from the subtraction unit 12 is minimized. In FIG. 4, the functions of the frame synchronization clock unit 11 and the FIR filter 14 are the same as those of the digital signal processing circuit 1 according to the first embodiment, and a description thereof will be omitted.

  In FIG. 4, the FIR tap coefficient is controlled using the known pattern generated at the receiving end in the known pattern portion and the pattern after digital determination in the other portions. The difference between the digital signal processing circuit 2 and the digital signal processing circuit 1 according to the first embodiment (FIG. 1) is a switch between the error amount calculated from the known pattern and the error amount calculated from the post-determination pattern. It is a point switched by the part 25 (switch part).

  Further, as shown in FIG. 5, the known pattern and the post-determination pattern are combined at a certain combination ratio and combined and input to the FIR tap coefficient control unit 13. Provided to the FIR tap coefficient controller 13 when the error amounts of the x polarization and y polarization according to the known pattern are e_t_x and e_t_y, and the error amounts according to the pattern after determination are e_d_x and e_d_y, respectively, and the coupling ratios are α and β. The error amounts e_x, e_y to be given are given by e_x = αe_t_x + βe_d_x, e_y = αe_t_y + βe_d_y. Using the frame synchronization clock, the value is controlled so that α is large and β is small in the known pattern portion, and α is zero or very small and β is large in the other portions. Further, the update speed may be increased by increasing the convergence coefficient in the pilot signal portion so that, for example, α is a numerical value of 1 or more.

FIG. 5 is a schematic block diagram showing the configuration of the digital signal processing circuit 3 according to a modification of the present embodiment.
In FIG. 5, the subtractor 12-1 (first subtractor) includes an equalized output (second subtractor) pattern output from the FIR filter 14, and a known pattern stored in the receiver. The error is calculated. The subtraction unit 12-2 calculates an error between the equalized output pattern output from the FIR filter and the post-determination pattern output from the identification determination unit 26. By using the frame synchronization clock, the switch unit 25 outputs an error from the subtracting unit 12-1 in the time portion where the known pattern of the received signal arrives, and outputs from the subtracting unit 12-2 in the other time portions. Output error. The FIR tap coefficient control unit 13 controls the FIR tap coefficient of the FIR filter 14 so that the error amount output from the switch unit 25 is minimized. In FIG. 5, since the functions of the frame synchronization clock unit 11, the FIR filter 14, and the identification determination unit 26 are the same as those of the digital signal processing circuit 2 (FIG. 4), the description thereof is omitted.

  FIG. 6 is a schematic diagram illustrating switching in the switch unit 25 according to the present embodiment. In this figure, the upper figure shows a received signal. The figure below shows the output of the switch unit 25. In the figure below, the signal indicated by “1” indicates the output of the switch unit 25. This figure shows that the switch unit 25 outputs the post-determination pattern in the time portion of the payload and outputs the known pattern in the time portion of the known pattern.

  As described above, according to the present embodiment, the digital signal processing circuits 2 and 3 output the known pattern stored in the receiving unit as the target pattern in the time portion when the known pattern of the received signal arrives, and otherwise In this time portion, the post-determination pattern output from the identification determination unit is output as a target pattern, and the FIR tap coefficient is updated so that the error amount between the equalized output pattern and the target pattern is minimized. Accordingly, the digital signal processing circuits 2 and 3 can follow the FIR tap coefficient without frequently inserting a known pattern into the received signal, and can improve the signal quality. Further, it is possible to prevent a known pattern from being frequently inserted into a signal to reduce a payload portion and to deteriorate data transmission efficiency. Furthermore, even when the received signal gradually changes due to a time fluctuation factor, the FIR tap coefficient can follow the fluctuation, and the signal quality can be improved.

(Third embodiment)
Hereinafter, the third embodiment of the present invention will be described in detail with reference to the drawings.
When there is a change in the time difference of the frequency difference and phase difference between the laser light at the transmitting end and the local light at the receiving end, the FIR tap is used in the tap coefficient estimation using a known signal to follow the phase rotation due to the frequency difference. The coefficient needs to change. If the frequency difference is large, the phase rotation cannot be followed and the FIR output may spread in the rotation direction.
The digital signal processing circuit according to this embodiment compensates for a phase shift.

  FIG. 7 is a schematic block diagram showing the configuration of the digital signal processing circuit 4 according to the third embodiment of the present invention. The first FIR filter 44-1 prepares signals with different delay amounts added to the received signal, multiplies each delayed signal by the FIR tap coefficient (referred to as the first FIR tap coefficient), and adds the signals. To do. The first FIR tap coefficient control unit 43-1 controls the first FIR tap coefficient so that the amplitude of the output signal from the first FIR filter 44-1 is constant. Specifically, the first FIR tap coefficient control unit 43-1 calculates the first FIR tap coefficient that minimizes the error amount, and outputs the first FIR tap coefficient to the first FIR filter 44-1. The first FIR tap coefficient control unit 43-1 includes the subtraction unit 12 shown in FIG. 1 (not shown). The carrier phase estimation unit 47 uses the output from the first FIR filter 44-1 to estimate the carrier phase shift amount between the local light and the transmission laser light. The phase compensation unit 48 compensates the carrier phase shift amount of the reception signal using the phase shift amount output from the carrier phase estimation unit 47 for the reception signal.

  The second FIR filter 44-2 prepares signals obtained by giving different delay amounts to the output signal from the phase compensator 48, and FIR tap coefficients (referred to as second FIR tap coefficients) in the respective delayed signals. ) And add. The second FIR tap coefficient control unit 43-2 controls the second FIR tap coefficient control unit 43-2 so that the error between the output signal from the second FIR filter 44-2 and the known target pattern stored in the receiving unit is minimized. Control FIR tap coefficients. The second FIR filter 44-2 includes the subtracting unit 12 shown in FIG. 1 (not shown). Specifically, the second FIR tap coefficient control unit 43-2 calculates a second FIR tap coefficient that minimizes the error amount, and outputs the second FIR tap coefficient to the second FIR filter 44-2.

  The digital signal processing circuit 4 shown in FIG. 7 prepares the first FIR filter 44-1 and the first FIR filter coefficient control unit 43-1 in order to estimate the carrier phase shift amount, and the carrier phase shift amount. Is detected at any time and this carrier phase shift is compensated before being input to the second FIR filter 44-2 that updates the second FIR tap coefficient using a known signal pattern.

  Here, the reason for using the first FIR filter 44-1 is that in the update of the first FIR tap coefficient, the first FIR filter 44-1 is controlled so as to have a degree of freedom with respect to the phase rotation of the reception pattern due to the carrier phase shift. This is because it is possible to suppress the time change of the FIR tap coefficient. In general, a reception pattern of a phase modulation signal can be represented by a constellation in which a real part of a reception signal is assigned to the horizontal axis and an imaginary part of the reception signal is assigned to the vertical axis, and the reception pattern is plotted on a two-dimensional plane. In the quaternary phase modulation (QPSK) system, plotting is performed at four points on concentric circles whose phases are shifted by 90 degrees. On the other hand, when there is a carrier phase shift, these four points rotate concentrically, resulting in a constellation with a tail. Therefore, in order to control the FIR tap coefficient so as to have a degree of freedom with respect to the carrier phase shift, the FIR tap coefficient may be controlled so as to form a donut-shaped constellation. A prominent method is Constant Modulus Algorithm (CMA). The following formula can be used for updating the FIR tap coefficient. First, as the operation of the first FIR filter 44-1, the received X polarization and Y polarization M signals x_in (k), y_in (k), and FIR tap coefficients having M components Using Hxx (m), Hxy (m), Hyx (m), and Hyy (m), the X polarization component, Y polarization component x_out (k), and y_out (k) of the FIR filter output 2).

  The error amounts e_x and e_y of the X and Y polarization are expressed by the following equations.

  Using the error amount shown in Equation (3), the FIR tap coefficient can be updated by the following Equation (4).

Here, μ is a parameter that determines the update speed, and is called a convergence coefficient. The value is 1 or less.
Next, the carrier phase shift is estimated from the output of the first FIR filter 44-1. In the QPSK modulation signal, when the output signal of the first FIR filter 44-1 is raised to the fourth power, all symbols converge to the same point on the constellation regardless of the modulation pattern. In general, x-PSK converges to one point by raising to the power of x. Here, the QPSK method will be described.
Furthermore, after the FIR filter output is raised to the fourth power, it is averaged with M symbols before and after. Specifically, it is represented by the following formula (5).

  Further, by taking the phase angle in the complex plane of x_avg (k−M / 2) and y_avg (k−M / 2), it is possible to detect the carrier phase shift regardless of the data modulation pattern. A specific example is shown by the following formula. When the k-th phase shift amount is φ_x (k) and φ_y (k), the update equations for φ_x (k) and φ_y (k) are expressed by the following equation (6).

Here, Arg [] is a notation for calculating the phase angle in the complex plane.
Further, before calculating the phase angle, an anti-phase rotation of the (k−1) th phase shift is given to change only the phase shift amount from k−1 to the kth. As a result, the inside of the Arg becomes small, and the problem of the 360 degree uncertainty of the Arg function can be avoided or reduced.

  The detected phase shift amount is provided to the phase compensation unit 48. The phase compensator 48 compensates for the phase shift by giving this phase shift amount as reverse rotation to the input x and y polarization components. Thereafter, by inputting to the second FIR filter 44-2, the phase shift amount and its time change are removed in the update of the second FIR tap coefficient, so the update of the second FIR tap coefficient is Since it can be updated except for this, only the component with a relatively small change rate such as polarization rotation and the residual component of the phase shift amount is compensated, so that the time change of the second FIR tap coefficient is relatively slow. Become. As a result, the convergence coefficient of the second filter tap coefficient control unit 43-2 can be reduced, the average time in the tap coefficient estimation can be lengthened, and errors due to noise or the like can be minimized, and the FIR tap can be reduced. It can approach the true optimal value of the coefficient.

  FIG. 8 is a schematic block diagram showing the configuration of the digital signal processing circuit 5 according to the first modification of the present embodiment. In FIG. 8, the delay unit 59 matches the arrival time of the signal pattern input to the phase compensation unit 48 with the arrival time of the signal pattern to which the phase shift amount output by the carrier phase estimation unit 47 can be adapted. Give the amount of delay. In FIG. 8, the first FIR filter 44-1, the first FIR tap coefficient control unit 43-1, the carrier phase estimation unit 47, the phase compensation unit 48, the second FIR filter 44-2, and the second Since the FIR tap coefficient control unit 43-2 is the same as that of the digital signal processing circuit 4 (FIG. 7), description thereof is omitted.

  When applying the phase rotation amount output from the carrier phase estimation to the phase compensation of the input signal, the digital signal processing circuit 5 causes a delay due to the average number of times in the carrier phase estimation and the first FIR filter. This time delay is given before phase compensation. As shown in Equation (5), since the average of M symbols is taken, at least the delay amount in the carrier phase estimation portion is about M / 2. The optimum delay amount is about the sum of the delay in the FIR filter and half the number of averaged symbols in the carrier phase estimation.

FIG. 9 is a schematic block diagram showing the configuration of the digital signal processing circuit 6 according to the second modification of the present embodiment. In the digital signal processing circuit 6, in order to estimate the carrier phase shift amount, the first FIR filters 44-11 and 44-12 and the first FIR tap coefficient are respectively corresponding to the X polarized wave and the Y knitted wave. Controllers 43-11 and 43-12 are prepared to perform rough polarization separation, polarization mode dispersion compensation, and residual CD compensation. Then, in the subsequent carrier phase estimation, the carrier phase shift amount is detected as needed to compensate for the carrier phase shift.
The first FIR filters 44-11 and 44-12 in FIG. 9, the first FIR filter 44-1 in FIG. 7, the first FIR tap coefficient control units 43-1 and 43-12 in FIG. 7 first FIR tap coefficient control unit 43-1, carrier phase estimation units 47-11 and 47-12 in FIG. 9, carrier phase estimation unit 47 in FIG. 7, phase compensation units 48-11 and 48- in FIG. 12 and the phase compensation unit 48 in FIG. The second FIR filter 44-2 and the second FIR tap coefficient control unit 43-2 are the same as those of the digital signal processing circuit 4 (FIG. 7), and thus the description thereof is omitted.

Here, the reason for using the first FIR filters 44-11 and 44-12 is that, in updating the filter tap coefficients, control is performed so as to have a degree of freedom with respect to the phase rotation of the received pattern due to the carrier phase shift. Thus, it is possible to suppress the time change of the FIR tap coefficient. In general, a reception pattern of a phase modulation signal can be expressed by a constellation in which a real part of a reception signal is assigned to the horizontal axis and an imaginary part of the reception signal is assigned to the vertical axis, and the reception pattern is plotted on a two-dimensional plane. In the quaternary phase modulation (QPSK) system, plotting is performed at four points on concentric circles whose phases are shifted by 90 degrees. On the other hand, when there is a carrier phase shift, these four points rotate concentrically, resulting in a constellation with a tail. Therefore, in order to control the FIR tap coefficient so as to have a degree of freedom with respect to the carrier phase shift, the FIR tap coefficient may be controlled so as to form a donut-shaped constellation. A prominent example of this technique is Constant Modulus Algorithm. The following formula can be used for updating the FIR tap coefficient.
First, as an operation of the FIR filter, received X polarization and Y polarization M signals x_in (k) and y_in (k), and tap coefficients Hxx (m) and Hxy (Mxy) having M components. m), Hyx (m), and Hyy (m) are used to express the X polarization component, Y polarization component x_out (k), and y_out (k) of the FIR filter output by Expression (2). In the second FIR filter 44-2 at the subsequent stage, the coarsely compensated signals of the first FIR filters 44-11 and 44-12 are input, and the highly accurate compensation is performed. This merit is that in addition to suppressing phase rotation due to carrier phase shift, it is possible to remove residual components of deterioration such as residual chromatic dispersion, polarization imperfection, and polarization mode dispersion. The optimization control of the FIR tap coefficient of the second FIR filter 44-2 is also performed individually for each of the X polarization and the Y polarization, so that a more accurate compensation calculation can be performed.

The result of having investigated the effect of the digital signal processing circuit 4 which concerns on this embodiment using experimental data is shown. It is a result using QPSK data. FIGS. 10A and 10B show constellations in the case where there is no phase compensation described above and in the case where there is phase compensation, respectively.
FIG. 10 is a schematic diagram showing an experimental evaluation of the effect of phase compensation. In this figure, it can be seen that the phase rotation is stopped by the phase compensation. Further, when there is no phase compensation, not only the phase rotation but also the distribution spread is observed. This is probably because the true value of the FIR tap coefficient changes due to the phase rotation, so that the optimization accuracy cannot be obtained.
When the Q value representing the signal quality was calculated from the error rate, it was 10.4 dB without phase compensation and 12.6 dB with phase compensation. On the other hand, when there is phase compensation, if the LMS convergence coefficient is further reduced, the error rate is further lowered. In updating the second FIR tap coefficient used, the LMS algorithm was used, and the convergence coefficient was set to 0.01 for both (a) and (b).

FIG. 11 is a schematic diagram showing the relationship between the LMS convergence coefficient and the Q value.
As shown in FIG. 11A, when the phase compensation is not used, the optimum value is about 0.01 to 0.012. On the other hand, as shown in FIG. 11B, when applying phase compensation using the phase shift amount output from the first FIR filter 44-1 and the carrier phase estimation 47, the allowable range of the LMS convergence coefficient is Widely, 0.01 or less indicates a sufficiently high Q value close to the limit value. Although the optimum value is less than 0.001 or the like, this experiment is evaluated in a situation where no polarization fluctuation occurs because the optical fiber transmission line is not transmitted. Can be raised.
This experiment was evaluated using a modulation format in which two subcarriers subjected to QPSK modulation and polarization multiplexing were orthogonal frequency multiplexed. Even in the case of the single carrier modulation format, although there are some differences, the tendency is considered to be the same. The symbol rate is 13.9 Gbaud and the bit rate is 111 Gbps. The number of symbols of the known signal is 2047, which corresponds to a time length of 150 nanoseconds. 10 and 11, the frame length is 20470 symbols, which is a condition of 10 times the known signal pattern. Further, the average number of symbols for carrier phase estimation was M = 32.

  Assuming a polarization fluctuation of about 10 kHz, 20 kHz, or 50 kHz, this corresponds to a time fluctuation period of 100, 50, or 20 microseconds. When the FIR tap coefficient of the FIR filter is updated using the pilot signal, it is necessary to transmit the pilot signal at a frequency of at least 10 times to 100 times or more in order to follow the fluctuation described on the left. Therefore, the pilot signal transmission time interval is about 10, 5, or 2 microseconds to 1,0.5, or 0.2 microseconds or less. Therefore, it is necessary to insert a transmission pilot signal at a high frequency. Assuming that the frequency is inserted at this frequency and further suppressing the rate of increase in the bit rate due to the transmission of the pilot signal to 1% or less, the time length of the pilot signal is equivalent to about 1%, 100, 50, Alternatively, it is necessary to suppress it to about 20 nanoseconds to 10 or 5 or 2 nanoseconds or less. One percent is an example, and 0.5% is determined by the design.

As a method of reducing this frequency, there is a determination feedback LMS that continuously updates the FIR tap coefficient in the payload portion by using the signal after determination as a target pattern in the payload portion.
Further, as a parameter for determining the frame size, the known pattern size, the known pattern transmission frequency, and the like, the characteristics of the error correction circuit arranged in the subsequent stage can be mentioned. The error correction circuit in the subsequent stage has the feature of encoding and decoding for error correction for each block, but the maximum value that can be corrected even when bit errors occur continuously, that is, the allowable number of consecutive errors is is there. By setting the frame length of the transmission signal to be less than or equal to this number of errors, even if the tracking of channel estimation fails in the payload part of the frame due to steep polarization fluctuations, phase fluctuations, frequency fluctuations, nonlinear distortion, etc. The occurrence of errors after correction can be avoided. This is because error generation can be limited to a single frame by promptly performing transmission path estimation using a known pattern portion.

  FIG. 12 is a schematic diagram illustrating an example of an experimental evaluation result of frame size dependency. In this figure, the graph represented by a solid line shows the case with phase compensation, and the graph represented by a broken line shows the case without phase compensation. In this figure, the known pattern length of the Q value in the case without phase compensation is fixed, the known pattern length is set to 1, and the frame size is changed. The horizontal axis corresponds to the frame length / known pattern length. For example, in the case of 10, the known pattern is 2047 symbols, the payload portion is 18423 symbols, and the frame length is 20470 symbols.

  FIG. 13 is a schematic block diagram showing the configuration of the digital signal processing circuit 7 according to the third modification of the present embodiment. In FIG. 13, the frame synchronization clock unit 11 detects and outputs a frame synchronization clock synchronized with the arrival time timing of the known pattern portion included in the received signal. The second FIR tap coefficient control unit controls to update the second FIR tap coefficient only in the known pattern portion by using the frame synchronization clock output from the frame synchronization clock unit 11. The first FIR filter 44-1, the first FIR tap coefficient control unit 43-1, the carrier phase estimation unit 47, the phase compensation unit 48, and the second FIR filter 44-2 are included in the digital signal processing circuit 4. Since it is the same as that of (FIG. 7), description is abbreviate | omitted.

In updating the second FIR tap coefficient, in the FIR tap coefficient estimation using the known pattern, the FIR tap coefficient can be updated when the known pattern arrives. Therefore, in the configuration of FIG. 13, when a known pattern arrives using the frame synchronization clock, the second FIR tap coefficient is reflected by reflecting the error between the received known pattern and the known pattern stored at the receiving end. Update.
At this time, it is necessary to match the time phases of the known pattern, the FIR filter output pattern, and the FIR input pattern stored at the receiving end inputted to the subtracting unit. Since the time phases of the FIR filter input and the FIR filter output are fixed, the time phases are matched by inserting a delay device, a buffer, or the like in the propagation path of each signal in the receiving end digital arithmetic circuit. be able to. You may design so that both time phases may correspond at the time of design. In the time phase of the known pattern, a frame synchronization clock may be provided to the generation unit to generate a pattern synchronized with the generation unit. Further, a time phase may be adjusted by inserting a buffer or the like in the propagation path of the known pattern.

  FIG. 14 is a schematic block diagram showing the configuration of the digital signal processing circuit 8 according to the fourth modification of the present embodiment. In FIG. 14, the identification determination unit 26 receives data output from the FIR filter and outputs a pattern after digital determination. The switch unit 25 uses the frame synchronization clock to output the known pattern stored in the receiving unit as a target pattern in the time portion when the known pattern of the received signal arrives, and in the other time portion, the identification determination unit The post-determination pattern output from 26 is output as a target pattern. The second FIR tap coefficient control unit 43-2 calculates an error between the equalized output pattern output from the second FIR filter 44-2 and the target pattern output from the switch unit 25. The second FIR tap coefficient control unit 43-2 controls the second FIR tap coefficient so that the calculated error amount is minimized. The frame synchronization clock 11, the first FIR filter 44-1, the first FIR tap coefficient control unit 43-1, the carrier phase estimation unit 47, the phase compensation unit 48, and the second FIR filter 44-2 are: Since it is the same as that of the digital signal processing circuit 7 (FIG. 13), description thereof is omitted.

In the digital signal processing circuit 7 shown in FIG. 13, since the FIR tap coefficient is not controlled at times other than the known pattern, the known pattern is changed to the polarization state, chromatic dispersion, polarization mode dispersion, and the frequency / phase of the transmission laser. Therefore, it is necessary to insert a known pattern sufficiently frequently with respect to the fluctuation time of temporal fluctuation factors such as the frequency and phase of the receiving end LO laser. In addition, when the received signal gradually changes due to the above-described time fluctuation factor, the FIR tap coefficient cannot follow the fluctuation, and thus the degradation of the received signal quality such as improvement in error rate is inevitable.
In the digital signal processing circuit 8 shown in FIG. 14, in the time when the received signal does not include the known pattern, that is, in the payload portion, the determined pattern digitally determined after the FIR filter is used as the target pattern instead of the known pattern, In this configuration, the FIR tap coefficient is estimated so that the error is minimized. In this case, using the frame synchronization clock, the target pattern is switched by using a switch unit that outputs a known pattern as a target pattern in the known pattern portion and a pattern after determination in the other payload portions.

  Further, as in the digital signal processing circuit 2 shown in FIG. 4, the error amount calculated from the known pattern and the error amount calculated from the post-determination pattern may be switched by the switch unit. Further, like the digital signal processing circuit 3 shown in FIG. 5, the known pattern and the post-determination pattern may be combined at a certain combination ratio and combined and input to the FIR tap coefficient control unit. Provided to the FIR tap coefficient control unit if the error amounts of the x-polarization and y-polarization according to the known pattern are e_t_x and e_t_y, respectively, and the error amounts according to the pattern after determination are e_d_x and e_d_y, respectively, and the coupling ratios are α and β. The error amounts e_x and e_y are given by e_x = αe_t_x + βe_d_x, e_y = αe_t_y + βe_d_y. Using the frame synchronization clock, the value is controlled so that α is large and β is small in the known pattern portion, and α is zero or very small and β is large in the other portions.

FIG. 15 is a schematic diagram illustrating another example of the experimental evaluation result of the frame size dependency. In this figure, a graph represented by a solid line shows a case where the determination feedback LMS is used (digital signal processing circuit 8), and a graph represented by a broken line shows a case where the determination feedback LMS is not used (digital signal processing circuit 7). . This figure shows the result of experimental evaluation of the frame size dependence of the Q value when used for the decision feedback LMS and when not used.
In FIG. 15A, carrier phase estimation by the first FIR filter using CMA is also applied, and the time variation of the large carrier phase shift is compensated, so the FIR tap coefficient of the second FIR filter is True time fluctuation is a small condition. Even so, when the frame size increases and the frequency of known patterns decreases, the Q value is maintained higher when the decision feedback LMS is used together. On the other hand, FIG. 15B shows a case where there is no carrier phase estimation by the first FIR filter using CMA. In this case, the difference due to the presence or absence of the determination feedback LMS is large. This is because the determination feedback LMS compensates for the time variation of the carrier phase shift. On the other hand, compared to FIG. 15A, the absolute value of the Q value is low, and the true value of the LMS tap coefficient changes with time in the carrier phase estimation, which makes it difficult to optimize the LMS tap coefficient.

  FIG. 16 is a schematic block diagram showing a configuration of a digital signal processing circuit 9 according to Modification 5 of the present embodiment. In FIG. 16, a carrier phase estimation unit 87 inputs a known pattern, and detects a carrier phase shift by comparing the known pattern with the output pattern of the first FIR filter in the known pattern arrival time portion. The phase rotation amount is output by combining with the carrier phase shift estimated from only the output signal from one FIR filter. The frame synchronization clock 11, the first FIR filter 44-1, the first FIR tap coefficient control unit 43-1, the phase compensation unit 48, the second FIR filter 44-2, and the second FIR filter 44- Since 2 is the same as that of the digital signal processing circuit 5 (FIG. 8), description thereof is omitted.

FIG. 16 shows a configuration using a known pattern in carrier phase estimation. In a time portion in which the received signal includes a known pattern, the phase rotation of the sample known pattern and the received known pattern by the complex plane is detected, and the carrier phase shift is estimated. On the other hand, in the payload portion, the carrier phase shift amount is estimated using the fourth power method.
First, in the known pattern portion, it is necessary to grasp the time position where the known pattern is included in the first FIR filter output, and the arrival time of the known pattern is grasped using the frame synchronization clock. As this method, by calculating the cross-correlation between the received data and the known pattern and detecting the time delay positions of both having a high correlation coefficient, the delay amount of both can be grasped. There is also a method for detecting a correlation peak in the frequency domain. The discrete time function of the received known pattern is Fourier transformed, the discrete time function of the sample known pattern is also Fourier transformed, one is divided by one, and further the inverse Fourier transformed. Then, peak detection is performed and the maximum peak time delay position is detected, whereby the former delay amount with respect to the latter can be grasped. Then, after compensating for this delay amount, the amount of rotation in the complex plane between the received known pattern and the known sample pattern is detected to estimate the carrier phase shift. Here, the X polarization and Y polarization of the k-th received known signal output from the first FIR filter are respectively x (k) and y (k), and the X polarization of the signal of the sample known pattern , Y polarization is px (k) and py (k), respectively, the average displacement amount on the complex plane due to phase shift for each of the X polarization and Y polarization is px_avg (k−M / 2), py_avg (k−M / 2), it is given by the following equation (7).

  Further, by taking the phase angle in the complex plane of px_avg (k−M / 2) and py_avg (k−M / 2), it is possible to detect a carrier phase shift using a known pattern. A specific example is shown by the following formula. When the k-th phase shift amount is φ_x (k) and φ_y (k), the update equations for φ_x (k) and φ_y (k) are expressed by the following equation (8).

Here, Arg [] is a notation for calculating the phase angle in the complex plane.
On the other hand, in the payload portion, the carrier phase shift is estimated using the Viterbi-Viterbi method. In the QPSK modulation signal, when the output signal from the first FIR filter is raised to the fourth power, all symbols converge to the same point on the constellation regardless of the modulation pattern. In general, x-PSK converges to one point by raising to the power of x. Here, the QPSK method will be described.
Furthermore, after the FIR filter output is raised to the fourth power, it is averaged with M symbols before and after. Specifically, it is the following formula (9).

  Further, by taking the phase angle in the complex plane of x_avg (k−M / 2) and y_avg (k−M / 2), it is possible to detect the carrier phase shift regardless of the data modulation pattern. A specific example is shown by the following formula. When the k-th phase shift amount is φ_x (k) and φ_y (k), the update equations for φ_x (k) and φ_y (k) are expressed by the following equation (10).

Here, Arg [] is a notation for calculating the phase angle in the complex plane.
Further, before calculating the phase angle, an anti-phase rotation of the (k−1) th phase shift is given to change only the phase shift amount from k−1 to the kth. As a result, the inside of the Arg becomes small, and the problem of the 360 degree uncertainty of the Arg function can be avoided or reduced.
Further, even when switching between the known pattern portion and the payload portion, it is possible to smoothly switch the phase estimation by combining the estimated amounts of both. At times other than switching, either carrier phase estimation is closed, and M symbols can be averaged. On the other hand, at the time of switching, one averaged symbol number is n, and the other averaged symbol number is M−n. Again, if both can be fused and averaged, switching can be performed smoothly, and changes in the amount of phase rotation can be followed during that time.

  The following is one method. Assuming switching from the payload portion to the known pattern portion, this is an example in which the averaging of the n symbols with the known pattern and the averaging of the payload portion of the MN symbols are fused. First, the average value of the displacement amount in the complex plane shape in the known pattern is expressed by the following equation (11).

  Moreover, the average value of the displacement amount in the complex plane shape in the payload portion is expressed by the following equation (12).

  Assuming that the k-th phase shift amount φ (k) is used, an update equation for φ_x (k) and φ_y (k) is expressed by the following equation (13).

α and β represent the contribution ratios from the payload portion and the known pattern portion. As a simple method, a method of weighting with the averaged symbol numbers n and M is devised. In the following example, a contribution rate proportional to the number of symbols is set. There is a method of setting α = (1−n / M) and β = n / M. There are other functional systems such as increasing the contribution rate from known patterns. Setting α + β to be 1 is effective for stable operation.

  As described above, according to the present embodiment, the digital signal processing circuits 4 to 9 estimate the phase shift amount of the local light and the transmission laser from the FIR filter output pattern, and the local light and the transmission laser from the time change of the phase shift amount. The amount of light frequency shift is calculated, and the amount of compensation of the frequency compensator is controlled so that the shift is reduced. As a result, the digital signal processing circuits 4 to 9 follow the phase rotation even when there is a time change in the frequency difference and phase difference between the laser light at the transmitting end and the local light at the receiving end. The tap coefficient can be followed, and the signal quality can be improved.

(Fourth embodiment)
Hereinafter, a fourth embodiment of the present invention will be described in detail with reference to the drawings.
When there is a frequency difference between the laser light at the transmitting end and the local light at the receiving end, the FIR tap coefficient estimation using a known signal needs to change the FIR tap coefficient so as to follow the phase rotation due to the frequency difference. is there. If the frequency difference is large, the phase rotation cannot be followed and the FIR output may spread in the rotation direction.
In the digital signal processing circuit according to the present embodiment, in order to stop this rotation, the frequency deviation is monitored and the frequency deviation is compensated before being input to the FIR filter.

  FIG. 17 is a schematic block diagram showing the configuration of the digital signal processing circuit 10 according to the fourth embodiment of the present invention. In the digital signal processing circuit 10, this frequency shift is estimated from the time change of the FIR tap coefficient, and the frequency of the input signal to the FIR filter is compensated in advance.

  In FIG. 17, the FIR filter unit 14 prepares signals with different delay amounts added to the received signals, adds the FIR tap coefficients in the signals subjected to the respective delays, and adds them. The subtractor 12 calculates an error between the equalized output pattern output from the FIR filter 14 and a target pattern such as a known pattern stored in the receiver. The FIR tap coefficient control unit 13 controls the FRI tap coefficient so that the error amount output from the subtraction unit 12 is minimized. The frequency offset amount calculation unit 97 calculates the carrier frequency difference between the local light and the transmission signal from the FRI tap coefficient output from the FIR tap coefficient control unit 13, and calculates the frequency compensation amount given by the frequency compensation unit 97. The frequency compensation unit 98 corrects the frequency shift of the reception signal input to the FIR filter 14 based on the frequency compensation amount calculated by the frequency offset amount calculation unit 97.

  If there is a frequency offset, the FIR tap coefficient is updated so as to cancel the carrier phase rotation due to the frequency offset. Therefore, phase rotation of the FIR tap coefficient occurs. Therefore, the frequency offset amount can be estimated from the FIR tap coefficient by detecting the time variation of the phase rotation of the FIR tap coefficient.

  FIG. 18 is a schematic block diagram showing the configuration of the frequency offset amount calculation unit 97 according to this embodiment. The time delay unit 971 delays the input FIR tap coefficient by a time ΔT and outputs it. The phase conjugate unit 972 performs phase mutual benefit conversion on the input FIR tap coefficient. The multiplier 973 multiplies the input value. The averaging unit 974 calculates an average value of the values multiplied by the multiplication unit 973. The phase angle unit 975 extracts the phase angle of the average value calculated by the averaging unit 974. The division unit 976 divides ΔT from the phase angle extracted by the phase angle unit 975.

For example, if ΔT is “1”, the FIR tap coefficient at a certain time k is h (k), and the FIR tap coefficient at a time k + 1 is h (k + 1), the carrier phase rotation during this time is h (k + 1) · h (k ) Equal to the phase rotation amount of ^* . Averaging this amount can suppress fluctuations, so averaging is desirable but not essential. Further, the phase rotation amount Δφ is given by Δφ = Arg (h (k + 1) · h (k) ^* ). By dividing this amount by the time interval ΔT, an instantaneous frequency offset Δf = Δφ / ΔT can be obtained. Since this amount includes an error due to optical noise or the like, if it is directly given to the frequency compensator as a frequency compensation amount, an unnecessary fluctuation occurs. For this reason, it is desirable to gradually compensate the frequency offset.

FIG. 19 is a schematic block diagram showing the configuration of the digital signal processing circuit 11 according to the first modification of the present embodiment. The digital signal processing circuit 11 is configured to average and gradually reflect the detected frequency offset amount when giving the frequency compensation to the frequency compensation. The frequency offset amount calculation unit 97 does not directly give the frequency offset estimated from the FIR tap coefficient as the frequency compensation amount in the frequency compensation unit 98, but the multiplication unit 1003 multiplies the detected frequency offset by a coefficient of 1 or less. Then, the adding unit 1001 updates the change as a frequency compensation amount to be given to the frequency compensation unit 98 and gives it to the frequency compensation unit 98 as a frequency compensation amount. For example, the multiplication unit 1003 multiplies the frequency offset calculated by the frequency offset amount calculation unit 97 by 1 / N. The adder 1001 outputs the value input from the multiplier 1003 to the frequency compensator 98 and stores it in the memory 1002. The adder 1001 sequentially outputs the value stored in the memory 1002 to the frequency compensator 98 N times.
In this way, the frequency offset is gradually attenuated, and the control is sequentially performed so that the optimum frequency compensation amount is obtained.

  FIG. 20 is a schematic diagram illustrating another example of the experimental evaluation result of the frame size dependency. In this figure, a graph represented by a solid line shows a case with carrier frequency offset compensation (digital signal processing circuit 10), and a graph represented by a broken line shows a case without phase compensation (digital signal processing circuit 1). This figure shows the dependence of the Q value on the frame size depending on the presence or absence of carrier frequency offset compensation using the time change of the FIR tap coefficient. Evaluation was performed with a FIR filter using CMA and a configuration not using carrier phase estimation. In this case, if the frequency offset is large, since the time change of the carrier phase shift is large in the update of the FIR tap coefficient using the known pattern, the optimum true value of the FIR tap coefficient changes every moment. Therefore, it is difficult to estimate the FIR tap coefficient using the known pattern, and the coefficient cannot be estimated with high accuracy. On the other hand, when carrier frequency offset compensation is applied, the frequency shift is suppressed to be small, so that the time change of the LMS tap coefficient is reduced, the FIR tap coefficient can be estimated more accurately, and the Q value is improved.

FIG. 21 is a schematic block diagram showing the configuration of the digital signal processing circuit 12 according to the second modification of the present embodiment.
The digital signal processing circuit 12 is configured to use FIR tap coefficient update and carrier phase estimation using CMA. In this case, the carrier frequency offset amount can be detected from the carrier phase estimation. Specifically, the carrier phase rotation amount estimated by the carrier phase estimation unit 87 is input to the frequency offset amount calculation unit 97 instead of the FIR tap coefficient. The frequency offset amount calculation unit 97 (see FIG. 18) calculates a frequency compensation amount from the carrier phase rotation amount input from the carrier phase estimation unit 87.

The carrier phase estimation unit 87 can estimate the carrier phase using the Viterbi-Viterbi fourth power method. In the QPSK modulation signal, when the output signal from the first FIR filter is raised to the fourth power, all symbols converge to the same point on the constellation regardless of the modulation pattern. In general, x-PSK converges to one point by raising to the power of x. Here, the QPSK method will be described.
Furthermore, after the FIR filter output is raised to the fourth power, it is averaged with M symbols before and after. Specifically, it is represented by the above formula (5).

Further, by taking the phase angle in the complex plane of x_avg (k−M / 2) and y_avg (k−M / 2), it is possible to detect the carrier phase shift regardless of the data modulation pattern. A specific example is shown by Formula (6). Assuming that the k-th phase shift amount is φ_x (k) and φ_y (k), the update equations for φ_x (k) and φ_y (k) are expressed by the above equation (6).
Further, before calculating the phase angle, an anti-phase rotation of the (k−1) th phase shift is given to change only the phase shift amount from k−1 to the kth. As a result, the inside of the Arg becomes small, and the problem of the 360 degree uncertainty of the Arg function can be avoided or reduced.

FIG. 22 is a schematic block diagram showing the configuration of the digital signal processing circuit 13 according to the third modification of the present embodiment. The digital signal processing circuit 13 is configured when carrier phase estimation is used after FIR tap coefficient compensation using a known pattern.
The carrier phase estimation unit 87 estimates the carrier phase shift from the output of the FIR filter 14. In the QPSK modulation signal, when the output signal from the FIR filter is raised to the fourth power, all symbols converge to one point on the constellation regardless of the modulation pattern. In general, x-PSK converges to one point by raising to the power of x. Here, the QPSK method will be described.
Further, after the output of the FIR filter 14 is raised to the fourth power, it is averaged by the front and rear M symbols. Specifically, it is represented by the above formula (5).

Further, by taking the phase angle in the complex plane of x_avg (k−M / 2) and y_avg (k−M / 2), it is possible to detect the carrier phase shift regardless of the data modulation pattern. A specific example is shown by Formula (6). Assuming that the k-th phase shift amount is φ_x (k) and φ_y (k), the update equations for φ_x (k) and φ_y (k) are expressed by the above equation (6).
Further, before calculating the phase angle, an anti-phase rotation of the (k−1) th phase shift is given to change only the phase shift amount from k−1 to the kth. As a result, the inside of the Arg becomes small, and the problem of the 360 degree uncertainty of the Arg function can be avoided or reduced.
The detected phase shift amount is provided to the phase compensation unit 48 and the frequency offset amount calculation unit 97. The phase compensator 48 compensates for the phase shift by giving this phase shift amount as reverse rotation to the input x and y polarization components. Further, the frequency offset amount calculation unit 97 (see FIG. 18) calculates a frequency compensation amount from the carrier phase rotation amount input from the carrier phase estimation unit 87.

  As described above, according to the present embodiment, the digital signal processing circuits 10 to 13 calculate the frequency compensation amount by calculating the carrier frequency difference between the local light and the transmission signal from the FIR tap coefficient or the phase rotation amount. Based on the frequency compensation amount, the frequency shift of the received signal input to the FIR filter is corrected. Thereby, even if there is a frequency difference between the laser light at the transmitting end and the local light at the receiving end, the digital signal processing circuits 10 to 13 can compensate the frequency shift and follow the FIR tap coefficient. Signal quality can be improved.

(Fifth embodiment)
Hereinafter, a fifth embodiment of the present invention will be described in detail with reference to the drawings.
In optical fiber transmission, waveform distortion due to chromatic dispersion has a large temporal spread, so that a semi-fixed FIR filter is used separately from an adaptive equalization filter for polarization separation, polarization mode dispersion compensation, etc. Is effective. In the digital signal processing circuit according to the present embodiment, the chromatic dispersion is measured at the time of initial setting, and the tap coefficient of the semi-fixed FIR filter is determined.

  FIG. 23 is a schematic block diagram showing the configuration of the digital signal processing circuit 14 according to the fifth embodiment of the present invention. In FIG. 23, in the initial setting, the chromatic dispersion is measured to determine the FIR tap coefficient of the semi-fixed FIR filter 14-1. At this time, an error is included in the estimated amount of chromatic dispersion. There are also time changes due to temperature changes, stress changes, and the like. Accordingly, the residual chromatic dispersion can be estimated by using the pilot signal or the feedback signal after digital determination in the adaptive equalization FIR filter 14-2 in the subsequent stage. This residual chromatic dispersion amount is estimated and fed back to the FIR tap coefficient control unit 13-2 of the semi-fixed FIR filter 14-1 at the previous stage. FIG. 22 shows a configuration for calculating from the FIR tap coefficient of the adaptive equalization filter 14-2 at the subsequent stage. However, a circuit for estimating the residual chromatic dispersion amount is prepared separately, and feedback after a known signal or digital determination is made. The signal may be used to estimate residual chromatic dispersion.

(Sixth embodiment)
Hereinafter, the sixth embodiment of the present invention will be described in detail with reference to the drawings.
In the present embodiment, a first FIR tap coefficient control unit and a second FIR tap coefficient control unit are provided in updating the tap coefficients of the FIR filter.

  FIG. 24 is a schematic block diagram showing the configuration of the digital signal processing circuit 15 according to the sixth embodiment of the present invention. The digital signal processing circuit 15 is configured to include a first FIR tap coefficient control unit 153-1 and a second FIR tap coefficient control unit 153-2 in updating the FIR tap coefficient of the FIR filter 14.

The first FIR tap coefficient control unit 153-1 calculates an error between the output of the FIR filter 14 and the target pattern using the known pattern as the target pattern, and controls the FIR tap coefficient so that the difference between them is reduced.
By using different patterns for the X polarization and the Y polarization as the known pattern, the FIR tap coefficient is controlled so that an error from the known pattern of the X polarization becomes small in the output of the X polarization FIR filter 14. To do. On the other hand, the output of the Y-polarized FIR filter 14 is controlled so that an error from the known pattern of the Y-polarized light becomes small. As a result, control can be performed so that the polarization components having different X polarization and Y polarization can be demodulated, and the output of the F polarization filter 14 of X polarization and Y polarization becomes the same polarization output. Can be avoided. A FIR filter and a tap coefficient control unit are prepared for each of the X polarization and the Y polarization. As a specific estimation algorithm, there is a method using LMS. The method of operation has been described above.

  Thereafter, when the tap coefficient estimation converges to some extent and the error becomes small, the control is switched to the second FIR tap coefficient control unit 153-2. Here, the characteristics of the FIR filter 14 in the case of switching are that the FIR tap coefficient is updated by controlling the FIR tap coefficient so as to have a degree of freedom with respect to the phase rotation of the received pattern due to the carrier phase shift. It is in the point that it becomes possible to suppress the time change. In general, a reception pattern of a phase modulation signal can be represented by a constellation in which a real part of a reception signal is assigned to the horizontal axis and an imaginary part of the reception signal is assigned to the vertical axis, and the reception pattern is plotted on a two-dimensional plane. In the quaternary phase modulation (QPSK) method, plotting is performed at four points on concentric circles whose phases are shifted by 90 degrees. On the other hand, when there is a carrier phase shift, these four points rotate concentrically, resulting in a constellation with a tail. Therefore, in order to control the FIR tap coefficient so as to have a degree of freedom with respect to the carrier phase shift, the FIR tap coefficient may be controlled so as to form a donut-shaped constellation. A prominent example of this technique is Constant Modulus Algorithm. The following formula can be used for updating the FIR tap coefficient. First, as an operation of the FIR filter, received X polarization and Y polarization M signals x_in (k) and y_in (k), and tap coefficients Hxx (m) and Hxy (Mxy) having M components. m), Hyx (m), and Hyy (m) are used to express the X polarization component, Y polarization component x_out (k), and y_out (k) of the FIR filter output by the following equation (14).

  The error amounts e_x and e_y of the X and Y polarization are expressed by the following equation (15).

  Using the error amount shown in Expression (15), the FIR tap coefficient can be updated by the following Expression (16).

ここで、μは更新の速度を決定するパラメータであり、収束係数と呼ぶ。１以下の値である。
次に、第一のＦＩＲフィルタ出力からキャリア位相ずれを推定する。ＱＰＳＫ変調信号では、第一のＦＩＲフィルタ出力信号を4乗すると、変調パターンにかかわらず全てのシンボルがコンスタレーション上で同一の１点に収束する。一般に、ｘ−ＰＳＫではｘ乗することで、一点に収束する。ここでは、ＱＰＳＫ方式で説明する。
さらに、ＦＩＲフィルタ出力を4乗した後に、前後Mシンボルで平均化する。具体的には、以下の式である。

Here, μ is a parameter that determines the update speed, and is called a convergence coefficient. The value is 1 or less.
Next, the carrier phase shift is estimated from the first FIR filter output. In the QPSK modulation signal, when the first FIR filter output signal is raised to the fourth power, all symbols converge to the same point on the constellation regardless of the modulation pattern. In general, x-PSK converges to one point by raising to the power of x. Here, the QPSK method will be described.
Furthermore, after the FIR filter output is raised to the fourth power, it is averaged with M symbols before and after. Specifically, it is the following formula.

  Further, by taking the phase angle in the complex plane of x_avg (k−M / 2) and y_avg (k−M / 2), it is possible to detect the carrier phase shift regardless of the data modulation pattern. A specific example is shown by the following formula. When the k-th phase shift amount is φ_x (k) and φ_y (k), the update equations for φ_x (k) and φ_y (k) are expressed by the following equation (18).

Here, Arg [] is a notation for calculating the phase angle in the complex plane.
Further, before calculating the phase angle, an anti-phase rotation of the (k−1) th phase shift is given to change only the phase shift amount from k−1 to the kth. As a result, the inside of the Arg becomes small, and the problem of the 360 degree uncertainty of the Arg function can be avoided or reduced.

FIG. 25 is a schematic block diagram showing the configuration of the digital signal processing circuit 16 according to the first modification of the present embodiment. The digital signal processing circuit 16 is configured to receive a frame synchronization clock and perform tap coefficient control using the known pattern at the time when the known pattern arrives.
In addition, there is a method in which the FIR tap coefficient is updated using the determination feedback LMS using the pattern after the identification determination at the time when the payload portion arrives instead of the known pattern. In detail, the above-described configuration for switching the target pattern or the error amount using the frame synchronization clock is used.

FIG. 26 is a schematic block diagram showing the configuration of the digital signal processing circuit 17 according to the second modification of the present embodiment.
When sudden polarization fluctuations, carrier phase fluctuations, or light intensity fluctuations occur, several to several tens of symbols are inserted as known frames, and errors between the known signals and the actually received signals are detected. When the error is large, it is detected that the FIR tap coefficient estimation is in an abnormal state.
In the normal state, the control of the FIR tap coefficient as described above is performed. However, the detection circuit 151 compares the known pattern with the digitally determined pattern to confirm the validity of the FIR tap coefficient and the validity of the carrier phase estimation / compensation. If there is an abnormality, if the error suddenly increases, it is determined that there is an error in FIR tap coefficient estimation or carrier phase estimation, and the FIR tap coefficient estimated by the second tap coefficient control unit 153-2 Change to Here, the second tap coefficient control unit 153-2 operates by a method of estimating the tap coefficient using a known signal, and the convergence coefficient is compared with the first tap coefficient control unit 153-1. Keep it big. As the operation method, the convergence coefficient is set so that the convergence is performed only in the known pattern portion. Further, an operation method in which the FIR tap coefficient is initialized in accordance with the timing when the known pattern arrives may be used.
In addition, when the detection circuit 151 detects an abnormality without providing the second tap coefficient control unit 153-2, the FIR tap coefficient of the first FIR filter coefficient control unit 153-1 is reset. The operation method may be used.
Also, the input data is saved in a buffer, and when an abnormality is detected, the tap coefficient newly estimated by the second tap coefficient control unit is applied to the saved input data and the output is recalculated. It may be configured.

FIG. 27 is a schematic block diagram showing the configuration of the digital signal processing circuit 18 according to the third modification of the present embodiment.
In the digital signal processing circuit 18, the carrier phase estimation unit 47 also uses a known signal to estimate the carrier phase offset, and there are methods described above in detail. Here, when an abnormality is detected in the detection circuit 151, the operation of switching the carrier phase offset estimation from the normal mode to the mode in which estimation is performed by focusing on the known pattern using the switching signal is performed. This method is realized by averaging the estimated amount with a large weight in the known signal portion when averaging. As a result, the carrier phase estimation error can be corrected.
Further, in the initial mode, there is a possibility that a signal pattern having the same X polarization and Y polarization arrives. In such a case, the timing at which the frame synchronization clock or the same pattern arrives may be detected, and control may be performed so that the tap coefficient of the FIR filter is not updated at that time. In the initial mode, control may be performed such that the tap coefficient of the FIR filter is not updated.

In the digital signal processing circuits 1 to 18 in each of the embodiments described above, a part of the configuration of the digital signal processing circuits 1 to 18 may be replaced, added, or deleted. Moreover, you may combine the one part structure of the digital signal processing circuits 1-18. For example, the FIR tap coefficient control unit 13 of the digital signal processing circuit 11 (FIG. 19) includes an identification determination unit 26, subtraction units 12-1 and 12-2, and a switch unit 25 of the digital signal processing circuit 3 (FIG. 5). May be. In this case, the subtraction unit 12-1 calculates an error between the equalized output pattern output from the FIR filter and the known pattern stored in the reception unit. The subtraction unit 12-2 calculates an error between the equalized output pattern output from the FIR filter 14 and the post-determination pattern output from the identification determination unit 26. By using the frame synchronization clock, the switch unit 25 outputs an error from the subtracting unit 12-1 in the time portion where the known pattern of the received signal arrives, and outputs from the subtracting unit 12-2 in the other time portions. Output error. The FIR tap coefficient control unit 13 controls the FIR tap coefficient of the FIR filter 14 so that the error amount output from the switch unit 25 is minimized. For example, the digital signal processing circuits 4 (FIG. 7) to 9 (FIG. 16) may include the frequency compensation unit 98 and the frequency offset amount calculation unit 97 of the digital signal processing circuit 10 (FIG. 17). In this case, the output of the first FIR tap coefficient control unit 43-1 is input to the frequency offset amount calculation unit 97, and the output of the frequency compensation unit 98 is input to the first FIR filter 44-1.
Moreover, in the drawings in the above-described embodiments, each part given the same reference numeral has the same function.

  A part of the digital signal processing circuits 1 to 18 in the above-described embodiment, for example, the frame synchronization clock unit 11, the subtraction units 12, 12-1, 12-2, the FIR tap coefficient control unit 13, the FIR filter 14, and the identification Determination unit 26, switch unit 25, first FIR tap coefficient control unit 43-1, second FIR tap coefficient control unit 43-2, first FIR filter 44-1, second FIR filter 44-2, The carrier phase estimation units 47 and 87, the phase compensation unit 48, the delay unit 59, the frequency offset amount calculation unit 97, and the frequency compensation unit 98 may be realized by a computer. In that case, the program for realizing the control function may be recorded on a computer-readable recording medium, and the program recorded on the recording medium may be read into a computer system and executed. Here, the “computer system” is a computer system built in the digital signal processing circuits 1 to 18 and includes an OS and hardware such as peripheral devices. The “computer-readable recording medium” refers to a storage device such as a flexible medium, a magneto-optical disk, a portable medium such as a ROM and a CD-ROM, and a hard disk incorporated in a computer system. Furthermore, the “computer-readable recording medium” is a medium that dynamically holds a program for a short time, such as a communication line when transmitting a program via a network such as the Internet or a communication line such as a telephone line, In such a case, a volatile memory inside a computer system serving as a server or a client may be included and a program that holds a program for a certain period of time. The program may be a program for realizing a part of the functions described above, and may be a program capable of realizing the functions described above in combination with a program already recorded in a computer system.

  As described above, the embodiment of the present invention has been described in detail with reference to the drawings. However, the specific configuration is not limited to the above, and various design changes and the like can be made without departing from the scope of the present invention. It is possible to

  DESCRIPTION OF SYMBOLS 1-18 ... Digital signal processing circuit, 11 ... Frame synchronous clock part, 12 ... Subtraction part (subtractor), 13, 13-1, 13-2 ... FIR tap coefficient control part (adaptive Equalization tap coefficient control unit), 14... FIR filter (adaptive equalization filter), 141... Delay unit, 142... Multiplication unit, 143. ... identification determination unit, 12-1 ... subtraction unit (first subtractor), 12-2 ... subtraction unit (second subtractor), 43-1, 43-11, 43-12 ... 1st FIR tap coefficient control part, 43-2 ... 2nd FIR tap coefficient control part, 44-1, 44-11, 44-12 ... 1st FIR filter, 44-2 ... Second FIR filter, 47, 87, 47-11, 47-12 ... Carrier phase Constant unit, 48, 48-11, 48-12 ... phase compensation unit, 59 ... delay unit, 97 ... frequency offset amount calculation unit, 98 ... frequency compensation unit, 971 ... time delay 972 ... Phase conjugate part, 973 ... Multiplying part, 974 ... Averaging part, 975 ... Phase angle part, 976 ... Division part, 1001 ... Adding part, 1002 ... Memory 1003... Multiplying unit 14-1... Semi-fixed FIR filter 14-2... Adaptive equalization FIR filter 140. , 152 ... switch unit, 153-1 ... first FIR tap coefficient control unit, 153-2 ... second FIR tap coefficient control unit, 171 ... detection circuit

Claims (6)

A digital signal processing circuit in a receiver used in an optical fiber transmission system,
The digital signal processing circuit uses local light to separate the optical electric field of the input signal light into orthogonal components for coherent reception, receives the time waveform of the orthogonal components as input, and receives it using digital computation Demodulate the data,
A frame synchronization clock unit that outputs a frame synchronization clock synchronized with the arrival time timing of the known pattern portion included in the received signal;
An adaptive equalization filter that prepares signals with different amounts of delay added to the received signals, multiplies each delayed signal by a tap coefficient, and adds them,
A subtractor that compares the output pattern after equalization output from the adaptive equalization filter with the known pattern stored in the receiver and calculates the error;
An adaptive equalization tap coefficient control unit that operates in a known pattern portion by using the frame synchronization clock and controls the tap coefficient of the adaptive equalization filter so that an error amount output from the subtractor is minimized; With
Two different patterns are used as the known pattern,
The adaptive equalization tap coefficient control unit operates in cooperation with two polarization outputs included in the reception signal, and either one of the two polarization outputs or one of the two different patterns. And the tap coefficient is updated so that the error amount between the other of the two polarization outputs and the other of the two different patterns is minimized. Processing circuit. A digital signal processing circuit in a receiver used in an optical fiber transmission system,
The digital signal processing circuit uses local light to separate the optical electric field of the input signal light into orthogonal components for coherent reception, receives the time waveform of the orthogonal components as input, and receives it using digital computation Demodulate the data,
A frame synchronization clock portion that detects and outputs a frame synchronization clock synchronized with the arrival time timing of the known pattern portion included in the received signal; and
An adaptive equalization filter that prepares signals with different amounts of delay added to the received signals, multiplies each delayed signal by a tap coefficient, and adds them,
An identification determination unit that inputs data output from the adaptive equalization filter and outputs a pattern after digital determination;
By using the frame synchronization clock, the known pattern stored in the receiving unit is output as the target pattern in the time portion where the known pattern of the received signal arrives, and is output from the identification determination unit in the other time portion. A switch unit that outputs a post-determination pattern as a target pattern;
A subtractor for calculating an error between the output pattern after equalization output from the adaptive equalization filter and the target pattern output from the switch unit;
An adaptive equalization tap coefficient control unit that controls tap coefficients of the adaptive equalization filter so that an error amount output from the subtractor is minimized,
Two different patterns are used as the known pattern,
The adaptive equalization tap coefficient control unit operates in cooperation with two polarization outputs included in the reception signal, and either one of the two polarization outputs or one of the two different patterns. And the tap coefficient is updated so that the error amount between the other of the two polarization outputs and the other of the two different patterns is minimized. Processing circuit. A digital signal processing circuit in a receiver used in an optical fiber transmission system,
The digital signal processing circuit uses local light to separate the optical electric field of the input signal light into orthogonal components for coherent reception, receives the time waveform of the orthogonal components as input, and receives it using digital computation Demodulate the data,
A frame synchronization clock portion that detects and outputs a frame synchronization clock synchronized with the arrival time timing of the known pattern portion included in the received signal; and
An adaptive equalization filter that prepares signals with different amounts of delay added to the received signals, multiplies each delayed signal by a tap coefficient, and adds them,
An identification determination unit that inputs data output from the adaptive equalization filter and outputs a pattern after digital determination;
A first subtractor for calculating an error between the output pattern after equalization output from the adaptive equalization filter and the known pattern stored in the reception unit;
A second subtractor that calculates an error between the output pattern after equalization output from the adaptive equalization filter and the post-determination pattern output from the identification determination unit;
By using the frame synchronization clock, an error from the first subtracter is output in the time portion where the known pattern of the received signal arrives, and an error output from the second subtractor is output in the other time portions. A switch part;
An adaptive equalization tap coefficient control unit that controls the tap coefficient of the adaptive equalization filter so that the amount of error output from the switch unit is minimized,
Two different patterns are used as the known pattern,
The adaptive equalization tap coefficient control unit operates in cooperation with two polarization outputs included in the reception signal, and either one of the two polarization outputs or one of the two different patterns. And the tap coefficient is updated so that the error amount between the other of the two polarization outputs and the other of the two different patterns is minimized. Processing circuit. A digital signal processing circuit according to any one of claims 1 to 3,
An adaptive equalization filter that prepares signals with different amounts of delay added to the received signals, multiplies each delayed signal by a tap coefficient, and adds them,
A subtractor that calculates an error between the output pattern after equalization output from the adaptive equalization filter and a target pattern such as a known pattern stored in the reception unit;
An adaptive equalization tap coefficient control unit that controls tap coefficients of the adaptive equalization filter so that an error amount output from the subtractor is minimized;
A frequency compensator for correcting a frequency shift of the received signal input to the adaptive equalization filter;
A frequency offset amount calculation unit that calculates a carrier frequency difference between the local light and the transmission signal from a tap coefficient output from the adaptive equalization tap coefficient control unit, and calculates a frequency compensation amount given by the frequency compensation unit. A digital signal processing circuit. A digital signal processing circuit according to any one of claims 1 to 4,
An adaptive equalization filter that prepares signals with different amounts of delay added to the received signals, multiplies each delayed signal by a tap coefficient, and adds them,
A subtractor that calculates an error between the output pattern after equalization output from the adaptive equalization filter and a target pattern such as a known pattern stored in the reception unit;
An adaptive equalization tap coefficient control unit that controls tap coefficients of the adaptive equalization filter so that an error amount output from the subtractor is minimized;
A frequency compensator for correcting a frequency shift of the received signal input to the adaptive equalization filter;
Frequency compensation is performed by comparing the target pattern with the output of the adaptive equalization filter, calculating an error, and using the tap coefficient and the input signal of the frequency compensation unit to control the frequency compensation amount so that the error is minimized. A digital signal processing circuit comprising: a quantity control unit; A digital signal processing circuit according to any one of claims 1 to 5,
An adaptive equalization filter that prepares signals with different amounts of delay added to the received signals, multiplies each delayed signal by a tap coefficient, and adds them,
A subtractor that calculates an error between the output pattern after equalization output from the adaptive equalization filter and a target pattern such as a known pattern stored in the reception unit;
An adaptive equalization tap coefficient control unit that controls tap coefficients of the adaptive equalization filter so that an error amount output from the subtractor is minimized;
A frequency compensator for correcting a frequency shift of the received signal input to the adaptive equalization filter;
A carrier phase estimator that estimates the amount of phase shift between the local light and the transmission laser from the adaptive equalization filter output pattern;
Frequency compensation for calculating the amount of frequency deviation between the local light and the transmitted laser light from the time change of the amount of phase deviation output from the carrier phase estimation unit, and controlling the compensation amount of the frequency compensation unit so that the deviation is reduced A quantity control unit;
A digital signal processing circuit comprising: a phase compensation unit that compensates a phase of an output signal from the adaptive equalization filter using a phase shift amount output from the carrier phase estimation unit.

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