WO2012019434A1

WO2012019434A1 - Method and device for sampling clock synchronization

Info

Publication number: WO2012019434A1
Application number: PCT/CN2011/001324
Authority: WO
Inventors: 刘斌彬; 葛启宏; 王秋生; 曹晓卫; 陶涛; 申红兵
Original assignee: 北京泰美世纪科技有限公司
Priority date: 2010-08-12
Filing date: 2011-08-10
Publication date: 2012-02-16
Also published as: CN102377715B; CN102377715A

Abstract

Disclosed is a sampling clock synchronization device, comprises: an A / D converter oversampling the received continuous signal to obtain oversampling sequence; an interpolation filter interpolates said oversampling sequence to obtain an oversampling sequence after a change in sampling frequency; a synchronous head extraction module to extract the synchronous head sequence from the oversampling sequence after a change in sampling frequency based on the signal frame structure and synchronous head location; a local synchronous sequence generator module generating local synchronous head sequence based on the signal frame structure; an early-late gate delays and down-samples said synchronous head sequence to obtain an early gate signal and a late gate signal, and correlate the local synchronous head sequence against the early gate signal and the late gate signal respectively, obtaining a sampling error based on the degree of symmetry of the correlation value;and a sample frequency offset adjustment module adjusting the current sample frequency offset based on the sampling error, obtaining the adjusted sample frequency offset and input into the A/D convertor or interpolation filter for sample frequency and phase synchronization. The present invention can quickly and accurately realize sampling clock synchronization.

Description

Sampling clock synchronization method and device

Technical field

The invention relates to a sampling clock synchronization method and device, in particular to a sampling clock synchronization method and device suitable for various digital broadcasting systems such as digital satellite broadcasting and digital terrestrial broadcasting. Background technique

In digital broadcasting systems, in addition to high frequency and power utilization, strong anti-noise and interference capabilities, and support for data and multimedia services, the biggest feature is the wide coverage. Especially for China, which has a vast territory, diverse geographical environment and uneven population distribution, digital broadcasting systems play an important role in national information infrastructure construction and national information security strategy.

In receivers of various digital broadcasting systems such as digital satellite broadcasting, digital terrestrial broadcasting, etc., an analog/digital (A/D) converter is required to sample the received continuous signal. However, the A/D converter of the receiver and the digital/analog (D/A) converter of the transmitter may not have exactly the same sampling clock frequency and phase.

For multi-carrier systems, such as Orthogonal Frequency Division Multiplexing (OFDM) systems, the sampling bias causes the subcarriers in the frequency domain to be no longer orthogonal, resulting in crosstalk between subcarriers. For single-carrier systems, the receiver has stricter requirements for sample synchronization, that is, the sampling position needs to be at the maximum of the eye diagram to obtain the best possible signal-to-interference ratio (SINR).

Summary of the invention

The object of the present invention is to at least solve one of the above problems in the prior art.

To this end, embodiments of the present invention provide a sampling clock synchronization method and apparatus capable of quickly and accurately implementing sampling frequency and phase synchronization.

According to an aspect of the present invention, an embodiment of the present invention provides a sampling clock synchronization method, the method comprising the following steps: (a) oversampling a received continuous signal by using an analog/digital (A/D) converter Obtaining an oversampling sequence; (b) performing an oversampling sequence using an interpolation filter Interpolation processing to obtain an oversampled sequence after sampling frequency conversion; (C) extracting a synchronization header sequence from the oversampled sequence after sampling frequency conversion according to the signal frame structure and the position of the synchronization header; (d) according to the signal frame structure Generating a local synchronization header sequence; (e) obtaining an early gate signal and a late gate signal by delaying and downsampling the synchronization header sequence, and respectively respectively, the local synchronization header sequence and the early gate signal and the late gate signal Performing cross-correlation, obtaining a sampling error according to the symmetry of the cross-correlation value; and (f) adjusting the current sampling frequency offset according to the sampling error, obtaining the adjusted sampling frequency offset, and inputting to the A/D converter Or the sampling frequency and phase synchronization are performed in the interpolation filter.

According to a further embodiment of the invention, step b is omitted when the A/D converter is controllable, and in step f, the adjusted sample frequency offset is input to the A/D converter.

According to a further embodiment of the present invention, the step of adjusting the current sampling frequency offset comprises: performing a temporary coarse adjustment on the current sampling frequency offset for controlling the synchronization of the sampling phase; and performing the current sampling frequency offset after a predetermined time. A permanent fine adjustment to control the synchronization of the sampling frequency.

According to a further embodiment of the invention, after step c, the segmentation of the synchronization header sequence is further performed, and the sequence of local synchronization headers generated in step d is correspondingly segmented. After the step e, the method further includes: performing mean calculation or filtering on the plurality of sampling errors corresponding to the segmentation, and performing noise reduction on the sampling error.

According to another aspect of the present invention, an embodiment of the present invention provides a sampling clock synchronization apparatus, the apparatus comprising: an A/D converter, the A/D converter oversampling a received continuous signal to obtain An over-sampling sequence, the interpolation filter, the interpolation filter performs interpolation processing on the over-sampling sequence to obtain an over-sampling sequence after sampling frequency conversion; a synchronization header extraction module, and the synchronization header extraction module according to a signal frame structure and a position of the synchronization header, extracting a synchronization header sequence from the oversampled sequence after the sampling frequency transformation; a local synchronization header sequence generation module, wherein the local synchronization header sequence generation module generates a local synchronization header sequence according to the signal frame structure; The sooner or later gate module delays and downsamples the synchronization header sequence to obtain an early gate signal and a late gate signal, and cross-correlates the local synchronization header sequence with the early gate signal and the late gate signal, respectively. Obtaining a sampling error according to the symmetry of the cross-correlation value; and sampling a frequency offset adjusting module, where the sampling frequency offset is adjusted The module adjusts the current sampling frequency offset according to the sampling error, obtains the adjusted sampling frequency offset, and inputs it into the A/D converter or the interpolation filter to perform sampling frequency. Rate and phase synchronization.

According to a further embodiment of the present invention, when the A/D converter is controllable, the interpolation filter is omitted, and the sampled frequency offset adjustment module adjusts the sampled frequency offset input to the A/D converter. in.

According to a further embodiment of the present invention, the sampling clock synchronization apparatus further includes: a segmentation module, the synchronization header sequence output by the segmentation module to the synchronization header extraction module and the local synchronization header output by the local synchronization header sequence generation module The sequence performs corresponding segmentation; and the noise reduction module performs mean calculation or filtering on the plurality of sampling errors corresponding to the segmentation output by the early and late gate modules, and is used for noise reduction of the sampling error.

According to a further embodiment of the present invention, when the A/D converter is controllable, the sampled frequency offset of the sampled frequency offset adjustment module is input to the interpolation filter.

According to a further embodiment of the present invention, when the A/D converter is uncontrollable, the sampled frequency offset adjustment module adjusts the sample frequency offset into the interpolation filter.

The invention obtains the sampling error by oversampling, synchronization header extraction, local synchronization header sequence generation, late-earth gate, and adjusts the sampling frequency offset according to the sampling error, and obtains the sampling frequency offset value input to the A/D converter or the interpolation filter. , can achieve fast and accurate sampling frequency and phase synchronization.

In addition, by segmenting the sync header and denoising the sampling error, it is possible to combat the effects of high-intensity noise interference and large carrier frequency offset values.

The additional aspects and advantages of the invention will be set forth in part in the description which follows.

DRAWINGS

The above and/or additional aspects and advantages of the present invention will become apparent and readily understood from

1 is a flowchart of a sampling clock synchronization method according to an embodiment of the present invention;

2 is a block diagram showing the structure of a clock synchronization device according to an embodiment of the present invention;

Figure 3 is a structural diagram of a signal frame suitable for use in the present invention;

4 is a schematic diagram of a pseudo-random sequence generator that generates a sequence of signal frame synchronization headers;

FIG. 5 is a schematic diagram of sampling error after sampling frequency offset adjustment according to an embodiment of the present invention. detailed description

The embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings. The embodiments described below with reference to the drawings are intended to be illustrative only and not to be construed as limiting.

Referring first to FIG. 1 and FIG. 2, FIG. 1 is a flowchart of a sampling clock synchronization method according to an embodiment of the present invention; FIG. 2 is a structural block diagram of a sampling clock synchronization apparatus according to an embodiment of the present invention.

As shown in FIG. 2, the sampling clock synchronization apparatus of the embodiment of the present invention includes an A/D converter 10, an interpolation filter 12, a synchronization header extraction module 14, a local synchronization header sequence generation module 18, a late-morning gate module 16, and a sampling frequency offset adjustment. Module 22.

The present invention is applicable to signals having a regular periodic frame structure, and each frame is composed of a sync header and a signal body, and the sync header may be a known sequence, a pseudo random (PN) sequence, a Walsh sequence, or the like. The structure of the signal frame is shown in Figure 3.

As shown in FIG. 1, the sampling clock synchronization method of the embodiment of the present invention includes the following steps: First, the received continuous signal is oversampled by the A/D converter 10 to obtain a sample sequence (step 102), and output. The interpolation filter 12 is given.

The interpolation filter 12 performs interpolation processing on the received oversampled sequence to obtain an oversampled sequence after the sampling frequency conversion (step 104), and outputs it to the sync header extraction module 14.

The sync header extraction module 14 extracts a sync header sequence from the sampled frequency-converted oversample sequence based on the signal frame structure and the position of the sync header (step 106).

The local sync header sequence generation module 18 then generates a local sync header sequence based on the signal frame structure (step 108).

The early and late gate module 16 obtains the early gate signal and the late gate signal by delaying and downsampling the synchronization header sequence, and cross-correlating the local synchronization header sequence with the early gate signal and the late gate signal respectively, according to the cross correlation value The symmetry results in a sampling error (step 110).

The sampling frequency offset adjustment module 22 adjusts the current sampling frequency offset according to the sampling error, obtains the adjusted sampling frequency offset, and inputs it into the A/D converter 10 or the interpolation filter 12 to perform sampling frequency and phase synchronization.

The sampling frequency of the A/D converter 10 can be controllable or uncontrollable. When A/D When the sampling frequency of the converter 10 is controllable, the adjusted sampling frequency offset is input to the A/D converter 10, and the A/D converter 10 dynamically adjusts according to the sampling frequency offset value to realize synchronization of the sampling frequency and phase. When the sampling frequency of the A/D converter 10 is controllable, the interpolation filter 12 can be omitted.

When the sampling frequency of the A/D converter 10 is uncontrollable, the interpolation filter 12 can be used to effect the conversion of the sampling frequency. The adjusted sample frequency offset is input to the interpolation filter 12, and the interpolation filter 12 performs interpolation processing on the sampling sequence according to the sampling frequency offset value to realize synchronization of the sampling frequency and phase.

Of course, when the sampling frequency of the A/D converter 10 is controllable, the interpolation filter 12 can also be reserved, and the adjusted sampling frequency offset can be input to the interpolation filter 12, and the interpolation filter 12 is based on the sampling frequency offset value. The sampling sequence is interpolated to synchronize the sampling frequency and phase.

In one embodiment, the sampling clock synchronization device of the present invention may further include a segmentation module (not shown) and a noise reduction module 20. The segmentation module can be connected between the synchronization header extraction module 14 and the early-morning gate module 16 and between the local synchronization header extraction module 18 and the late-morning gate module 16, for synchronizing the header sequence output by the synchronization header extraction module 14 and the local synchronization header. The sequence of local synchronization headers output by the sequence generation module 18 performs corresponding segmentation.

The purpose of segmentation is to combat the effects of noise interference and carrier frequency offset. The length of each segment and the number of segments can be traded off based on the noise interference strength and carrier frequency offset values that are required to be combated.

The noise reduction module 22 is used for performing mean calculation or filtering on a plurality of sampling errors corresponding to segments in a signal frame outputted by the early and late gate modules. Through the method of mean calculation or filtering, the sampling error is denoised, and a more accurate sampling error value can be obtained.

In one embodiment, the noise reduction module 20 can also be used to perform mean calculation or filtering on sampling errors corresponding to multiple signal frames to further improve the accuracy of the sampling error.

Hereinafter, the present invention will be described in detail in conjunction with specific embodiments.

For example, in the digital satellite broadcasting system of this embodiment, the clock frequency of the system is 30 MHz. The length of the signal frame is 300000 points, which consists of a sync header and a signal body. The synchronization header Κν(«) has a length of 18432 points and is generated by a pseudo-random sequence PN («) after binary phase shift keying (BPSK) constellation mapping.

SYN(n) = \ - 2 x PN(n), k = 0,\, 2,18431

The pseudo-random sequence W («) is generated by the pseudo-random sequence generator shown in Figure 4, generating a polynomial For x ¹⁵ +x ¹² +x ^u +x ⁹ +x ⁷ +x ⁵ +x ² +l, the initial value of the shift register is 101010100101010. The shift clock of the pseudo-random sequence generator is synchronized with the system clock and has the same frequency. At the beginning of each signal frame sync header, the shift register is reset to its initial value.

Implementation steps

1, oversampling

The A/D converter 10 is used to perform a three-times over-sampling of the received continuous signal to obtain an oversampling sequence where the sampling frequency of the A/D is uncontrollable.

It will be apparent to those skilled in the art that the oversampling factor is not limited to three times the specific embodiment, and the present invention may employ any multiple greater than one.

2, interpolation filter

The interpolation filter uses a Farrow filter. The interpolation method uses second-order parabolic interpolation. The four filter coefficients are = 0.5^„ ² - 0.5μ _η , Co = - .5μ _η ² - .5μ„ + 1, C, = - .5μ _η ² + \.5μ _η , C ₂ = .5μ _η ² - .5μ _η . The interpolation filter 12 interpolates the oversampled sequence s (A) according to the sampling frequency offset value to obtain an oversampled sequence r(k) after the sampling frequency conversion.

Here, the sampling frequency offset value is the value outputted by the sampling frequency offset adjusting module 22 of Fig. 2. Of course, in the initial stage, the sampling frequency offset value can be set to zero.

3, synchronization header extraction and segmentation

According to the signal frame structure of the digital satellite system and the position of the synchronization header, the synchronization header extraction module 14 extracts the synchronization header sequence in the oversampled sequence after the sampling frequency transformation, and is combined with the segmentation module (not shown) to be divided into certain The number of segments, here is an example of six segments. Thus, each sequence has a length of 3x3076 points, which is denoted by ( , / = 0,1,2,...,5, A: = 0,1,2, ..., 9227.

Such segmentation can combat 20 dB of noise interference and a few KHz carrier frequency offsets.

4, local synchronization header sequence generation

According to the signal frame structure of the digital satellite system, the local sync header sequence generating module 18 generates a local sync header sequence >S}W(«). Correspondingly, the local synchronization header sequence is divided into 6 segments by a segmentation module (not shown). The length of each sequence is 3076 points, denoted as SKV,.(«), / = 0,1,2,...,5, "= 0,1, .."3075.

5, sooner or later Sooner or later, the gate module 16 obtains a single tweeted early door signal p _e («) and a late gate signal / ? / («) by delay and 3 times downsampling.

/ ") = (3x"), " = 0,1,2,L ,3075

A(") = ( ^3x "— ² ), " = 0,1,2,L,3075

The sooner or later gate module 16 and the early gate signal and the late gate signal are respectively correlated with the corresponding local sync header sequence according to the following formula:

& ⁼ ∑: ⁷ (") , (")

=∑D ) , (")

Also, find the first norm for the cross-correlation values & and & respectively:

α,. =|^a/(S _e )| + |zwag(S _e )|

b _i =| real(S,) | + 1 imagiS,)]

Among them, the function rea / () means to take the real part, which means to take the imaginary part. The sampling error can be obtained from the symmetry of b and .

Of course, the above α, . and b,. may also have other expressions, such as the square root of & and &.

The sampling error can also be expressed as other forms such as the difference between α, . and b, . The present invention is not limited to this specific embodiment.

6, noise reduction

Then, the noise reduction module 20 averages the six sampling error values in one signal frame to obtain a more accurate sampling error value e.

In order to obtain a more accurate sampling error value, the noise reduction module 20 can further average the sampling error values in the plurality of signal frames.

7, sampling frequency adjustment

The sampling frequency offset adjustment module 22 dynamically adjusts the sampling frequency offset value according to the sampling error e. For example, if |e| is less than the threshold Γ (the threshold Γ can be in the range of 0~1, those skilled in the art It can be set according to the actual system requirements. If r= oi is used here, the sampling frequency offset s is not adjusted. If I e I is greater than the threshold T, the sampling frequency offset Δ / ₅ is first based on the original value to perform a temporary coarse realization of the sampling phase synchronization:

Among them, the superscript is the adjustment number, which is the coarse adjustment value, which is a function proportional to the sampling error e. Here, the piecewise function can be taken:

Of course, Δ/O) can also be expressed as a continuous function proportional to the sampling error e.

After a certain period of time, for example, taking a signal frame, the sampling frequency offset is restored to the original value of 4 s, and then a permanent fine adjustment is performed on the basis of the original value, and the Farrow filter 12 is controlled to realize the sampling frequency. Synchronize:

Where Δ / _Μ is a fine adjustment value, and the value of Δ / _Μ can be appropriately set by a person skilled in the art according to actual system requirements. For example, take Δ/ _Μ = 0.05 ρρηι. Considering that the entire sampling frequency offset adjustment loop may have a certain delay, it may wait for a certain time after performing the sample frequency offset fine adjustment, for example, taking two signal frames.

When the signal-to-noise ratio of the received signal is -20 dB, the carrier frequency offset is 3 KHz, and the frequency stability of the A/D converter 10 is 1 ppm, the sampling error value after 200 sampling frequency offset adjustment is shown in Fig. 5. Shown. It can be seen that the sampling frequency offset adjustment loop can reach a steady state after 50 sampling frequency offset adjustments (about 1.5 seconds). After reaching a steady state, the sampling error can be basically controlled within 0.1 (less than 0.1 sampling points). This demonstrates that the method and apparatus of the present invention enable fast and accurate sampling frequency and phase synchronization and can combat high intensity noise interference and large carrier frequency offset values.

The present invention is applicable to various digital broadcasting systems such as digital satellite broadcasting and digital terrestrial broadcasting, and various parameters involved in the present invention can be flexibly configured according to different systems. While the embodiments of the present invention have been shown and described, it will be understood by those skilled in the art The scope of the invention is defined by the appended claims and their equivalents.

Claims

Claim

A sampling clock synchronization method, characterized in that the method comprises the following steps:

(a) oversampling the received continuous signal using an analog-to-digital (A/D) converter to obtain an oversampled sequence;

(b) performing interpolation processing on the oversampled sequence by using an interpolation filter to obtain an oversampled sequence after sampling frequency conversion;

(c) extracting a synchronization header sequence from the oversampled sequence after the sampling frequency transformation according to the signal frame structure and the position of the synchronization header;

(d) generating a local sync header sequence based on the signal frame structure;

(e) obtaining an early gate signal and a late gate signal by delaying and downsampling the synchronization header sequence, and cross-correlating the local synchronization header sequence with the early gate signal and the late gate signal respectively, according to The symmetry of the cross-correlation value is obtained by sampling error;

(f) The current sampling frequency offset is adjusted according to the sampling error, and the adjusted sampling frequency offset is obtained and input to the A/D converter or the interpolation filter for sampling frequency and phase synchronization.

The method according to claim 1, wherein when the A/D converter is controllable, step b is omitted, and in step f, the adjusted sampling frequency offset is input to the A/D In the converter.

3. The method according to claim 1, wherein the formula for obtaining the early gate signal and the late gate signal by delaying and downsampling the synchronization header sequence is:

p _e (n) = q(M xn), " = 0,1, 2,L , N— \

p,(n) = q(M x n - m), " = 0,1,2,L , N - \

Where (A:) is the synchronization header sequence, /7 _e («) and the early gate signal and the late gate signal respectively, M is the downsampling multiple, m is the delay point number, and N is the synchronization header sequence length;

The formula for mutually correlating the local sync header sequence with the early gate signal and the late gate signal is:

Where («) is the local sync header sequence, and & and respectively are the local sync header sequences respectively Cross-correlation values with the early gate signal and the late gate signal;

The formula for obtaining the sampling error according to the symmetry of the cross-correlation value is:

a=\real(S _e )\ + \imag(S _e )\

b^realiS^l + imagiS,)]

A-b

e =

a + b

Among them, the function represents the real part, imag ( ) means the imaginary part, and e is the sampling error.

4. The method according to claim 1, wherein the step of adjusting the current sampling frequency offset comprises:

Performing a temporary coarse adjustment on the current sampling frequency offset to control the synchronization of the sampling phase;

A permanent fine adjustment of the current sampling frequency offset after a predetermined time is used to control the synchronization of the sampling frequency.

5. The method of claim 4 wherein the temporary coarse adjustment formula is:

Where, for the sampling frequency offset, _ is the adjustment number, e is the sampling error, and is the coarse adjustment value, and ΔΛ(β) is the piecewise function or continuous function of the sampling error e.

6. The method of claim 4 wherein the permanent fine tuning formula is:

_Δ /·") ₌ { ^Δ /" + Α , ^{E > 0} where Δ is the sampling frequency offset, y' is the number of adjustments, e is the sampling error, and 4/M is the fine adjustment value.

7. The method according to claim 1, further comprising, after step c, segmenting the synchronization header sequence and correspondingly segmenting the local synchronization header sequence generated by step d.

The method according to claim 7, wherein after step e, the method further comprises: performing mean calculation or filtering on the plurality of sampling errors corresponding to the segmentation in a signal frame, for performing noise reduction on the sampling error .

9. The method according to claim 8, further comprising performing a mean calculation or filtering on sampling errors corresponding to the plurality of signal frames.

10. A sampling clock synchronization device, characterized in that the device comprises:

An A/D converter, the A/D converter oversampling the received continuous signal to obtain an oversampling sequence;

An interpolation filter, wherein the interpolation filter performs interpolation processing on the oversampled sequence to obtain an oversampled sequence after sampling frequency conversion;

a synchronization header extraction module, wherein the synchronization header extraction module extracts a synchronization header sequence from the oversampled sequence after the sampling frequency transformation according to the signal frame structure and the position of the synchronization header;

a local synchronization header sequence generation module, where the local synchronization header sequence generation module generates a local synchronization header sequence according to the signal frame structure;

a sooner or later gate module, the delay gate module delays and downsamples the synchronization header sequence to obtain an early gate signal and a late gate signal, and respectively the local synchronization header sequence and the early gate signal and the late gate signal Performing cross-correlation, obtaining sampling error according to the symmetry of the cross-correlation value; sampling frequency offset adjusting module, the sampling frequency offset adjusting module adjusts the current sampling frequency offset according to the sampling error, and obtains the adjusted sampling frequency offset and inputs Sample frequency and phase synchronization are performed in the A/D converter or filter.

The device according to claim 10, wherein when the A/D converter is controllable, the interpolation filter is omitted, and the sampled frequency offset adjustment module adjusts the sampled frequency offset input to In the A/D converter.

12. The apparatus according to claim 10, wherein the sampling frequency offset adjustment module comprises:

a coarse adjustment unit, wherein the coarse adjustment unit performs a temporary coarse adjustment on the current sampling frequency offset for controlling synchronization of the sampling phase;

a micro-adjusting unit that performs a permanent fine adjustment on the current sampling frequency offset after a predetermined time for controlling synchronization of the sampling frequency.

13. The device according to claim 10, further comprising:

a segmentation module, wherein the segmentation module performs corresponding segmentation on a synchronization header sequence output by the synchronization header extraction module and a local synchronization header sequence output by the local synchronization header sequence generation module; and

a noise reduction module, the noise reduction module segments the signal frame of the early and late gate module output After the corresponding multiple sampling errors are averaged or filtered for noise reduction of the sample error.

The device according to claim 13, wherein the noise reduction module is further configured to perform mean calculation or filtering on sampling errors corresponding to the plurality of signal frames.

The device according to claim 10, wherein when the A/D converter is controllable, the adjusted frequency offset of the sampling frequency offset adjustment module is input to the interpolation filter.

16. The apparatus according to claim 10, wherein when the A/D converter is uncontrollable, the adjusted sampling frequency offset of the sampling frequency offset adjustment module is input to the interpolation filter.