CN105323056B - bit synchronization method and device - Google Patents
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- CN105323056B CN105323056B CN201410323166.7A CN201410323166A CN105323056B CN 105323056 B CN105323056 B CN 105323056B CN 201410323166 A CN201410323166 A CN 201410323166A CN 105323056 B CN105323056 B CN 105323056B
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Abstract
The invention discloses a kind of bit synchronization method and devices.This method includes：It is sampled by AD and obtains initial data a (n), symbol data streams x (n) is obtained after handling the initial data, wherein x (n) is real number, and n is natural number；Two-value judgement is carried out to the x (n), it is configured to data flow xd (n), input signal by the data flow xd (n) as the filter H (n) constructed in advance carries out matched filtering, obtains output signal y (n)；One threshold value is set, when y (n) is less than or equal to the threshold value, without processing, when y (n) is more than the threshold value, the peak value for finding y (n), determines the transition edges edge of symbolic information at the time of according to corresponding to the peak value；The optimum sampling moment of successive character position is determined according to the transition edges, and sampling of data, processing are carried out to the follow-up data of same data frame at the optimum sampling moment.
Description
Technical field
The present invention relates to communication fields, more particularly to a kind of bit synchronization method and device.
Background technology
The purpose of bit synchronization is that each code element is made to obtain best demodulation judgement.Bit synchronization can be divided into external synchronization method and
Self-synchronizing method two major classes：External synchronization method needs in addition special transmission bit synchronization information；Motor synchronizing rule is carried from signal element
Take it includes bit synchronization information.In general, self-synchronizing method is using more.
In the prior art, self-synchronizing method can be divided into two kinds, i.e. open loop Synchronos method and closed-loop synchronization method again.Open loop method is adopted
Bit synchronization information is extracted with the method that input symbols are done with certain transformation.Closed loop rule is with comparing local clock and input signal
Method, on the input signals by local clock locking.Closed loop method is more accurate, but also increasingly complex.Bit synchronization inaccuracy will
The bit error rate is caused to increase.
Bit synchronization system is one of the important component in modern age electronic information communication, while also in other many fields
Middle extensive use.Bit synchronization, which ensures to receive and dispatch in system, to be synchronized, and is ensureing to obtain frame synchronization, group synchronization and to the number of reception
Symbol carries out the synchronous of various processing and carries out, and the synchronised clock of a benchmark is also provided for system.Also, accurate bit synchronization
Help to improve the noise resisting ability of reception system.
Invention content
In view of the above problems, it is proposed that the present invention overcoming the above problem in order to provide one kind or solves at least partly
State the bit synchronization method and device of problem.
The present invention provides a kind of bit synchronization method, including：By AD sample obtain initial data a (n), to initial data into
Symbol data streams x (n) is obtained after row processing, wherein x (n) is real number, and n is natural number；Two-value judgement is carried out to x (n), is configured to
Data flow xd (n), the input signal by data flow xd (n) as the filter H (n) constructed in advance carry out matched filtering, obtain
Output signal y (n)；One threshold value is set, when y (n) is less than or equal to threshold value, without processing, when y (n) is more than thresholding
When value, the peak value of y (n), n at the time of according to corresponding to peak value are foundpeakDetermine the transition edges edge of symbolic information, i.e. edge
=npeak；The optimum sampling moment of successive character position is determined according to transition edges, and at the optimum sampling moment to same data frame
Follow-up data carry out data pick-up.
Preferably, the method for construction filter H (n) specifically includes：The binary system PN sequences of data frame frame head are run end to end
, each bit is repeated M times, then 1 in repeatedly M times of each bit is mapped as 1,0 and is mapped as -1, wherein M is
The sampling number of each symbol, M=Fs/Fb, fs are digital display circuit sample rate, and fb is symbol rate.
Preferably, two-value judgement is carried out to x (n), is configured to data flow xd (n) and specifically includes：
When x (n) is more than 0, xd (n)=1；When x (n) is less than or equal to 0, xd (n)=- 1；
Obtaining output signal y (n) is specially：Y (n)=∑ H (i) * xd (n-i), wherein 1≤i≤M*D, D are data frame
The length of PN sequences in frame head, M are the sampling number of each symbol, and M=Fs/Fb, fs are digital display circuit sample rate, and fb is symbol
Rate.
Preferably, a threshold value is arranged to specifically include：Threshold value is set according to numerical value M*D/2, wherein D is data frame
The length of PN sequences in frame head, M are the sampling number of each symbol, and M=Fs/Fb, fs are digital display circuit sample rate, and fb is symbol
Rate.
Preferably, the optimum sampling moment of successive character position is determined according to transition edges edge, and at the optimum sampling moment
Data pick-up is carried out to the follow-up data of same data frame, is specifically included：The optimal sampling moment of successive character position is n=k*M/
2+edge, wherein k=1,2,3 ..., edge are transition edges；To the follow-up data of same data frame with x (k*M/2+edge) into
Row data pick-up.
The present invention also provides a kind of bit synchronizers, including：Sampling module obtains initial data for being sampled by AD
A (n) obtains symbol data streams x (n) after handling initial data, wherein x (n) is real number, and n is natural number；Binaryzation mould
Block is configured to data flow xd (n) for carrying out two-value judgement to x (n)；Filter module, it is pre- for data flow xd (n) to be used as
The input signal of the filter H (n) first constructed carries out matched filtering, obtains output signal y (n)；Peak searching module, for being arranged
One threshold value finds the peak of y (n) without processing when y (n) is less than or equal to threshold value when y (n) is more than threshold value
Value, determines the transition edges of symbolic information at the time of according to corresponding to peak value；Decimation blocks, after being determined according to transition edges
The optimum sampling moment of continuous sign bit, and data pick-up is carried out to the follow-up data of same data frame at the optimum sampling moment.
Preferably, above-mentioned apparatus further comprises：Filter constructing module, for constructing filter H (n)：By data frame
The binary system PN sequences of frame head overturn end to end, each bit are repeated M times, then 1 in repeatedly M times of each bit is reflected
Penetrate is 1,0 to be mapped as -1, wherein M is the sampling number of each symbol, and M=Fs/Fb, fs are digital display circuit sample rate, and fb is symbol
Number rate.
Preferably, binarization block is specifically used for：When x (n) is more than 0, xd (n)=1；When x (n) is less than or equal to 0, xd
(n)=- 1；Filter module is specifically used for：Obtaining output signal y (n) is specially：Y (n)=∑ H (i) * xd (n-i), wherein 1≤
I≤M*D, D are the length of PN sequences in data frame frame head, and M is the sampling number of each symbol, and M=Fs/Fb, fs are that number is
System sample rate, fb is symbol rate.
Preferably, peak searching module is specifically used for：Threshold value is set according to numerical value M*D/2, wherein D is in data frame frame head
The length of PN sequences, M are the sampling number of each symbol, and M=Fs/Fb, fs are digital display circuit sample rate, and fb is symbol rate.
Preferably, decimation blocks are specifically used for：The optimal sampling moment of successive character position is n=k*M/2+edge, wherein k
=1,2,3 ..., edge are transition edges；Data pick-up is carried out with x (k*M/2+edge) to the follow-up data of same data frame.
The present invention has the beneficial effect that：
By means of the technical solution of the embodiment of the present invention, fine correction is carried out by using the autocorrelation performance of PN sequences,
It with higher anti-noise ability, and can realize finely positioning, be a kind of simple, practical to be suitable for Digital Signal Processing
Open loop motor synchronizing mode.
Above description is only the general introduction of technical solution of the present invention, in order to better understand the technical means of the present invention,
And can be implemented in accordance with the contents of the specification, and in order to allow above and other objects of the present invention, feature and advantage can
It is clearer and more comprehensible, below the special specific implementation mode for lifting the present invention.
Description of the drawings
By reading the detailed description of hereafter preferred embodiment, various other advantages and benefit are common for this field
Technical staff will become clear.Attached drawing only for the purpose of illustrating preferred embodiments, and is not considered as to the present invention
Limitation.And throughout the drawings, the same reference numbers will be used to refer to the same parts.In the accompanying drawings：
Fig. 1 is the flow chart of the bit synchronization method of the embodiment of the present invention；
Fig. 2 is the processing flow schematic diagram of the bit synchronization method of present example；
Fig. 3 is the result waveform diagram of the analog simulation of the embodiment of the present invention；
Fig. 4 is the partial enlarged view of Fig. 3；
Fig. 5 is the structural schematic diagram of the bit synchronizer of the embodiment of the present invention.
Specific implementation mode
The exemplary embodiment of the disclosure is more fully described below with reference to accompanying drawings.Although showing the disclosure in attached drawing
Exemplary embodiment, it being understood, however, that may be realized in various forms the disclosure without should be by embodiments set forth here
It is limited.On the contrary, these embodiments are provided to facilitate a more thoroughly understanding of the present invention, and can be by the scope of the present disclosure
Completely it is communicated to those skilled in the art.
The present invention provides a kind of relatively easy, practical, pseudorandom (Pseudo-noise, referred to as PN) sequence is utilized
Autocorrelation performance does the open loop motor synchronizing method that fine correction, anti-noise ability are relatively strong, are suitable for Digital Signal Processing, it ties below
Attached drawing and embodiment are closed, the present invention will be described in further detail.It should be appreciated that specific embodiment described herein is only
Only to explain the present invention, the present invention is not limited.
Embodiment of the method
According to an embodiment of the invention, a kind of bit synchronization method is provided, Fig. 1 is the bit synchronization method of the embodiment of the present invention
Flow chart, as shown in Figure 1, bit synchronization method according to the ... of the embodiment of the present invention includes following processing：
Step 101, it is sampled by AD and obtains initial data a (n), symbol data streams are obtained after handling initial data
X (n), wherein x (n) are real number, and n is natural number；
Step 102, two-value judgement is carried out to x (n), is configured to data flow xd (n), regard data flow xd (n) as advance structure
The input signal of the filter H (n) made carries out matched filtering, obtains output signal y (n)；
Wherein, the method for construction filter H (n) specifically includes：The binary system PN sequences of data frame frame head are overturned end to end,
Each bit is repeated M times, then 1 in repeatedly M times of each bit is mapped as 1,0 and is mapped as -1, wherein M is every
The sampling number of a symbol, M=Fs/Fb, fs are digital display circuit sample rate, and fb is symbol rate.
In a step 102, two-value judgement is carried out to x (n), is configured to data flow xd (n) and specifically includes：
When x (n) is more than 0, xd (n)=1；When x (n) is less than or equal to 0, xd (n)=- 1；
Obtaining output signal y (n) is specially：Y (n)=∑ H (i) * xd (n-i), wherein 1≤i≤M*D, D are data frame
The length of PN sequences in frame head, M are the sampling number of each symbol, and M=Fs/Fb, fs are digital display circuit sample rate, and fb is symbol
Rate.
Step 103, a threshold value is set, when y (n) is less than or equal to threshold value, without processing, when y (n) is more than door
When limit value, the peak value of y (n), n at the time of according to corresponding to peak value are foundpeakDetermine the transition edges edge of symbolic information, i.e.,
Edge=npeak；In step 103, a threshold value is arranged to specifically include：
Threshold value is set according to numerical value M*D/2, wherein D is the length of PN sequences in data frame frame head, and M is each symbol
Sampling number, M=Fs/Fb, fs be digital display circuit sample rate, fb is symbol rate.
Step 104, the optimum sampling moment of successive character position is determined according to transition edges edge, and at the optimum sampling moment
Sampling of data is carried out to subsequent data frame.
Step 104 specifically includes following processing：
The optimal sampling moment of successive character position is n=k*M/2+edge, and wherein k=1,2,3 ..., edge are saltus step side
Edge；
Sampling of data is carried out with x (k*M/2+edge) to the follow-up data of same data frame.
Below in conjunction with attached drawing, the above-mentioned technical proposal of the embodiment of the present invention is described in detail.
Assuming that digital display circuit sample rate is fs hertz (Hz), symbol rate is fb bps, fbs of the fs at least more than 10 times,
A then symbol period Tb=1/fb, unit are the second.The sampling number that each symbol includes is M, and M=Fs/Fb is (general to take M
For even number).
Assuming that data are to transmit (burst mode or continuation mode all can) by frame.It is made of frame head and content frame per frame,
Frame head is the binary system PN sequences that length known to one is D (D generally takes 32,40 or 64 bit lengths).
Before handling data, matched filter H (n) is first constructed.Building method is：PN sequences above-mentioned are run end to end
, then each bit repeats M times, then is mapped as 1,0 by 1 and is mapped as -1.
It illustrating, it is assumed that D=4, M=4, PN sequence are 1011, are inverted as 1101 end to end, and it is 1111 to repeat 4 times,
1111,0000,1111, it is mapped as 1111,1111, -1-1-1-1,1111, this is the coefficient of H (n).
Data processing is carried out after construction matched filter.
Fig. 2 is the processing flow schematic diagram of the bit synchronization method of present example, as shown in Fig. 2, processing step is specifically wrapped
It includes：
1), the initial data a (n) that AD samplings obtain becomes symbol data streams x after the processing such as frequency conversion, filtering, demodulation
(n), wherein x (n) is real number, and n is sequence number 1,2,3,4 ....
2) x (n), is done into the judgement of 2 values, constitutes new data flow xd (n).Decision rule is：When x (n) is more than 0, xd (n)
=1；When x (n) is less than or equal to 0, xd (n)=- 1.
3), matched filtering.The value range of y (n)=∑ H (i) * xd (n-i), i are from 1 to M*D.Fig. 3 is of the invention real
The result waveform diagram of the analog simulation of example is applied, Fig. 4 is the partial enlarged view of Fig. 3, as shown in Figure 3,4, the upper column wave in figure
Shape is xd (n), and lower column waveform is filtering output y (n).
4), peak-seeking is adjudicated.When input signal is matched with H (n), y (n) is the peak value close to M*D, so decision rule is such as
Under：The value of threshold value a Y, Y are set near M*D/2, when y (n) is less than or equal to Y, is not processed, when y (n) is more than Y
Later, its peak value is found, n at the time of corresponding to peak valuepeakThe as transition edges edge of symbolic information, i.e. edge=npeak。
5), bit synchronization.N=k*M/2+edge is the optimum sampling moment of subsequent sign bit, wherein k=1, and 2,3 ....With
Content frame afterwards all carrys out gathered data with x (k*M/2+edge), and does subsequent processing.
By analog simulation and the test of practical open channel, when using PN sequence correlations, correlation is close to maximum value M*
D, and it is uncorrelated when fall to the property under M*D/2 rapidly to do bit synchronization positioning, effect is fine.Also can when noise is larger
Reliably PN sequences are detected, to obtain bit synchronization information.
In general, PN sequences are longer, antimierophonic ability is stronger, but the digit and operand that occupy also accordingly increase.
So according to the signal-to-noise ratio of actual channel, to select the PN sequences of suitable length and threshold value Y appropriate, specific field can be met
The demand of conjunction is also unlikely to occupy too many resource, is only optimal selection.
Device embodiment
According to an embodiment of the invention, a kind of bit synchronizer is provided, Fig. 5 is the bit synchronizer of the embodiment of the present invention
Structural schematic diagram, as shown in figure 5, bit synchronizer according to the ... of the embodiment of the present invention includes：
Sampling module 50 obtains initial data a (n) for being sampled by AD, symbol is obtained after handling initial data
Number stream x (n), wherein x (n) are real number, and n is natural number；
Binarization block 51 is configured to data flow xd (n) for carrying out two-value judgement to x (n)；Binarization block 51 has
Body is used for：When x (n) is more than 0, xd (n)=1；When x (n) is less than or equal to 0, xd (n)=- 1；
Filter module 52, for the input signal by data flow xd (n) as the filter H (n) constructed in advance, progress
With filtering, output signal y (n) is obtained；Filter module 52 is specifically used for：Obtaining output signal y (n) is specially：Y (n)=∑ H
(i) * xd (n-i), wherein 1≤i≤M*D, D are the length of PN sequences in data frame frame head, and M is the sampling number of each symbol,
M=Fs/Fb, fs are digital display circuit sample rate, and fb is symbol rate.
Peak searching module 53, when y (n) is less than or equal to threshold value, without processing, works as y for a threshold value to be arranged
(n) when being more than threshold value, the peak value of y (n) is found, the transition edges of symbolic information are determined at the time of according to corresponding to peak value
edge；Peak searching module 53 is specifically used for：Threshold value is set according to numerical value M*D/2, wherein D is PN sequences in data frame frame head
Length, M are the sampling number of each symbol, and M=Fs/Fb, fs are digital display circuit sample rate, and fb is symbol rate.
Decimation blocks 54, the optimum sampling moment for determining successive character position according to transition edges edge, and best
Sampling instant carries out sampling of data to the follow-up data of same data frame.Decimation blocks 54 are specifically used for：Successive character position is most
Good sampling time is n=k*M/2+edge, and wherein k=1,2,3 ..., edge are transition edges；To the follow-up number of same data frame
X (k*M/2+edge) carries out sampling of data according to this.
Preferably, above-mentioned apparatus further comprises：
Filter constructing module, for constructing filter H (n)：The binary system PN sequences of data frame frame head are overturned end to end,
Each bit is repeated M times, then 1 in repeatedly M times of each bit is mapped as 1,0 and is mapped as -1, wherein M is every
The sampling number of a symbol, M=Fs/Fb, fs are digital display circuit sample rate, and fb is symbol rate.
In conclusion by means of the technical solution of the embodiment of the present invention, carried out by using the autocorrelation performance of PN sequences
Fine correction has higher anti-noise ability, and can realize finely positioning, is a kind of simple, practical to be suitable for number
The open loop motor synchronizing mode of signal processing.
Obviously, various changes and modifications can be made to the invention without departing from essence of the invention by those skilled in the art
God and range.In this way, if these modifications and changes of the present invention belongs to the range of the claims in the present invention and its equivalent technologies
Within, then the present invention is also intended to include these modifications and variations.
Claims (8)
1. a kind of bit synchronization method, which is characterized in that including：
It is sampled by AD and obtains initial data a (n), symbol data streams x (n) is obtained after handling the initial data,
Middle x (n) is real number, and n is natural number；
Two-value judgement is carried out to the x (n), is configured to data flow xd (n), by the data flow xd (n) as constructing in advance
The input signal of filter H (n) carries out matched filtering, obtains output signal y (n)；
One threshold value is set, when y (n) is less than or equal to the threshold value, without processing, when y (n) is more than the threshold value
When, the peak value of y (n) is found, the transition edges edge of symbolic information is determined at the time of according to corresponding to the peak value；
The optimum sampling moment of successive character position is determined according to the transition edges, and at the optimum sampling moment to same number
Sampling of data is carried out according to the follow-up data of frame；
Wherein, the method for construction filter H (n) specifically includes：
The binary system PN sequences of data frame frame head are overturned end to end, each bit are repeated M times, then each of M times will be repeated
1 in bit, which is mapped as 1,0, is mapped as -1, wherein M is the sampling number of each symbol, and M=Fs/Fb, Fs are digital display circuit
Sample rate, Fb are symbol rate.
2. the method as described in claim 1, which is characterized in that
Two-value judgement is carried out to the x (n), data flow xd (n) is configured to and specifically includes：
When x (n) is more than 0, xd (n)=1；When x (n) is less than or equal to 0, xd (n)=- 1；
Obtaining output signal y (n) is specially：Y (n)=∑ H (i) * xd (n-i), wherein 1≤i≤M*D, D are data frame frame head
The length of middle PN sequences, M are the sampling number of each symbol, and M=Fs/Fb, Fs are digital display circuit sample rate, and Fb is symbol rate.
3. the method as described in claim 1, which is characterized in that one threshold value of setting specifically includes：
The threshold value is set according to numerical value M*D/2, wherein D is the length of PN sequences in data frame frame head, and M is each symbol
Sampling number, M=Fs/Fb, Fs be digital display circuit sample rate, Fb is symbol rate.
4. the method as described in claim 1, which is characterized in that determine successive character position most according to the transition edges edge
Good sampling instant, and data acquisition is carried out to the follow-up data of same data frame at the optimum sampling moment and is specifically included：
The optimum sampling moment of successive character position is n=k*M/2+edge, and wherein k=1,2,3 ..., edge are the saltus step side
Edge；
Data pick-up is carried out with x (k*M/2+edge) to the follow-up data of same data frame.
5. a kind of bit synchronizer, which is characterized in that including：
Sampling module obtains initial data a (n) for being sampled by AD, symbol is obtained after handling the initial data
Data flow x (n), wherein x (n) are real number, and n is natural number；
Binarization block is configured to data flow xd (n) for carrying out two-value judgement to the x (n)；
Filter module is matched for the input signal by the data flow xd (n) as the filter H (n) constructed in advance
Filtering obtains output signal y (n)；
Peak searching module, for a threshold value to be arranged, when y (n) is less than or equal to the threshold value, without processing, as y (n)
When more than the threshold value, the peak value of y (n) is found, the saltus step side of symbolic information is determined at the time of according to corresponding to the peak value
Along edge；
Decimation blocks, the optimum sampling moment for determining successive character position according to the transition edges, and most preferably adopted described
The sample moment carries out data pick-up to the follow-up data of same data frame；
Filter constructing module, for constructing filter H (n)：The binary system PN sequences of data frame frame head are overturned end to end, it will be every
A bit repeats M times, then is mapped as 1,0 by repeat in M times of each bit 1 and is mapped as -1, wherein M is each to accord with
Number sampling number, M=Fs/Fb, Fs be digital display circuit sample rate, Fb is symbol rate.
6. device as claimed in claim 5, which is characterized in that
Binarization block is specifically used for：When x (n) is more than 0, xd (n)=1；When x (n) is less than or equal to 0, xd (n)=- 1；
Filter module is specifically used for：Obtaining output signal y (n) is specially：Y (n)=∑ H (i) * xd (n-i), wherein 1≤i≤
M*D, D are the length of PN sequences in data frame frame head, and M is the sampling number of each symbol, and M=Fs/Fb, Fs adopt for digital display circuit
Sample rate, Fb are symbol rate.
7. device as claimed in claim 5, which is characterized in that peak searching module is specifically used for：According to numerical value M*D/2 settings
Threshold value, wherein D is the length of PN sequences in data frame frame head, and M is the sampling number of each symbol, and M=Fs/Fb, Fs are number
Type families system sample rate, Fb is symbol rate.
8. device as claimed in claim 5, which is characterized in that decimation blocks are specifically used for：
The optimal sampling moment of successive character position is n=k*M/2+edge, and wherein k=1,2,3 ..., edge are the saltus step side
Edge；
Data pick-up is carried out with x (k*M/2+edge) to the follow-up data of same data frame.
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|---|---|---|---|---|
| JP2011229131A (en) * | 2010-03-31 | 2011-11-10 | Fujitsu Ten Ltd | Synchronous timing reproducing device, data transfer device, antenna device, and head unit |
| CN102377715A (en) * | 2010-08-12 | 2012-03-14 | 北京泰美世纪科技有限公司 | Method and apparatus for sampling clock synchronization |
| CN102497240A (en) * | 2011-12-20 | 2012-06-13 | 北京泰美世纪科技有限公司 | Sampling synchronous device and sampling synchronous method of digital broadcasting system |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2011229131A (en) * | 2010-03-31 | 2011-11-10 | Fujitsu Ten Ltd | Synchronous timing reproducing device, data transfer device, antenna device, and head unit |
| CN102377715A (en) * | 2010-08-12 | 2012-03-14 | 北京泰美世纪科技有限公司 | Method and apparatus for sampling clock synchronization |
| CN102497240A (en) * | 2011-12-20 | 2012-06-13 | 北京泰美世纪科技有限公司 | Sampling synchronous device and sampling synchronous method of digital broadcasting system |
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