CN105978777B - A kind of Waveform storage method and device - Google Patents
A kind of Waveform storage method and device Download PDFInfo
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- CN105978777B CN105978777B CN201610472132.3A CN201610472132A CN105978777B CN 105978777 B CN105978777 B CN 105978777B CN 201610472132 A CN201610472132 A CN 201610472132A CN 105978777 B CN105978777 B CN 105978777B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L12/40006—Architecture of a communication node
- H04L12/40013—Details regarding a bus controller
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L12/40169—Flexible bus arrangements
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L2012/40208—Bus networks characterized by the use of a particular bus standard
- H04L2012/40215—Controller Area Network CAN
Abstract
This application provides a kind of Waveform storage methods, comprising: samples to the Wave data in CAN bus, and each Wave data that sampling obtains is converted to logic level signal；When being continuously available multiple logic level signals characterization CAN bus and be in Idle state, detect in subsequent obtained logic level signal with the presence or absence of frame start signal；When detecting frame start signal, the corresponding Wave data of frame start signal is stored.Method provided by the present application converts Wave data to convenient for the logic level signal of detection frame start signal, frame start signal indicates communication waveforms occur in bus, as long as therefore detecting that frame start signal stores the corresponding Wave data of frame start signal after bus is in Idle state, addition controller is not needed to receive CAN message, it does not need addition transceiver to be decoded CAN message to judge whether bus is in communications status, effectively reduces the cost of Waveform storage yet.
Description
Technical field
The present invention relates to the communications fields, more particularly, to a kind of Waveform storage method and device.
Background technique
CAN (Controller Area Network, CAN) is a kind of important kind of fieldbus, since it has height
Performance, high reliability and it is unique design and increasingly receive significant attention, formed international standard, be acknowledged as most
One of promising fieldbus.
One most basic function of the CAN bus of CAN bus analyzer or oscillograph analysis plug-in unit is that record CAN is total
Waveform on line, and subsequent software Decoding Analysis is carried out to waveform.In order to record communication waveforms for a long time as far as possible, and
Make waveform when bus communication as much as possible by complete documentation, it is necessary to which CAN bus analyzer will prop up when stored waveform
Frame triggering technique is held, i.e. the not wave recording in the CAN bus free time, and when occurring CAN frame in bus by this frame Waveform storage
Get off.
Traditional frame triggering technique needs to be added CAN controller and receives to CAN message, it is also necessary to control by CAN
Device decodes the CAN message in bus, then triggers Waveform storage by decoded message, before triggering stored waveform at least
The waveform of 1 frame CAN frame is cached, which needs a large amount of ram in slice resource, improves the cost of waveform in storage CAN bus.
Summary of the invention
The purpose of the present invention is to provide a kind of Waveform storage method and devices, need to only detect after bus is in Idle state
The corresponding Wave data of frame start signal can be stored to frame start signal, not need to be added controller to CAN report
Text is received, and is not also needed addition transceiver and is decoded to CAN message to judge whether bus is in communications status, effectively
Reduce the cost of Waveform storage.
A kind of Waveform storage method, which comprises
Wave data in CAN bus is sampled, and each Wave data that sampling obtains is converted into logic
Level signal；
When being continuously available multiple logic level signals and characterizing the CAN bus and be in Idle state, detection is subsequent to be obtained
It whether there is frame start signal in logic level signal；
When detecting frame start signal, the corresponding Wave data of the frame start signal is stored.
Preferably, the Wave data in CAN bus is acquired, and each Wave data that will be collected
Being converted to logic level signal includes:
The road Wave data Zhong Ge analog signal is compared by default sampling to be sampled；
Decay to per the analog signal described all the way by default decaying rule；
Digital signal will be converted to per the analog signal described all the way through overdamping；
Digital signal described in each road is carried out arithmetic by default algorithmic rule to subtract each other, obtains mathematical difference data all the way；
Each signal data in the mathematical difference data is successively converted into logic level signal.
Preferably, the logic level signal is stealthy position or dominant bit；
It is described be continuously available multiple logic level signals and characterize the CAN bus and be in idle condition include:
The number for the recessive position that detection continuous sampling obtains；
When the number for the recessive position that continuous sampling obtains meets predetermined number requirement, determine that the CAN bus is currently located
In idle state.
Preferably, include: with the presence or absence of frame start signal in the subsequent obtained logic level signal of detection
When determining that the CAN bus is currently at Idle state, first that subsequent acquisition is arrived is the logic of dominant bit
Level signal is determined as frame start signal.
Preferably, after each Wave data that sampling obtains being converted to logic level signal further include:
Interference is carried out to each logic level signal to handle, it is subsequent determining according to multiple logic level signals to guarantee
Whether the CAN bus is in Idle state and detects whether the accuracy there are frame start signal.
A kind of Waveform storage device, described device include:
Sampling module, for being sampled to the Wave data in CAN bus, and each digit wave form number that sampling is obtained
According to being converted to logic level signal；
Detection module, for examining when being continuously available multiple logic level signals and characterizing the CAN bus and be in Idle state
It surveys in subsequent obtained logic level signal with the presence or absence of frame start signal；
Memory module, for being carried out to the corresponding Wave data of the frame start signal when detecting frame start signal
Storage.
Preferably, the sampling module includes:
Submodule is sampled, is sampled for comparing the road Wave data Zhong Ge analog signal by default sampling；
Decaying submodule, for decaying to per the analog signal described all the way by default decaying rule；
First transform subblock, for digital signal will to be converted to per the analog signal described all the way through overdamping；
Acquisition submodule is subtracted each other for digital signal described in each road to be carried out arithmetic by default algorithmic rule, is obtained all the way
Mathematical difference data；
Second transform subblock, for each signal data in the mathematical difference data to be successively converted to logic
Level signal.
Preferably, the logic level signal is recessive position or dominant bit；The detection module includes:
Decision sub-module, for detecting the number for the recessive position that continuous sampling obtains；When the recessive position that continuous sampling obtains
Number when meeting predetermined number requirement, determine that the CAN bus is currently at idle state.
Preferably, the detection module includes:
Determine submodule, first for when determining that the CAN bus is currently at Idle state, subsequent acquisition to be arrived
It is determined as frame start signal for the logic level signal of dominant bit.
Preferably, described device further include:
Interference module is gone, is handled for carrying out interference to each logic level signal, it is subsequent according to multiple to guarantee
Logic level signal determines whether the CAN bus is in Idle state and detects whether the accuracy there are frame start signal.
The above are a kind of Waveform storage methods provided by the invention, sample to the Wave data in CAN bus, and will
It samples each obtained Wave data and is converted to logic level signal；When being continuously available described in multiple logic level signals characterization
When CAN bus is in Idle state, detects and whether there is frame start signal in subsequent obtained logic level signal；When detecting frame
When initial signal, the corresponding Wave data of the frame start signal is stored.
Waveform storage method provided by the invention, each digit wave form that the Wave data in CAN bus will be sampled
Data are converted to logic level signal, by carrying out whether analysis may determine that CAN bus to continuous multiple logic level signals
In Idle state, and subsequent obtained logic level signal is detected after CAN bus is in Idle state and is originated with the presence or absence of frame
Signal.In CAN message structure, frame start signal indicates communication waveforms occur in bus, as long as therefore being in CAN bus
It detects that frame start signal can store the corresponding Wave data of the frame start signal after Idle state, does not need to add
Enter controller to receive CAN message, does not also need addition transceiver and CAN message is decoded to judge whether bus is located
In communications status, the cost of CAN transceiver and controller is saved, while only needing a small amount of ram in slice resource, effectively reduces wave
The cost of shape storage.
Detailed description of the invention
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
The embodiment of invention for those of ordinary skill in the art without creative efforts, can also basis
The attached drawing of offer obtains other attached drawings.
Fig. 1 is a kind of Waveform storage method flow diagram disclosed by the invention；
Fig. 2 is a kind of another method flow diagram of Waveform storage method disclosed by the invention；
Fig. 3 is a kind of another method flow diagram of Waveform storage method disclosed by the invention；
Fig. 4 is a kind of another method flow diagram of Waveform storage method disclosed by the invention；
Fig. 5 is that CAN bus Wave data interference schematic diagram occurs when being converted into logic level signal；
Fig. 6 is a kind of Waveform storage apparatus structure schematic diagram disclosed by the invention；
Fig. 7 is another Waveform storage apparatus structure schematic diagram disclosed by the invention；
Fig. 8 is another Waveform storage apparatus structure schematic diagram disclosed by the invention.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, it is obtained by those of ordinary skill in the art without making creative efforts every other
Embodiment shall fall within the protection scope of the present invention.
Referring to Fig. 1, Fig. 1 is a kind of Waveform storage method flow diagram disclosed by the invention, the method includes following steps
It is rapid:
Step S101: sampling the Wave data in CAN bus, and each Wave data that sampling is obtained turns
It is changed to logic level signal；
Specifically, when recording the communication waveforms in CAN bus, it is desirable that in the CAN bus free time when stored waveform
When not wave recording, this frame Waveform storage is got off when occurring CAN frame in bus.That is, to logical in CAN bus
Letter waveform will sample CAN Wave data before being stored, to sentence to whether CAN bus is in idle condition
It is disconnected.
Wherein, the Wave data in CAN bus is analog signal, for the ease of subsequent analysis, needs to sample and obtains
The Wave data of each be converted to logic level signal.
Step S102: when being continuously available multiple logic level signals and characterizing the CAN bus and be in Idle state, after detection
With the presence or absence of frame start signal in continuous obtained logic level signal；
Specifically, a complete CAN frame is originated by frame, arbitration field, controlling filed, (remote frame does not have data to data fields
), verification field, response field and frame end composition.In fact, whether detection bus is in idle relative to detection bus communication
State is more simple and easy, as long as detecting frame start signal it may determine that bus is in after determining that CAN bus is in Idle state
Communications status.
Step S103: when detecting frame start signal, the corresponding Wave data of the frame start signal is stored.
Specifically, indicating that bus is in communications status, this when can be to described when detecting frame start signal
The corresponding Wave data of frame start signal is stored, that is to say, that Waveform storage method disclosed by the invention is to CAN frame number
According to not needing to decode, decodes and realized in the work of the correlative study after Waveform storage, it is not necessary that repeat decoding is carried out, as long as quasi-
Really detect that frame start signal can trigger Waveform storage.That is, the present invention does not need to buffer a complete CAN frame
Waveform, only need to buffer the Wave data of a position can trigger Waveform storage.To the two-way analog signal in CAN bus with
8 ADC samplings are than being for 100:1 is sampled, it is only necessary to the waveform for buffering 2*8*100=200Bytes, relative to existing skill
Art needs to buffer a frame 32000Bytes waveform, and the ram in slice resource of FPGA is greatly saved.
The above are a kind of CAN Waveform storage methods provided by the invention, will sample to obtain to the Wave data in CAN bus
Each Wave data be converted to logic level signal, may determine that by carrying out analysis to continuous multiple logic level signals
Whether CAN bus is in Idle state, and whether detects subsequent obtained logic level signal after CAN bus is in Idle state
There are frame start signals.In CAN message structure, frame start signal indicate bus on there are communication waveforms, as long as therefore
CAN bus detects that frame start signal can deposit the corresponding Wave data of the frame start signal after being in Idle state
Storage does not need addition controller and receives to CAN message, does not need addition transceiver yet and is decoded to CAN message to sentence
Whether disconnected bus is in communications status, saves the cost of CAN transceiver and controller, while only needing a small amount of ram in slice resource,
Effectively reduce the cost of Waveform storage.
As shown in Fig. 2, each Wave data for being sampled to the Wave data in CAN bus, and sampling being obtained
Be converted to logic level signal, specific implementation procedure, comprising the following steps:
Step S201: the road Wave data Zhong Ge analog signal is compared by default sampling and is sampled；
Wherein, sampling is than being the sample rate of analog-digital converter and the ratio between the baud rate of CAN bus signal.The wave of CAN bus
Graphic data includes CANH and CANL two-way analog signal.
Preferably, the preset sampling is than being 100:1, it may be assumed that the sample rate of analog-digital converter is 100M/S, CAN bus
The baud rate of signal is 1Mb/S, then samples than for 100:1, that is to say, that need to sample on the waveform of 1Bit 100 times.
Step S202: decay to per the analog signal described all the way by default decaying rule；
Specifically, CANH and CANL signal may exceed normal range under very strong external interference, in some instances it may even be possible to
Reach more than ten volts.It is therefore desirable to which CANH the and CANL signal that sampling obtains is decayed in the tolerance range of analog-digital converter.
Step S203: digital signal will be converted to per the analog signal described all the way through overdamping；
Specifically, CANH the and CANL signal through overdamping is analog signal, for the ease of subsequent analysis, need to decline
CANH and CANL signal after subtracting is converted into the digital signal of 2 systems.
Step S204: carrying out arithmetic by default algorithmic rule for digital signal described in each road and subtract each other, and it is poor to obtain mathematics all the way
Divided data；
Specifically, CANH and CANL digital signal progress arithmetic is subtracted each other, mathematical difference data all the way, the mathematics are obtained
Differential data is the voltage signal that unit is volt.
Step S205: each signal data in the mathematical difference data is successively converted into logic level signal.
Specifically, two threshold values are arranged in value range 0V~1V of the mathematical difference data, first threshold is
0.2V, second threshold 0.8V provide 0.2V and 0.2V mathematical difference data below in the mathematical difference data of each
It is converted into the logic level signal of dominant bit；The mathematical difference data of 0.8V and 0.8V or more are converted into the logic level of recessive position
Signal；Differential data between first threshold and second threshold is converted into reference to a upper sampled result for the differential data
Logic level signal as a result, if on the differential data of institute's rheme a sampled result be converted into dominant bit logic level letter
Number then convert the differential data to the logic level signal of dominant bit；If a sampled result on the differential data of institute's rheme
The logic level signal for being converted into recessive position then converts the differential data to the logic level signal of recessive position.
Referring to Fig. 3, being detected when being continuously available multiple logic level signals and characterizing the CAN bus and be in Idle state
It whether there is frame start signal in subsequent obtained logic level signal, specifically includes the following steps:
Step 301: the number for the recessive position that detection continuous sampling obtains；When the number for the recessive position that continuous sampling obtains is full
When sufficient predetermined number requires, determine that the CAN bus is currently at idle state.
Specifically, passing through CAN frame structure it can be found that a complete CAN frame is originated by frame, arbitrates field, controlling filed, number
According to field (remote frame does not have data fields), verification field, response field and frame end composition.Frame end is 8 recessive positions, and interframe is divided into 3
A recessiveness position adds up and shares 11 recessive positions.And CAN bus agreement is defined except frame starting and other the 5 of frame end
Once 5 continuous identical bits occur must be filled with an opposite position in a field, i.e., can only at most there are 5 continuous recessive positions.
The logic level that namely simply can only sample CAN bus determines at CAN bus when continuous sampling is to 11 recessive positions
In idle state.
Preferably, when continuous sampling is to 8 or more recessive positions it is determined that CAN bus is in idle condition.
Step S302: when determining that the CAN bus is currently at Idle state, first that subsequent acquisition is arrived is dominant
The logic level signal of position is determined as frame start signal.
Specifically, passing through CAN frame structure it can be found that frame starting is fixed as 1 dominant bit, as long as determining CAN bus
Detect that 1 dominant bit just can determine that this dominant bit is frame start signal when being currently at Idle state.
Referring to Fig. 4, the Waveform storage method further include:
Step S104: carrying out interference to each logic level signal and handle, subsequent according to multiple logic electricity to guarantee
Ordinary mail number determines whether the CAN bus is in Idle state and detects whether the accuracy there are frame start signal；
Specifically, the signal of a position is actually the voltage signal of a period of time length, if this voltage signal does not have
Have it is disturbed, then it all can be identical as a result, but such as that theoretically any moment during this period of time, which samples signal,
This voltage signal of fruit is disturbed, and the voltage that will lead to this period is not always maintained at constant, is adopted at different times
Sample just will appear different results.
After CAN bus Wave data is converted to logic level signal, each voltage signal is only converted into performance
For dominant bit or the logic level signal of recessive position, pulse interference signal therein can not be filtered, when there is interference in bus
Or it can be showed in logic level.Occurs a bit of dominant bit interference in Fig. 5 in a recessive position, if sampling is only
It is that simple Edge check is timed sampling again, is just likely to accidentally sample dominant bit.If this interference occurs total
It can then be judged by accident when line idle state and be set to frame starting, that is, understand false triggering CAN Waveform storage.And if this interference occurs continuous
Two CAN frames between, it is likely that less than continuous 11 recessive level can be sampled to leak triggering CAN Waveform storage.For
These are avoided to happen, the present invention carries out interference to each logic level signal and handles, to guarantee that subsequent foundation is more
A logic level signal determines whether the CAN bus is in Idle state and detects whether the accuracy there are frame start signal.
Preferably, using re-synchronize and three samples by the way of interference carried out to each logic level signal handle,
Realize accurately and reliably data sampling.
The logic level signal of one position is divided into sync section, pretreatment section, phase section 1 and phase section 2, sync section and pre-
Processing section is used to re-synchronize signal, solves the problems, such as signal position width dither.By taking the CAN signal of 1M baud rate as an example, 1 letter
Number length is 1uS；But because of the presence of shake and other interference, certain positions is caused to become greater than 1uS, and certain positions become less than
1uS so sampling cannot go to judge the section of a position with the time interval of fixed 1uS, and is needed according to recessive position and is shown
Property position switching when signal edge carry out re-synchronization；By taking time quantum is ten equal parts as an example, in signal jump, if preceding
The signal length of 1 position in face is greater than 1.1uS, then the hopping edge in sync section by sampling less than signal, hopping edge will located in advance
Reason section is sampled, and samples hopping edge if it is the 1st time quantum in pretreatment section, then the sampling to this below
Just need to move back 1 time quantum, thus re-synchronization signal.
3 numbers are sampled between the phase section of each logic level signal 1 and phase section 2 by the way of three samples
According to determining institute's rheme for dominant bit if having 2 in sampled result or 3 sampled datas are dominant bit；If having in sampled result
2 or 3 sampled datas are recessive position, then determine institute's rheme for recessive position.This avoid the interference of dominant bit, so as to standard
It is really reliable to extract start of frame bits.
Based on the above method, interference of the CAN bus interference signal to detection frame start signal when can be excluded, accurately and reliably
Extract frame start signal.By sampling obtain CAN bus Wave data be converted into logic level signal, only need to be according to interference be gone after
Logic level signal judge whether CAN bus is in Idle state, determine CAN bus be in Idle state after detect frame starting
Signal can store the corresponding Wave data of the frame start signal, do not need be added controller to CAN message into
Row receives, and does not also need addition transceiver and is decoded to CAN message to judge whether bus is in communications status, is saved
The cost of CAN transceiver and controller, while a small amount of ram in slice resource is only needed, effectively reduce the cost of Waveform storage.
Based on a kind of Waveform storage method disclosed in aforementioned present invention, referring to Fig. 6, present invention correspondence discloses a kind of wave
Shape storage device, comprising:
Sampling module 101, for being sampled to the Wave data in CAN bus, and each wave that sampling is obtained
Graphic data is converted to logic level signal；
Specifically, when recording the communication waveforms in CAN bus, it is desirable that in the CAN bus free time when stored waveform
When not wave recording, this frame Waveform storage is got off when occurring CAN frame in bus.That is, to logical in CAN bus
Letter waveform will sample CAN Wave data before being stored, to sentence to whether CAN bus is in idle condition
It is disconnected.
Wherein, the Wave data in CAN bus is analog signal, for the ease of subsequent analysis, needs to sample and obtains
The Wave data of each be converted to logic level signal.
Detection module 102 is in Idle state for that ought be continuously available multiple logic level signals characterizations CAN bus
When, it detects and whether there is frame start signal in subsequent obtained logic level signal；
Specifically, a complete CAN frame is originated by frame, arbitration field, controlling filed, (remote frame does not have data to data fields
), verification field, response field and frame end composition.In fact, whether detection bus is in idle relative to detection bus communication
State is more simple and easy, as long as detecting frame start signal it may determine that bus is in after determining that CAN bus is in Idle state
Communications status.
Memory module 103, for when detecting frame start signal, to the corresponding Wave data of the frame start signal into
Row storage.
Specifically, indicating that bus is in communications status, this when can be to described when detecting frame start signal
The corresponding Wave data of frame start signal is stored, that is to say, that Waveform storage method disclosed by the invention is to CAN frame number
According to not needing to decode, decodes and realized in the work of the correlative study after Waveform storage, it is not necessary that repeat decoding is carried out, as long as quasi-
Really detect that frame start signal can trigger Waveform storage.That is, so there is no need to buffer a complete CAN frame
Waveform, only need to buffer the Wave data of a position can trigger Waveform storage.To the two-way analog signal in CAN bus with
8 ADC samplings are than being for 100:1 is sampled, it is only necessary to the waveform for buffering 2*8*100=200Bytes, relative to existing skill
Art needs to buffer a frame 32000Bytes waveform, and the ram in slice resource of FPGA is greatly saved.
The above are a kind of CAN Waveform storage device provided by the invention, the preprocessing module 101 is in CAN bus
Wave data is sampled, and each Wave data that sampling obtains is converted to logic level signal；The detection module
102, when being continuously available multiple logic level signals and characterizing the CAN bus and be in Idle state, it is electric to detect subsequent obtained logic
It whether there is frame start signal in ordinary mail number；The memory module 103 originates the frame and believes when detecting frame start signal
Number corresponding Wave data is stored.CAN Waveform storage device provided by the invention, will be to the Wave data in CAN bus
It samples each obtained Wave data and is converted to logic level signal, by analyzing continuous multiple logic level signals
It may determine that whether CAN bus is in Idle state, and detect subsequent obtained logic level after CAN bus is in Idle state
Signal whether there is frame start signal.In CAN message structure, frame start signal indicates communication waveforms occur in bus, because
As long as this detects frame start signal to the corresponding waveform number of the frame start signal after CAN bus is in Idle state
It according to being stored, does not need addition controller and CAN message is received, do not need to be added transceiver to CAN message progress yet
Decoding saves the cost of CAN transceiver and controller, while only needing in a small amount of piece to judge whether bus is in communications status
RAM resource effectively reduces the cost of Waveform storage.
Referring to Fig. 7, sampling module 101 specifically includes
The sampling submodule 104 is carried out for comparing Wave data Zhong Ge road analog signal by default sampling
Acquisition；
Wherein, sampling is than being the sample rate of analog-digital converter and the ratio between the baud rate of CAN bus signal.The wave of CAN bus
Graphic data includes CANH and CANL two-way analog signal.
Preferably, the preset sampling is than being 100:1, it may be assumed that the sample rate of analog-digital converter is 100M/S, CAN bus
The baud rate of signal is 1Mb/S, then samples than for 100:1, that is to say, that need to sample on the waveform of 1Bit 100 times.
The decaying submodule 105, for decaying to per the analog signal described all the way by default decaying rule；
Specifically, CANH and CANL signal may exceed normal range under very strong external interference, in some instances it may even be possible to
Reach more than ten volts.It is therefore desirable to which CANH the and CANL signal that sampling obtains is decayed in the tolerance range of analog-digital converter.
First transform subblock 106, for digital letter will to be converted to per the analog signal described all the way through overdamping
Number；
Specifically, CANH the and CANL signal through overdamping is analog signal, for the ease of subsequent analysis, need to decline
CANH and CANL signal after subtracting is converted into the digital signal of 2 systems.
The acquisition submodule 107 is subtracted each other for digital signal described in each road to be carried out arithmetic by default algorithmic rule, is obtained
Obtain mathematical difference data all the way；
Specifically, CANH and CANL digital signal progress arithmetic is subtracted each other, mathematical difference data all the way, the mathematics are obtained
Differential data is the voltage signal that unit is volt.
Second transform subblock 108, for successively turning each signal data in the mathematical difference data
It is changed to logic level signal.
Specifically, two threshold values are arranged in value range 0V~1V of the mathematical difference data, first threshold is
0.2V, second threshold 0.8V provide 0.2V and 0.2V mathematical difference data below in the mathematical difference data of each
It is converted into the logic level signal of dominant bit；The mathematical difference data of 0.8V and 0.8V or more are converted into the logic level of recessive position
Signal；Differential data between first threshold and second threshold is converted into reference to a upper sampled result for the differential data
Logic level signal as a result, if on the differential data of institute's rheme a sampled result be converted into dominant bit logic level letter
Number then convert the differential data to the logic level signal of dominant bit；If a sampled result on the differential data of institute's rheme
The logic level signal for being converted into recessive position then converts the differential data to the logic level signal of recessive position.
Detection module 102 includes: decision sub-module 109 and determining submodule 110；
The decision sub-module 109, for detecting the number for the recessive position that continuous sampling obtains；It is obtained when continuous sampling
When the number of recessive position meets predetermined number requirement, determine that the CAN bus is currently at idle state.
Specifically, passing through CAN frame structure it can be found that a complete CAN frame is originated by frame, arbitrates field, controlling filed, number
According to field (remote frame does not have data fields), verification field, response field and frame end composition.Frame end is 8 recessive positions, and interframe is divided into 3
A recessiveness position adds up and shares 11 recessive positions.And CAN bus agreement is defined except frame starting and other the 5 of frame end
Once 5 continuous identical bits occur must be filled with an opposite position in a field, i.e., can only at most there are 5 continuous recessive positions.
The logic level that namely simply can only sample CAN bus determines at CAN bus when continuous sampling is to 11 recessive positions
In idle state.
Preferably, when continuous sampling is to 8 or more recessive positions it is determined that CAN bus is in idle condition.
The determining submodule 110, for when determining that the CAN bus is currently at Idle state, subsequent acquisition to be arrived
First logic level signal for dominant bit be determined as frame start signal.
Specifically, passing through CAN frame structure it can be found that frame starting is fixed as 1 dominant bit, as long as determining CAN bus
Detect that 1 dominant bit just can determine that this dominant bit is frame start signal when being currently at Idle state.
Referring to Fig. 8, present invention another kind Waveform storage device includes sampling module 101, goes interference module 111, detection
Module 102 and memory module 103, wherein the function of preprocessing module 101, detection module 102 and memory module 103 is same as above no longer
It repeats.
Interference module 111 is gone, is handled for carrying out interference to each logic level signal, to guarantee that subsequent foundation is more
A logic level signal determines whether the CAN bus is in Idle state and detects whether the accuracy there are frame start signal.
Specifically, the signal of a position is actually the voltage signal of a period of time length, if this voltage signal does not have
Have it is disturbed, then it all can be identical as a result, but such as that theoretically any moment during this period of time, which samples signal,
This voltage signal of fruit is disturbed, and the voltage that will lead to this period is not always maintained at constant, is adopted at different times
Sample just will appear different results.
After CAN bus Wave data is converted to logic level signal, each voltage signal is only converted into performance
For dominant bit or the logic level signal of recessive position, pulse interference signal therein can not be filtered, when there is interference in bus
Or it can be showed in logic level.Occurs a bit of dominant bit interference in Fig. 5 in a recessive position, if sampling is only
It is that simple Edge check is timed sampling again, is just likely to accidentally sample dominant bit.If this interference occurs total
It can then be judged by accident when line idle state and be set to frame starting, that is, understand false triggering CAN Waveform storage.And if this interference occurs continuous
Two CAN frames between, it is likely that less than continuous 11 recessive level can be sampled to leak triggering CAN Waveform storage.For
These are avoided to happen, interference module 111 is gone in increase of the present invention, carry out at interference to each logic level signal
Reason, to guarantee subsequent to determine whether the CAN bus is in Idle state and detects whether exist according to multiple logic level signals
The accuracy of frame start signal.
Preferably, it is described go interference module 111 using re-synchronize and three samples by the way of to each logic level believe
Number carrying out interference is handled, and realizes accurately and reliably data sampling.
The logic level signal of one position is divided into sync section, pretreatment section, phase section 1 and phase section 2, sync section and pre-
Processing section is used to re-synchronize signal, solves the problems, such as signal position width dither.By taking the CAN signal of 1M baud rate as an example, 1 letter
Number length is 1uS；But because of the presence of shake and other interference, certain positions is caused to become greater than 1uS, and certain positions become less than
1uS so sampling cannot go to judge the section of a position with the time interval of fixed 1uS, and is needed according to recessive position and is shown
Property position switching when signal edge carry out re-synchronization；By taking time quantum is ten equal parts as an example, in signal jump, if preceding
The signal length of 1 position in face is greater than 1.1uS, then the hopping edge in sync section by sampling less than signal, hopping edge will located in advance
Reason section is sampled, and samples hopping edge if it is the 1st time quantum in pretreatment section, then the sampling to this below
Just need to move back 1 time quantum, thus re-synchronization signal.
3 numbers are sampled between the phase section of each logic level signal 1 and phase section 2 by the way of three samples
According to determining institute's rheme for dominant bit if having 2 in sampled result or 3 sampled datas are dominant bit；If having in sampled result
2 or 3 sampled datas are recessive position, then determine institute's rheme for recessive position.This avoid the interference of dominant bit, so as to standard
It is really reliable to extract start of frame bits.
Based on above-mentioned apparatus, interference of the CAN bus interference signal to detection frame start signal when can be excluded, accurately and reliably
Extract frame start signal.By sampling obtain CAN bus Wave data be converted into logic level signal, only need to be according to interference be gone after
Logic level signal judge whether CAN bus is in Idle state, determine CAN bus be in Idle state after detect frame starting
Signal can store the corresponding Wave data of the frame start signal, do not need be added controller to CAN message into
Row receives, and does not also need addition transceiver and is decoded to CAN message to judge whether bus is in communications status, is saved
The cost of CAN transceiver and controller, while a small amount of ram in slice resource is only needed, effectively reduce the cost of Waveform storage.
The foregoing description of the disclosed embodiments enables those skilled in the art to implement or use the present invention.
Various modifications to these embodiments will be readily apparent to those skilled in the art, as defined herein
General Principle can be realized in other embodiments without departing from the spirit or scope of the present invention.Therefore, of the invention
It is not intended to be limited to the embodiments shown herein, and is to fit to and the principles and novel features disclosed herein phase one
The widest scope of cause.
Claims (8)
1. a kind of Waveform storage method, which is characterized in that the described method includes:
Wave data in CAN bus is sampled, and each Wave data that sampling obtains is converted into logic level
Signal；
Interference is carried out to each logic level signal to handle, specifically: the logic level signal of a position is divided into synchronization
Section, pretreatment section, phase section 1 and phase section 2 re-synchronize signal using the sync section and the pretreatment section, and use three
The mode of point sampling samples 3 data between the phase section 1 and phase section 2 of logic level signal, if there is 2 in sampled result
Or 3 sampled datas are dominant bit, then determine institute's rheme for dominant bit；If having 2 in sampled result or 3 sampled datas being hidden
Property position, then determine institute's rheme for recessive position；
When being continuously available multiple logic level signals and characterizing the CAN bus and be in Idle state, the subsequent obtained logic of detection
It whether there is frame start signal in level signal；
When detecting frame start signal, the corresponding Wave data of the frame start signal is stored.
2. the method according to claim 1, wherein the Wave data in CAN bus is acquired, and
Each Wave data collected, which is converted to logic level signal, includes:
The road Wave data Zhong Ge analog signal is compared by default sampling to be sampled；
Decay to per the analog signal described all the way by default decaying rule；
Digital signal will be converted to per the analog signal described all the way through overdamping；
Digital signal described in each road is carried out arithmetic by default algorithmic rule to subtract each other, obtains mathematical difference data all the way；
Each signal data in the mathematical difference data is successively converted into logic level signal.
3. the method according to claim 1, wherein the logic level signal is stealthy position or dominant bit；
It is described be continuously available multiple logic level signals and characterize the CAN bus and be in idle condition include:
The number for the recessive position that detection continuous sampling obtains；
When the number for the recessive position that continuous sampling obtains meets predetermined number requirement, determine that the CAN bus is currently at sky
Not busy state.
4. the method according to claim 1, wherein in the subsequent obtained logic level signal of the detection whether
There are frame start signals to include:
When determining that the CAN bus is currently at Idle state, first that subsequent acquisition is arrived is the logic level of dominant bit
Signal is determined as frame start signal.
5. a kind of Waveform storage device, which is characterized in that described device includes:
Sampling module, for sampling to the Wave data in CAN bus, and each Wave data that sampling is obtained turns
It is changed to logic level signal；
Interference module is gone, is handled for carrying out interference to each logic level signal, specifically: by the logic electricity of a position
Ordinary mail number is divided into sync section, pretreatment section, phase section 1 and phase section 2, is re-synchronized using the sync section and the pretreatment section
Signal, and 3 data are sampled between the phase section of logic level signal 1 and phase section 2 by the way of three samples, if adopting
There are 2 in sample result or 3 sampled datas are dominant bit, then determines institute's rheme for dominant bit；If having 2 or 3 in sampled result
A sampled data is recessive position, then determines institute's rheme for recessive position；
Detection module, for when being continuously available multiple logic level signals and characterizing the CAN bus and be in Idle state, after detection
With the presence or absence of frame start signal in continuous obtained logic level signal；
Memory module, for being stored to the corresponding Wave data of the frame start signal when detecting frame start signal.
6. device according to claim 5, which is characterized in that the sampling module includes:
Submodule is sampled, is sampled for comparing the road Wave data Zhong Ge analog signal by default sampling；
Decaying submodule, for decaying to per the analog signal described all the way by default decaying rule；
First transform subblock, for digital signal will to be converted to per the analog signal described all the way through overdamping；
Acquisition submodule subtracts each other for digital signal described in each road to be carried out arithmetic by default algorithmic rule, obtains mathematics all the way
Differential data；
Second transform subblock, for each signal data in the mathematical difference data to be successively converted to logic level
Signal.
7. device according to claim 5, which is characterized in that the logic level signal is recessive position or dominant bit；Institute
Stating detection module includes:
Decision sub-module, for detecting the number for the recessive position that continuous sampling obtains；As for the recessive position that continuous sampling obtains
When number meets predetermined number requirement, determine that the CAN bus is currently at idle state.
8. device according to claim 5, which is characterized in that the detection module includes:
Submodule is determined, for when determining that the CAN bus is currently at Idle state, first that subsequent acquisition is arrived to be aobvious
The logic level signal of property position is determined as frame start signal.
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| CN111416761A (en) * | 2019-01-04 | 2020-07-14 | 珠海零边界集成电路有限公司 | CAN waveform simulation device, simulation method and CAN waveform transmitter |
| CN115065575B (en) * | 2022-07-26 | 2022-11-29 | 广州智慧城市发展研究院 | Data transmission system based on CAN bus controller and electronic equipment |
| CN117650866A (en) * | 2023-11-23 | 2024-03-05 | 广州致远仪器有限公司 | CAN frame decoding method, device, equipment and storage medium |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN201122984Y (en) * | 2007-08-22 | 2008-09-24 | 深圳市智林机电技术有限公司 | Mobile covering synchronous transmission device |
| CN102355382A (en) * | 2011-09-28 | 2012-02-15 | 东南大学 | Method for analyzing and triggering controller area network (CAN) bus |
| CN103475523A (en) * | 2013-09-10 | 2013-12-25 | 浙江大学 | CAN bus analysis system with bus error analysis function |
| CN104457824A (en) * | 2014-11-24 | 2015-03-25 | 成都盛军电子设备有限公司 | General testing system |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| US7929461B2 (en) * | 2005-06-09 | 2011-04-19 | Tekronix, Inc. | Controller area network performance parameters measurement |
-
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN201122984Y (en) * | 2007-08-22 | 2008-09-24 | 深圳市智林机电技术有限公司 | Mobile covering synchronous transmission device |
| CN102355382A (en) * | 2011-09-28 | 2012-02-15 | 东南大学 | Method for analyzing and triggering controller area network (CAN) bus |
| CN103475523A (en) * | 2013-09-10 | 2013-12-25 | 浙江大学 | CAN bus analysis system with bus error analysis function |
| CN104457824A (en) * | 2014-11-24 | 2015-03-25 | 成都盛军电子设备有限公司 | General testing system |
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