CN103176014B - A kind of Wave data decoding apparatus and oscillograph - Google Patents
A kind of Wave data decoding apparatus and oscillograph Download PDFInfo
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- CN103176014B CN103176014B CN201110434965.8A CN201110434965A CN103176014B CN 103176014 B CN103176014 B CN 103176014B CN 201110434965 A CN201110434965 A CN 201110434965A CN 103176014 B CN103176014 B CN 103176014B
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Abstract
The embodiment of the present invention provides a kind of Wave data decoding apparatus and oscillograph, and described Wave data decoding apparatus includes: data capture unit, for obtaining one group of Wave data after triggering from waveform acquisition datarams space；Digital unit, for being digitized by the described Wave data obtained, is converted into two-value data；Decoder element, for utilizing the decoder of described Wave data correspondence agreement, is decoded as protocol data by described two-value data.The present invention also provides for a kind of oscillograph.The present invention provides a kind of technical scheme that can realize Wave data decoding, uses a set of unified handling process, simplified system model, additionally by modularized design with multiplexing assembly, reduces complexity.
Description
Technical field
The present invention relates to test field of measuring technique, particularly relate to a kind of Wave data decoding apparatus and oscillograph.
Background technology
Storage depth and the sample rate of digital oscilloscope are more and more higher, and its function is no longer limited to the shape of observation signal, also may be used
Protocol-decoding is carried out with the data for capture.During use, first it is stored in internal memory, then with oscillograph capture one piece of data
Protocol decoder carries out protocal analysis for the data captured, and the result of analysis will show at screen in the way of numeral or icon
On curtain.So, when debugging circuit, obtained by oscillograph is not only the shape information of waveform, also has and wherein contains
Digital information, change for numeral intuitively from the waveform of physical layer, it is no longer necessary to comparison waveform manually records height
Low level.
In the circuit of Debug Wire Protocol, the both sides of communication are transceiving data under the agreement of regulation.When transmission-receiving function is abnormal
Time, it is possible to use the waveform quality on oscillograph detection communication link.If communication quality meets requirement, in order to divide further
Analysis, needs to check that the data of communication are the most effective.Than such as whether the data with or without effect are transmitted, if there is miscommunication etc., this
Time, without decoder, it is difficult to analyze information therein by waveform shape.And had protocol decoder, just
The result of decoding and corresponding waveform can be compareed, analyze the trouble point of communication.Communications protocol has many kinds, in order to adapt to
Demand, requires the most integrated multiple decoder in product.Communications protocol complexity is different, and required resource is different.
How simplified system model, reduce complexity, this is the important topic that those skilled in the art are urgently to be resolved hurrily.
Summary of the invention
The embodiment of the present invention provides a kind of Wave data decoding apparatus and oscillograph, to provide one can realize Wave data solution
The technical scheme of code, simplified system model, reduces complexity.
On the one hand, embodiments providing a kind of Wave data decoding apparatus, described device includes: data capture unit,
For obtaining one group of Wave data after triggering from waveform acquisition datarams space；Digital unit, for the institute that will obtain
State Wave data to be digitized, be converted into two-value data；Decoder element, is used for utilizing described Wave data correspondence agreement
Decoder, described two-value data is decoded as protocol data.
Optionally, in an embodiment of the present invention, described digital unit, specifically may be used for utilizing the threshold level arranged
With sensitivity to be digitized by the described Wave data obtained, it is converted into two-value data.
Optionally, in an embodiment of the present invention, described device can also include: decoding data processing unit, for basis
The unified display format that protocol data is corresponding, obtains the displays content data that described protocol data is corresponding respectively；Display unit,
For the position that described displays content data is corresponding with waveform position on screen is shown.
Optionally, in an embodiment of the present invention, described decoding data processing unit, specifically may be used for by described decoding
Described protocol data is filtered by the frame data filter that data processing unit comprises, and according to unification corresponding to protocol data
Display format, obtains the displays content data that described protocol data is corresponding respectively.
Optionally, in an embodiment of the present invention, described display unit, specifically may be used for described displays content data,
Shown with the position that the form of event table is corresponding with waveform position on screen by the window ejected.
Optionally, in an embodiment of the present invention, described device can also include: decoder dispensing unit, is used for configuring institute
State the decoding parametric of the decoder of Wave data correspondence agreement；Described decoder element utilizes the described solution after configuration decoding parametric
Code device, is decoded as protocol data by described two-value data.
Optionally, in an embodiment of the present invention, described decoder may include that shift unit, message pump, message processor,
Shift register and enumerator, wherein: described shift unit, be used for obtaining described two-value data, be converted into Bit data and depend on
Secondary output；Described message pump, for receiving the described Bit data of described shift unit output, extracts from described Bit data
Go out and protocol-dependent message；Described message processor, for receiving the described and protocol-dependent of the output of described message pump
Message, and according to the described and protocol-dependent message described Bit data of sampling, safeguard the state transition of self, at shape simultaneously
The Bit data after sampling is outwards exported when state redirects；Described enumerator, for the position of accumulative described Bit data of sampling,
And the time sequencing of described protocol data is determined according to the position of described Bit data；Described shift register, with described message
Datatron is connected, the Bit data after caching described sampling, and output protocol data.
Optionally, in an embodiment of the present invention, described enumerator is for the position of accumulative described Bit data of sampling, and depends on
The time sequencing of described protocol data is determined according to the position of described Bit data.
Optionally, in an embodiment of the present invention, described decoder also includes: clock, wherein: described clock, with described
Message pump and described message processor are respectively connected with, and under message processor control, timing produces a sampled signal,
Utilize described sampled signal notify described message pump using current bit data as data bit；Under message processor control, fixed
Time produce sampled data message, notify that the Bit data after decoded described sampling is delivered to displacement and posted by described message processor
Storage caches.
Another further aspect, embodiments provides a kind of oscillograph, and described oscillograph includes above-mentioned Wave data decoding apparatus.
Technique scheme has the advantages that because using data capture unit, for from waveform acquisition datarams
Space obtains one group of Wave data after triggering；Digital unit, for the described Wave data obtained is digitized,
It is converted into two-value data；Decoder element, for utilizing the decoder of described Wave data correspondence agreement, by described two-value number
According to being decoded as the technological means of protocol data, so providing a kind of technical scheme that can realize Wave data decoding, use
A set of unified handling process, simplifies system model, additionally by modularized design with multiplexing assembly, reduces complexity.
Accompanying drawing explanation
In order to be illustrated more clearly that the embodiment of the present invention or technical scheme of the prior art, below will be to embodiment or existing skill
In art description, the required accompanying drawing used is briefly described, it should be apparent that, the accompanying drawing in describing below is only the present invention
Some embodiments, for those of ordinary skill in the art, on the premise of not paying creative work, it is also possible to
Other accompanying drawing is obtained according to these accompanying drawings.
Fig. 1 is embodiment of the present invention one Wave data decoding apparatus structural representation；
Fig. 2 is embodiment of the present invention another kind Wave data decoding apparatus structural representation；
Fig. 3 is the handling process schematic diagram that inventive decoder is overall；
Fig. 4 is that embodiment of the present invention decoder basic module processes schematic diagram；
Fig. 5 is application example binaryzation schematic diagram of the present invention；
Fig. 6 is application example Wave data transition diagram of the present invention；
Fig. 7 is application example RS232 decoder configuration parameter schematic diagram of the present invention；
Fig. 8 is application example SPI decoder configuration parameter schematic diagram of the present invention；
Fig. 9 is application example RS232 decoding process schematic diagram of the present invention；
Figure 10 is application example SPI of the present invention (Serial Peripheral Interface, Serial Peripheral Interface) decoded stream
Journey schematic diagram；
Figure 11 is that application example of the present invention decodes flow chart of data processing schematic diagram；
Figure 12 is several incomplete form of expression schematic diagram that application example frame of the present invention contains；
Figure 13 is several basic configuration schematic diagrams of application example induction-arrangement of the present invention；
Figure 14 is application example of the present invention abstract decomposes schematic diagram in concrete display by several；
Figure 15 is application example application frame data filter (Frame Filter) schematic diagram of the present invention；
Figure 16 is that application example of the present invention display representations of events is intended to.
Detailed description of the invention
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clearly and completely
Describe, it is clear that described embodiment is only a part of embodiment of the present invention rather than whole embodiments.Based on this
Embodiment in invention, the every other reality that those of ordinary skill in the art are obtained under not making creative work premise
Execute example, broadly fall into the scope of protection of the invention.
As it is shown in figure 1, be embodiment of the present invention one Wave data decoding apparatus structural representation, described device includes:
Data capture unit 21, for obtaining one group of Wave data after triggering from waveform acquisition datarams space；
Digital unit 22, for being digitized by the described Wave data obtained, is converted into two-value data；
Decoder element 23, for utilizing the decoder of described Wave data correspondence agreement, is decoded as association by described two-value data
View data.
Optionally, described digital unit 22, specifically may be used for utilizing the threshold level arranged and sensitivity with by acquisition
Described Wave data is digitized, and is converted into two-value data.
As in figure 2 it is shown, be embodiment of the present invention another kind Wave data decoding apparatus structural representation, described device not only wraps
Include above-mentioned data capture unit 21, digital unit 22 and decoder element 23, it is also possible to including: decoding data process single
Unit 24, for the unified display format corresponding according to protocol data, obtains the display content number that described protocol data is corresponding respectively
According to and organize；Display unit 25, for entering the position that described displays content data is corresponding with waveform position on screen
Row display.
Optionally, described decoding data processing unit 24, specifically may be used for being comprised by described decoding data processing unit
Described protocol data is filtered by frame data filter, to filter out the data outside screen shows, and according to protocol data pair
The unified display format answered, obtains the displays content data that described protocol data is corresponding respectively.
Optionally, described display unit 25, specifically may be used for described displays content data, by the window of ejection with thing
The position corresponding with waveform position on screen of the form of part table shows.
Optionally, described device can also include: decoder dispensing unit 26, is used for configuring described Wave data correspondence agreement
The decoding parametric (such as data channel, clock lane etc., for different decoders, its configuration project is different) of decoder；
Described decoder element utilizes the described decoder after configuration decoding parametric, and described two-value data is decoded as protocol data.
Optionally, described decoder may include that shift unit, message pump, message processor, shift register and enumerator,
Wherein: described shift unit, it is used for obtaining described two-value data, is converted into Bit data and is sequentially output；Described message pump,
For receiving the described Bit data of described shift unit output, extract from described Bit data and protocol-dependent message；
Described message processor, for receiving the described and protocol-dependent message of the output of described message pump, and according to described and association
The message described Bit data of sampling that view is relevant, safeguards the state transition of self simultaneously, outwards exports sampling when state transition
After Bit data；Described enumerator, for determining the time sequencing of described protocol data；Described shift register, with institute
State message processor to be connected, the Bit data after caching described sampling, and output protocol data.Optionally, described meter
Number device is for the position of accumulative described Bit data of sampling, and determines described protocol data according to the position of described Bit data
Time sequencing.
Optionally, described decoder also includes: clock, wherein: described clock, with described message pump and described Message Processing
Machine is respectively connected with, and under message processor control, timing produces a sampled signal, utilizes described sampled signal to notify
Described message pump using current bit data as data bit；In asynchronous communication, under message processor control, timing produces
Sampled data message, notifies that the Bit data after decoded described sampling is delivered to shift register and delayed by described message processor
Deposit.
Embodiment of the present invention said apparatus technical scheme have the advantages that because use data capture unit, for from
Waveform acquisition datarams space obtains one group of Wave data after triggering；Digital unit, for the described waveform that will obtain
Data are digitized, and are converted into two-value data；Decoder element, for utilizing the decoding of described Wave data correspondence agreement
Device, is decoded as the technological means of protocol data by described two-value data, so providing one can realize Wave data decoding
Technical scheme, use a set of unified handling process scheme, simplify system model, additionally by modularized design with multiple
With assembly, reduce complexity.
Application example of the present invention above-mentioned Wave data decoding apparatus can be oscillograph, is below described in detail: actual application
In communications protocol have many kinds, but can be decoded processing according to overall procedure above to it, the ripple that will collect
Graphic data goes out each communication field according to protocol identification.Different agreements needs corresponding different " decoder " module, other moulds
Block can all multiplexings.Therefore, the design of " decoder " module is an emphasis during decoding function realizes.
The design of decoder:
Decoder receives two-value data input, is analyzed data according to agreement, outside output protocol data, protocol data
It is usually byte-aligned.So, it is also possible to decoder is regarded as " string-and " transducer, Bit data is converted into
Byte data.As it is shown on figure 3, be the overall handling process schematic diagram of inventive decoder.Its input is " digitized " place
Two-value data after reason, is output as protocol data, protocol data defeated as " decoding data processing unit " in the present system
Enter.
For different agreements, need to realize different " decoders ", owing to its overall process flow is identical, so design
Some realize the assembly of basic function, according to concrete agreement, combine these basic functional components and can be achieved with the solution of concrete agreement
Code device.
As shown in Figure 4, schematic diagram is processed for embodiment of the present invention decoder basic module, wherein:
Shift unit shifter: be sequentially output by Bit data, corresponding to physical receiver step-by-step receive capabilities.Two-value data,
Only " 1 ", " 0 " two states, the memory space of digital oscilloscope is with byte-aligned, and i.e. one byte can contain
Having 8 two-value datas, this can reduce the two-value data demand for memory space.Owing to decoder needs two-value data defeated
Enter, the most once input " 1 " or " 0 " state, so needing byte data is sequentially output 8 two-value datas.Shift unit
Input be bytes of stream data, be output as Bit data.Shift unit receives parallel input, then step-by-step output, as
One byte (8Bit), after entering shift unit, the most outwards 8 bits of output, can be high-order output or low level output.
Shift register uart: shift register, receives number of bits and according to input and caches, often receive new Bit data
After, data unification originally is moved to high-order or low level, the data of shift register outside output byte alignment.Caching is from number
According to the data sampled in stream, step-by-step inputs, and byte exports, and is additionally operable to cache described protocol data, and exports.
Clock clock: timing produces a sampled signal, using current bit data as data bit.Asynchronous communication needs sampling
Clock, timing produces sampled data message in a decoder, and notification message datatron is delivered to shift register from sampled data and delayed
Deposit.
Enumerator counter: the position of accumulative sampling bits data, it is ensured that the time sequencing of protocol data.
Message pump pumper: receive the input of shift unit, extract from Bit data and protocol-dependent message.Message pump
Receive from the output of shift unit, shift unit output Bit data, so what message pump received is 0,1 data, according to 0,
The change of 1 i.e. can obtain " high " " low " change in communications protocol with detection waveform raising and lowering message.?
In asynchronous communication, needing to recover clock in a decoder, clock timing produces sample message, and this message also passes through message
Pump transmits to message processor.
Message processor processor: receive the message input of message pump, process message under different decoder states.Place
Reason comes from the message of message pump, safeguards the state transition of self simultaneously.Under every sub-state, it is required for process and comes from
All message of message pump.If receiving the message of sampled data, then the Bit data sampled is exported shift register
Middle caching, outwards exports decoding data at state transition or depositor time full.Message processor also produce a control signal to
Clock is so that it produces clock signal.
Below, the digitized of the data acquisition of data capture unit 21, digital unit 22 (namely is converted to two
Value Data) process, the configuration process of decoding configuration unit 26 and the decoding process of decoder element 23, be described further.
Data acquisition:
It is different from existing coding/decoding method, one group of Wave data after the triggering that data capture unit 21 obtains, and discontinuous
Wave data.Decoding data (namely aforesaid Wave data) obtains from sample of memory, can use FIFO (First
Input First Output, First Input First Output) mode guarantee that decoding and sampling are carried out simultaneously.Digital oscilloscope waveform is adopted
Collection memory headroom is by byte-aligned, and i.e. one data point is stored in one or more byte.
Data form: decoding data use binary format, do not have concrete amplitude information, only " 1 " " 0 ",
Two states.
Digitized:
Decoding data use binary data, and the data in sample of memory have complete amplitude information, according to ADC
The resolution of (Analog-to-Digital Converter, A-D converter) is different, and the space that internal storage data takies is different.?
Need before decoding sample of memory Wave data is carried out binaryzation, " 1 " will be quantified as by analog waveform point value, " 0 " two kinds
Numerical value.In order to complete this quantizing process, need to set a threshold value (namely threshold level), and converting sensitivity.This
The individual process that analog waveform point value is quantified as " 1 " " 0 ", we are referred to as " binaryzation ", after converting, only
There are two kinds of values.
As it is shown in figure 5, be application example binaryzation schematic diagram of the present invention: if waveform is more than threshold value, be then judged to 1, as
Fruit is then judged to 0 less than threshold value, if waveform saltus step beyond threshold value and sensitivity, is then judged to original anti-, otherwise protects
Hold.
After " digitized ", data point only has two kinds of values possible, " 1 " or " 0 ", so using a bit with regard to energy
Store two value informations that a data point is corresponding.And RAM memory space is usually byte-aligned, if a byte
Interior only one data point two value information of storage, then can waste 7 bits.In order to save RAM memory space, at " number
Word " after Bit data be combined into the form of byte and store, containing 8 bilevel waveform dot informations in i.e. one byte.
As shown in Figure 6, for application example Wave data transition diagram of the present invention, finally, 8 bytes are apparently seen with 16 systems
Data are 0x78.
Decoder configures:
Decoder configures and is divided into two classes:
General configuration project, is required for the project of configuration for all decoders.
Decoder proprietary configuration project, decoder is corresponding with communications protocol, and communications protocol varies, so decoder configuration
Parameter is also very different.
Decoder general configuration parameters:
Passage threshold value: the analog channel Wave data gathered is carried out binaryzation according to this threshold value；For logical channel, no
Threshold value is needed to be digitized processing, because the data that logical channel collects have been logical one or " 0 " again.
Display format: the display format of decoding data, such as hexadecimal, decimal scale etc.；
Display position: decoding data display position on screen.
The configurable parameter of RS232 decoder:
Data channel: the data channel of configuration TX/RX；
Polarity: the positive/negative polarity of configuration communication；
Position sequence: configuration communication is big end pattern or little endian mode；
Baud rate: the speed of communication；
Bit wide: the bit width of communication every time；
Stop bit width；
Verification mode.
As it is shown in fig. 7, be application example RS232 decoder configuration parameter schematic diagram of the present invention.
The configurable parameter of SPI decoder:
The data channel of data channel: CS/SCLK/MISO/MOSI；
Data width: communication data bit width；
Position sequence.
As shown in Figure 8, for application example SPI decoder configuration parameter schematic diagram of the present invention.
As it is shown in figure 9, be application example RS232 decoding process schematic diagram of the present invention:
The sub-state of RS232 decoder:
RS232 decoder messages datatron contains idle, tetra-sub-states of data, check, stop, corresponds respectively to decode data
4 stages, its transformational relation successively:
Idle-＞ data, idle state is detecting that data enter data mode after initial, is exporting data to uart in data state；
Data-＞ [check]-＞ stop, output the data of designated length in data state to uart after, data state needs root
According to whether having check bit to enter check state or stop state.In check state, need to check check bit, enter the most again
Enter stop state；
Stop-＞ idle, detects stop position the most effective when stop state, and otherwise one erroneous frame prompting of output, then decodes
Device enters idle state, waits and is again introduced into data state.
RS232 decoder messages datatron message:
232 decoders are carrying out state change under the message-driven of message pump, and process this message.The message of 232 has:
(1) START: represent that in agreement " 1 " arrives the saltus step of " 0 "；
(2) DATA: notice sampled data, the data bit of sampling enters uart caching, timer asynchronicity produces；
(3) END: represent that " 0 " arrives the saltus step of " 1 "；
(4) POST_SYNC: postpone message.
As shown in Figure 10, for application example SPI of the present invention (Serial Peripheral Interface, Serial Peripheral Interface)
Decoding process schematic diagram:
The sub-state of SPI decoder messages datatron:
SPI decoder contains idle, tetra-sub-states of csd, data, err, and its transformational relation is:
Idle-＞ csd, after SPI decoder detects chip selection signal, enters csd state, represents and wait data receiver；
Csd-＞ data, csd state, after receiving clock signal, enters data state, starts to receive data, and data export
Uart caches；
Data-＞ err-＞ idle, if be not received by the data length specified in data state, then decoder enters err state,
Give the frame prompting made mistake, be then reset to idle state；
Data-＞ idle, in data mode, does not has data, and receives sheet and select invalid signals, enter idle shape in uart
State, does not has mistake.Select invalid signals without sheet, be then always maintained at data state, export data to uart.
SPI decoder messages datatron message:
(1) CLK, rising edge；
(2) NCLK, trailing edge clock；
(3) CS, sheet choosing is effectively；
(4) DCS, sheet selects invalid.
SPI decoder carries out state change under these message-driven, process to these message when different
Cheng Huiyou is different.As, in data state, send into uart caching according to clk or (nclk) sampled data position, and at idle
State, then be not responding to the two message.
By RS232 and SPI decoder it can be seen that the difference that exists of different decoder
(1) assembly used in decoder is different, i.e. the composition of decoder is different.For whole decoding process, will not
With partially defined in the implementing of " decoder ", different agreement corresponding different " decoder "；
(2) State Transferring of decoder is different, but the pre-treatment of " decoder " and post processing, identical；
(3) message of decoder is different, uses the assembly arrived different, but major part assembly is all general in " decoder "
The assembly of function.
As shown in figure 11, decoding flow chart of data processing schematic diagram for application example of the present invention, the data once decoded may have
Different display modes and scope, as checked the details of decoding, in MAIN (main body) in ZOOM (scaling) district
All of decoded data block, it can be seen that overall picture substantially, can be checked in event table by district.
Decoder output protocol data, decoding data processing unit, according to unified display format corresponding to protocol data, obtains respectively
Take displays content data corresponding to described protocol data and organize, by tissue by unified for displays content data for abstract frame
Form export to display unit, containing data in frame, frame position, the information such as frame type, display unit is by the institute after tissue
The position stating displays content data corresponding with waveform position on screen shows.As shown in figure 12, apply for the present invention
Several incomplete form of expression schematic diagram that example frame contains.
As shown in figure 13, for several basic configuration schematic diagrams of application example induction-arrangement of the present invention.
As shown in figure 14, abstract schematic diagram in concrete display is decomposed for application example of the present invention by several.
As shown in figure 15, for application example application frame data filter (Frame Filter) schematic diagram of the present invention: should in reality
In with, what screen showed may be a bit of internal memory waveform, and the decoding data of its correspondence are also a section of internal memory.Decoding
From the beginning of internal memory starting point, in order to improve the efficiency of execution, need to filter out the frame outside screen shows.Such as at ZOOM mould
Under formula, ZOOM district is shown that the details of the one section of waveform in MAIN district, correspondingly the quantity of information MAIN to be less than of its display
District.Decoder is when being decoded, and still according to the decoding data in MAIN district, the Frame of decoding passes through respectively
ZOOM filter and MAIN filter are attached on two decoded result lines (LINE), and the most once decoding process just can be defeated
Go out the decoding data of different indication range, be not required to individually decode for ZOOM and MAIN computing.
Decoded result line (LINE) the accumulative Frame coming from frame data filter successively, can be real in the way of using array
Existing linear access.Article one, LINE represents a data output lead, for the decoder containing multiple data wires, has a plurality of LINE
Corresponding with physical connection.RX (reception) and TX (transmission) two is had to decode data wire in RS232 decoder,
SPI decoding there are MISO (multiple input single output) and MOSI (multi output single input) two data line.External module exists
When drawing decoding data, according to frame format analysis result LINE, drawing frames data, for there being the decoder of a plurality of LINE,
The form of every LINE is completely the same, can use identical handling process.
As shown in figure 16, it is intended to for application example of the present invention display representations of events: on screen, the decoded result line of display can
Can a part of data of corresponding internal memory, and when video data is more, on screen, the decoded data block width of display is very
Little, it has not been convenient to check data therein.Event table lists the decoding data corresponding to internal storage data in the way of form, this
Sample need not mobile waveform skew just can check all decoded results that internal memory is corresponding.Event table data come from decoder
Frame data export, it is possible to directly frame is exported data without filtering frames device incoming event table.Another kind of method is to solve
The data of the another kind of form of output in code device, it is simple to adapt with event table application.Containing temporal information in row in event table,
It is no longer necessary to the information such as color, frame explanation.
As fully visible, the embodiment of the present invention has the advantage that
1) multiple decoder is set up unified process: an a. decoding and is divided into " data acquisition ", " digitized ", " solve
Code device ", " decoding data process ", several steps such as " display ", this process is consistent for all protocol processes；
The most different decoding protocol processes, and only processes difference at " decoder "；C. decoder is specifically arranged for each agreement,
Decoder is internal uses basic functional unit to set up according to agreement, multiplexing assembly as far as possible.The input of all decoders,
Output is consistent.
2) realization of multiple decoders shares existing assembly: the pre-treatment of decoder, post processing is identical.To decoder
Function is finely divided, and independently goes out the assembly of specific function.A decoder can use identical with another decoder
Assembly.The most different decoders can use general assembly to set up according to agreement.
3) consistent output result, adapts to different displays and content: a. and shows shape according to general decoding data, fixed
Justice decoding data output format；B. the decoding data exported are deposited on the data line, i.e. show that decoding data with data wire are
Unit, uses a handling process, and screen can show a plurality of data lines simultaneously；C. the form that decoder output is identical,
The data of decoding are converted into by " decoding data process " and show corresponding form.
Those skilled in the art are it will also be appreciated that the various illustrative components, blocks (illustrative that list of the embodiment of the present invention
Logical block), unit, and step can pass through electronic hardware, computer software, or both combinations realize.For
Clearly show that the replaceability (interchangeability) of hardware and software, above-mentioned various illustrative components (illustrative
Components), unit and step the most universally describe their function.Such function is by hardware or soft
Part realizes depending on specifically applying the design requirement with whole system.Those skilled in the art can be specific for every kind
Application, it is possible to use the function described in the realization of various methods, but this realization is understood not to protect beyond the embodiment of the present invention
The scope protected.
Various illustrative logical block described in the embodiment of the present invention, or unit can pass through general processor, numeral
Signal processor, special IC (ASIC), field programmable gate array (FPGA) or other FPGA dress
Put, discrete gate or transistor logic, discrete hardware components, or the design of any of the above described combination realizes or operates described
Function.General processor can be microprocessor, alternatively, this general processor can also be any traditional processor,
Controller, microcontroller or state machine.Processor can also realize, such as at digital signal by calculating the combination of device
Reason device and microprocessor, multi-microprocessor, one or more microprocessors one Digital Signal Processor Core of associating, or appoint
What its similar configuration realizes.
Method or the step of algorithm described in the embodiment of the present invention can be directly embedded into hardware, the software mould of processor execution
Block or the combination of both.Software module can be stored in RAM memory, flash memory, ROM memory, EPROM
In memorizer, eeprom memory, depositor, hard disk, moveable magnetic disc, CD-ROM or this area, other is any
In the storage medium of form.Exemplarily, storage medium can be connected with processor, so that processor can be from storage matchmaker
Jie reads information, it is possible to deposit write information to storage medium.Alternatively, storage medium can also be integrated in processor.
Processor and storage medium can be arranged in ASIC, and ASIC can be arranged in user terminal.Alternatively, processor and
Storage medium can also be arranged in the different parts in user terminal.
In one or more exemplary designs, the above-mentioned functions described by the embodiment of the present invention can hardware, software,
The combination in any of firmware or this three realizes.If realized in software, these functions can store the matchmaker with computer-readable
On Jie, or it is transmitted on the medium of computer-readable with one or more instructions or code form.Computer readable medium includes computer
Store medium and be easy to so that allowing computer program transfer to the telecommunication media in other place from a place.Storage medium can be
Any general or special computer can be with the useable medium of access.Such as, such computer readable media can include but not
It is limited to RAM, ROM, EEPROM, CD-ROM or other optical disc storage, disk storage or other magnetic storage device,
Other any may be used for carrying or storage with instruction or data structure and other can by general or special computer or general or
Special processor reads the medium of the program code of form.Additionally, any connection can be properly termed computer-readable
Medium, such as, if software is by coaxial cable, a light from a web-site, server or other remote resource
Fine computer, twisted-pair feeder, Digital Subscriber Line (DSL) or with the wireless way for transmittings such as the most infrared, wireless and microwave also by
It is included in defined computer readable medium.Described video disc (disk) and disk (disc) include Zip disk, radium-shine
Dish, CD, DVD, floppy disk and Blu-ray Disc, disk is generally with magnetic duplication data, and video disc generally carries out light with laser
Learn and replicate data.Combinations of the above can also be included in computer readable medium.
Above-described detailed description of the invention, has been carried out the purpose of the present invention, technical scheme and beneficial effect the most in detail
Illustrate, be it should be understood that the detailed description of the invention that the foregoing is only the present invention, be not intended to limit the present invention
Protection domain, all within the spirit and principles in the present invention, any modification, equivalent substitution and improvement etc. done, all should wrap
Within being contained in protection scope of the present invention.
Claims (8)
1. a Wave data decoding apparatus, it is characterised in that described device includes:
Data capture unit, for obtaining one group of Wave data after triggering from waveform acquisition datarams space；
Digital unit, for being digitized by the described Wave data obtained, is converted into two-value data；
Decoder element, for utilizing the decoder of described Wave data correspondence agreement, is decoded as agreement by described two-value data
Data；
Described decoder includes: shift unit, message pump, message processor, shift register and enumerator, wherein:
Described shift unit, is used for obtaining described two-value data, is converted into Bit data and is sequentially output；
Described message pump, for receive described shift unit output described Bit data, extract from described Bit data and
Protocol-dependent message；
Described message processor, for receiving the described and protocol-dependent message of the output of described message pump, and according to described
With the protocol-dependent message described Bit data of sampling, safeguard the state transition of self simultaneously, outwards export when state transition
Bit data after sampling；
Described enumerator, for the position of accumulative described Bit data of sampling, and determines institute according to the position of described Bit data
State the time sequencing of protocol data；
Described shift register, is connected with described message processor, the Bit data after caching described sampling, and exports
Protocol data.
2. device as claimed in claim 1, it is characterised in that
Described digital unit, specifically for utilizing the threshold level arranged and sensitivity to be entered by the described Wave data obtained
Digitized, is converted into two-value data.
3. device as claimed in claim 1, it is characterised in that described device also includes:
Decoding data processing unit, for the unified display format corresponding according to protocol data, obtains described protocol data respectively
Corresponding displays content data；
Display unit, for showing the position that described displays content data is corresponding with waveform position on screen.
4. device as claimed in claim 3, it is characterised in that
Described decoding data processing unit, specifically for the frame data filter pair comprised by described decoding data processing unit
Described protocol data filters, and according to unified display format corresponding to protocol data, obtains the agreement number after filtering respectively
According to corresponding displays content data.
5. device as claimed in claim 3, it is characterised in that
Described display unit, specifically for by described displays content data, shielding with the form of event table by the window ejected
Position corresponding with waveform position on curtain shows.
6. device as claimed in claim 1, it is characterised in that described device also includes:
Decoder dispensing unit, for configuring the decoding parametric of the decoder of described Wave data correspondence agreement；Described decoder
Unit utilizes the described decoder after configuration decoding parametric, and described two-value data is decoded as protocol data.
7. device as claimed in claim 1, it is characterised in that described decoder also includes: clock, wherein:
Described clock, is respectively connected with described message pump and described message processor, under message processor control, fixed
Time produce a sampled signal, utilize described sampled signal notify described message pump using current bit data as data bit；?
Under message processor controls, timing produces sampled data message, notifies that described message processor is by after decoded described sampling
Bit data deliver to shift register caching.
8. an oscillograph, it is characterised in that described oscillograph includes Wave data according to any one of claim 1-7
Decoding apparatus.
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| CN104730306A (en) * | 2013-12-24 | 2015-06-24 | 苏州普源精电科技有限公司 | Automatic decoding threshold setting method and oscilloscope with automatic decoding threshold setting function |
| CN105372468B (en) * | 2014-08-26 | 2019-03-05 | 苏州普源精电科技有限公司 | In the system and method for oscillograph up-regulation entire data decoding function |
| TWI584191B (en) * | 2016-07-26 | 2017-05-21 | 東元電機股份有限公司 | Method for checking control instruction of driving device by using control instruction waveform |
| CN108254606B (en) * | 2016-12-28 | 2022-02-08 | 北京普源精电科技有限公司 | Decoding data processing method and device and oscilloscope |
| CN108226598B (en) * | 2018-01-05 | 2020-11-10 | 深圳市道通科技股份有限公司 | Oscilloscope signal decoding method and device and oscilloscope |
| CN113608001A (en) * | 2021-07-30 | 2021-11-05 | 上汽通用汽车有限公司 | SPI waveform processing method and device |
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| CN101067630A (en) * | 2007-05-17 | 2007-11-07 | 王悦 | Oscilloscope with higher wave-form refresh rate |
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| CN201540324U (en) * | 2009-11-02 | 2010-08-04 | 北京普源精电科技有限公司 | Digital oscilloscope |
| CN102033149A (en) * | 2009-09-17 | 2011-04-27 | 特克特朗尼克公司 | Mixed signal acquisition system for a measurement instrument |
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| CN101067630A (en) * | 2007-05-17 | 2007-11-07 | 王悦 | Oscilloscope with higher wave-form refresh rate |
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